JPS641810B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a shift-type diagnostic circuit that is incorporated in advance into a logic circuit board or an IC in order to test logic circuits. The present invention relates to a diagnostic circuit for diagnosing logic circuits in which registers and counters that require input are added to the scan loop.

[Conventional technology]

2. Description of the Related Art In recent years, as information processing devices and various control devices have become larger and have higher performance, a large number of complex and large-scale logic circuits are being used. On the other hand, due to advances in LSI technology and packaging technology, the circuit packaging density of logic circuit boards has improved significantly, making testing of logic circuit boards extremely difficult and time-consuming.

Generally speaking, testing or diagnosing logic circuit boards involves applying test data and determining the presence or absence of a fault from the logical output results. The disadvantage is that it is not possible to know the detailed internal state of Therefore, one solution is to use a flip-flop inside the circuit to directly set test data or read out the internal state of the circuit by incorporating a shift register mechanism into the logic circuit in advance. A diagnostic method called the shift method is often used.

This shift method uses each flip-flop FF ₀ , FF ₁ ,
...FF _i , ...FF _o are connected in series to create a scan loop with a shift register configuration, and during diagnosis, a shift pulse is applied from the outside to transfer the test data string, that is, scan-in data, into the scan loop. Shift input (called scan in) to
Next, a logical operation is executed based on the test data set in each flip-flop _FF0 to _FF0 in this way, and when the results are set in each flip-flop, they are shifted out as scan-out data (scan-out data). out). By the way, each flip-flop in the scan loop includes a signal circuit for performing the original flip-flop function in each logic circuit and a control circuit for shift register operation.
The shift pulse and the clock for the original flip-flop operation were stopped and only the shift pulse was input.

[Problem that the invention seeks to solve]

Conventionally, in logic circuit diagnosis using the shift method,
There were cases where the diagnosis was performed on the board alone and cases where the diagnosis was performed with the board mounted. In the latter case, if the output of a logic circuit on one board is essential for the operation of a circuit on another board, the clock of that logic circuit will be stopped. In that case, it was necessary to exclude the logic circuit from the scan loop.

For example, if a refresh counter for generating a memory refresh address is placed on one board, and a memory that uses that refresh address is placed on another board, the refresh counter cannot stop the counting clock.

Therefore, even if it is possible to stop the count clock supply to the refresh counter when diagnosing the board alone, as long as there is a possibility of diagnosing the board while it is mounted, each flip-flop that makes up the refresh counter cannot be included in the scan loop, which is a major cause of the inability to increase the proportion of the diagnosable range in the logic circuit, that is, the diagnostic rate.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides clock supply to logic circuits depending on the conditions in which diagnosis is performed, that is, the diagnosis environment, such as diagnosis on a board alone and diagnosis on a board mounted on a device. Regarding flip-flops in logic circuits that change whether they can be stopped or not, it is possible to select whether to include or exclude them from the scan loop, and their configuration is as follows:
In a logic circuit that performs shift-type scan-in and scan-out, the first scan loop that connects a group of flip-flops, which may not be able to stop clock supply even during diagnostic operation depending on the diagnostic environment of the logic circuit, and the first scan loop that is unrelated to the above diagnostic environment. and a second scan loop connected to a group of flip-flops that can stop clock supply during diagnostic operation, and one scan loop connecting the first scan loop and the second scan loop, and a single scan loop connected to the first scan loop and the second scan loop. The second scan loop is switched by an external control signal.

〔Example〕

The details of the present invention will be explained below with reference to Examples.

FIG. 1 shows the configuration of one embodiment of a logic circuit board equipped with a diagnostic circuit according to the present invention.

In the figure, 1 is a logic block that can stop the clock regardless of the diagnostic environment;
2 is a logic block whose clock cannot be stopped depending on the diagnostic environment, 3 is a multiplexer for switching scan out data, 4 is a clock for logic block 1, 5 is input data for logic block 1, 6 is a shift pulse, and 7 is a scan block. 8 is the count clock, 9 is the reset signal, 10 is the test mode signal, 11 is the shift pulse of logic block 2, 12, 13, 18 is the scan-out data of logic block 1, 14 is the logic block 1 and logic 15 is the output data of the logic block 1, 16 is the output data of the logic block 2, 17 is the scan-out data, 19 is an AND circuit, and 20 and 21 are buffers.

Also, 1a, 1b, shown in logic block 1,
1c and 2a, 2 shown in logic block 2.
Reference numerals b and 2c are flip-flops each having a predetermined role in each logic block, and in particular, 2a, 2b and 2c constitute each stage of a refresh counter. These flip-flops also serve as stages of a shift register constituting a scan loop. Terminals Si, So, and Sc in each flip-flop are terminals provided to function as a shift register, where Si represents a shift data input terminal, So represents a shift data output terminal, and Sc represents a shift pulse input terminal.

Flip-flop 1a, 1 of logic block 1
The scan loop consisting of b and 1c is buffer 2
0 to flip-flop 2 of logic block 2
a, 2b, 2c, and further connected to one input terminal of multiplexer 3, and the scan loop of logic block 1 is
It is connected alone to one other input terminal of the multiplexer 3 via a buffer 21. Therefore, by controlling the multiplexer 3, either one long scan loop in which the scan loops in the two blocks of logic block 1 and logic block 2 are cascaded, or only the scan loop in logic block 1 is created. can be selected.

Next, a specific diagnosis operation will be explained.

For example, when diagnosing the illustrated logic circuit board alone, the refresh counter function of the logic block 2 can be temporarily stopped, so the test mode signal 10 is set to "1" and the multiplexer 3
Then, the scan-out data 14 from the scan loop which is a combination of the scan loops of both logic block 1 and logic block 2 is selected. At this time, since the AND circuit 19 is functionalized, the shift pulse 6 is supplied to both logic block 1 and logic block 2. Thereby, the scan-in data 7 can be sequentially input into the scan loop of the logic block 1 and the scan loop of the logic block 2, and the scan-out data 17 can be read out from the multiplexer 3.
This scanout data 17 is used to diagnose logic block 1 and logic block 2.

Next, when each logic circuit board is mounted on a device and a device test is performed, logic block 2 must be removed from the test. In this case, the test mode signal 10 is set to "0". As a result, multiplexer 3 is controlled to select scanout data 13 from the scan loop of logic block 1, and AND circuit 19 is disabled to prevent supply of shift pulses to logic block 2. Therefore, the shift pulse 6 is supplied only to the logic block 1, and the scan-in data 7 is input and the scan-out data 13 is output.
Scanout data 17 from multiplexer 3
It is read as . Logic block 1 is tested using this scanout data 17. During this time, the counting clock 8 or the reset signal 9 is applied to the logic block 2, which operates as a refresh counter and sends out the refresh address as output data 16.

〔Effect of the invention〕

As described above, according to the present invention, flip-flops in a logic circuit are divided into those that can be put into the scan loop and those that cannot be put into the scan loop depending on the diagnostic environment, and by enabling each operation, the flip-flops are always kept in the diagnostic environment. Diagnosis can be performed for the maximum range of logic circuits according to the requirements, and the diagnostic rate can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is an explanatory diagram of a diagnostic circuit using a shift method. In the figure, 1 is a logic block whose clock can always be stopped, 2 is a logic block whose clock cannot be stopped depending on the conditions of the diagnostic environment, 3 is a multiplexer, 4 is a clock, 5 is input data, 6 is a shift pulse, and 7 is scan-in data, 8 is a count clock, 9 is a reset signal, 10 is a test mode signal, 12, 13, 14, 17, 18 are scan-out data, 15, 16 are output data, 1
9 represents an AND circuit, and 20 and 21 represent buffers.

Claims (1)

[Claims] 1. In a logic circuit that performs shift-type scan-in and scan-out, the first scan loop that connects a group of flip-flops that may not be able to stop clock supply even during diagnostic operation depending on the diagnostic environment of the logic circuit, and the above-mentioned diagnostic environment A second scan loop connecting a group of flip-flops that can independently stop clock supply during a diagnostic operation is separately provided, and a single scan loop connecting the first scan loop and the second scan loop; 1. A diagnostic circuit for a logic circuit, comprising means for switching between a single second scan loop and a second scan loop using an external control signal.