JPS642956B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display system using a display device such as a raster scan type CRT.

This invention provides for writing to the refresh memory using the non-display period of the CRT when periodically reading out the contents of the refresh memory and displaying it on a CRT screen while changing the display contents. By using a timing pulse to distinguish between the display period and the non-display period, and confirming the writing performed during the non-display period,
This was done in order to provide a write completion determination method that ensures that the write operation can be performed reliably.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram of a CRT display device that implements a method showing one embodiment of the present invention. However, in the figure, the CRT itself is not shown because it is not directly related to the present invention.

The outline of the CRT display device in this embodiment is as follows.

Information to be displayed is written into the refresh memory 5 via the bus driver 2 by an input source such as a CPU (microprocessor 1). This information includes address information indicating the display position on the CRT screen and character display code information such as ASCII code. This address information is input to the refresh memory 5 through the address decoder 10 and address selector 4.

The refresh memory 5 has addresses corresponding to character display addresses assigned on the CRT screen. Therefore, the refresh memory 5 has a memory capacity capable of storing code information for the total number of characters that can be displayed on a CRT screen.

For example, if the number of characters is 32 characters horizontally and 16 lines vertically,
One page requires a storage capacity of 32 x 16 (bytes). In this embodiment, the refresh memory 5 has a storage capacity of 2048 bytes, and is capable of writing over four pages. Therefore, the address information is 11
It has a bit structure.

Address information in microcomputer systems generally has a 16-bit configuration, so the above
The address decoder 10 converts address information of the CPU, etc. into an address of the refresh memory 5 having an 11-bit configuration, and forms an address signal specifying a readout circuit 11, which will be described later. The address selector 4 is for switching between address information from a CRT controller 3, which will be described later, and address information from an input source such as the CPU 1, and transmitting the same to the refresh memory 5.

Reading the refresh memory 5 is as follows:
Timing pulses (MA) corresponding to character addresses on the CRT formed by the CRT controller 3 are used as address information, and processing is performed sequentially for each character.
This read code information is converted by the pattern generation circuit 6 into a pattern signal in which each character is composed of dots.

This pattern generation circuit 6 is a read-only memory (ROM) in which pixels such as characters are written.
Consisted of. Therefore, by giving the character code to be displayed from the refresh memory 5 to the pattern generation circuit 6, that is, by specifying the character address of the pattern generation circuit 6 and the raster address, the output can be changed. ,
The character pattern signal is synchronized with the raster scan timing.

This pattern output is converted into a serial video signal by a parallel/serial conversion circuit 7. This serial video signal is processed by the video control circuit 8 as a synchronizing pulse (H/
CRT
Characters will be displayed on the screen.

The timing controller 9 has a built-in oscillation circuit, and processes the character clock (CLK), which is the basis of the address timing pulse (MA) of the refresh memory 5, the raster address timing pulse (RA) of the pattern generation circuit 6, and the serial clock. It forms a video clock (VCLK) etc. for obtaining pixel data.

The CRT controller 3 controls various control registers such as a horizontal display character register and a vertical display character register, and a refresh memory 5, in other words,
It consists of a character and line counter that specifies addresses in synchronization with the raster on the CRT screen, a CRT horizontal and vertical synchronization signal generation circuit, a raster control circuit, a cursor control circuit, etc., and a refresh function synchronized with the CRT raster. Address specification of memory 5 (MA), raster specification of pattern generation circuit 6 (RA)
This is used to form the pixel data as described above, as well as to form synchronizing pulses and the like for the CRT. As this CRT controller 3, for example, a monolithic integrated circuit under the trade name "HD46505" can be used.

Note that the readout circuit 11 is used to read out the display timing pulses generated by the CRT controller, and its role will be described later.

In the CRT display device as mentioned above,
For example, as shown in Fig. 2, the number of rasters constituting the display screen section 12 of a CRT in non-interlaced mode is 240, and blanking areas (hatched areas) of 10% each on the top, bottom, left and right sides are provided. The effective display screen 13 shall be configured by providing the following information. This blanking part is used for horizontal and
This is necessary to prevent displayed characters from being displayed off the screen due to variations in vertical drive ability.

In a CRT such as a home television receiver, the horizontal scanning time H is about 63.5 μs. this house,
If the blanking time _t4 is 9.3 μs, the scanning time for forming the display screen 12 is 54.2 μs. Therefore, if blanking parts of 10% t ₁ and t ₂ are provided on the left and right as described above, t ₁ and t ₂ are as follows.
The scanning time t 3 for forming the effective display screen 13 is 5.4 μs, and the scanning time t ₃ is 43.3 μs.

Therefore, per horizontal scanning time H, a display timing pulse (DISPTMG) is generated in which the effective display time _t3 is set to "1" and the other times are set to "0" (blanking).

On the other hand, in the vertical direction, the number of rasters on the display screen 12 is 240, and blanking parts of 10% t ₅ and t ₆ are provided at the top and bottom, so t ₄ , t ₅
is a time corresponding to 24 rasters (24×63.5 μs), and the number of rasters forming the initial display screen 13 is 192.

Therefore, for one display screen V, the above effective display time _t7 is set to "1", and the others are set to "0" (blanking).
A display timing pulse (DISPTMG) is then formed.

FIG. 3 shows a pulse waveform per one display screen obtained by combining the horizontal and vertical display timing pulses. This timing pulse (DISPTMG)
As shown in the figure, when configured in non-interlace mode using an NTSC CRT, 1
The display screen V is 1/60 second, and is a pulse signal having 192 horizontal display timing pulses H and a vertical blanking portion corresponding to 70 horizontal display timing pulses H.

In the vertical blanking section, the number of rasters is 525 in the NTSC system, and the number of rasters is 262.5 in the non-interlaced mode, so the horizontal display timing corresponds to 262.5-192≈70. Of these, 48 pieces are for the above time t ₅ +
t ₆ , and the remaining 22 pieces correspond to the vertical retrace time t ₈ .

In this embodiment, in addition to the blanking period of the CRT, blanking for forming the above-mentioned effective display screen 13 is used to adjust the access timing from the input source such as the CPU when changing the display contents of the CRT. This is what you are trying to allocate. That is,
During the blanking period and retrace period, the CRT display device stops reading the refresh memory, in other words, stops the operation for displaying characters, so flashing may occur in a part of the display screen. The contents of refresh memory can be changed without any changes. Then, the effective display screen 13
By allocating the blanking period for forming the data to the access timing, the time slot can be lengthened and the duration of the rewrite speed can be shortened.

In this case, the above display timing is
Since it is determined by the unilateral operation cycle of the CRT display device, the following problems arise.

For example, a write operation is started from an input source such as a CPU at the timing of the blanking described above,
When data is actually sent to the refresh memory 5, at the display timing, the refresh memory 5 is automatically placed under the control of the CRT controller 3 and no writing is performed. On the other hand, since the CPU and the like complete writing by sending data, a mismatch in display data occurs between the two.

When using a CRT display device for program debugging, if the above writing operation is not performed, you can tell on the display screen that you can write again, but in the case of video games, etc., this cannot be recognized. As a result, the content of the game does not match the program, resulting in malfunctions.

In this embodiment, in order to solve this problem, the above display timing is read out immediately after writing, and since it is a blanking period,
This is intended to determine the end of the write operation.

That is, when changing the contents of the refresh memory 5, the CPU 1 first specifies the address of the read circuit 11, reads the signal (DISPTMG), and determines whether or not it is a write period.
When writable is "0", the address and data of the refresh memory 5 are sent and written. After this write, the read circuit 11 is specified again to read the signal (DISPTMG), and when it is "0", it means that the write operation has been completed, that is, the display timing has not changed during the write operation. The write operation is confirmed with , and the series of write operations is completed.

As described above, in addition to checking the operation using a program (software) such as a CPU, the operation of the reading circuit may be automatically performed in response to a write command.

When the confirmation signal is not obtained, the writing is performed again from the beginning, thereby preventing data mismatch as described above. In this case, the display timing is immediately after the writing is completed, and even if the CPU writes the same thing twice, no problem will occur.

The present invention can be widely used as a refresh memory writing determination method in a CRT display device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram illustrating the display timing of the embodiment of the invention, and FIG. 3 is a waveform diagram of the display timing pulse. . 1...CPU, 2...Bus driver, 3...
CRT controller, 4...address selector,
5... Refresh memory, 6... Pattern generation circuit, 7... Parallel/serial conversion circuit, 8...
...Video control circuit, 9...Timing controller, 10...Address decoder, 11
...readout circuit, 12...display screen section, 13...
...Effective display screen.

Claims (1)

[Claims] 1. A display method for displaying display data on a display device by sequentially sending display data corresponding to a raster to the display device, comprising: a microprocessor; a bus line coupled to the microprocessor; a control means coupled to the bus line to perform display control; a first circuit that supplies the bus line with a timing signal that enables determination of a non-display period indicated by the control means; a storage means for storing information, the non-display period of the display screen of the display device is the only time period in which information can be written to the storage means, and after writing the information to the storage means, the first circuit A display method characterized in that writing completion is determined by checking the state of the .