JPS648338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display control device using a raster scan type display device.

The present invention is intended to enable a CPU (microprocessor) to easily detect a writable period in a refresh memory in which information corresponding to a display screen is written.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram of a CRT display device showing one embodiment of the present invention.

The outline of the CRT display device in this embodiment is as follows.

Information to be displayed is written into the refresh memory 5 by an input source such as the CPU 1 via the bus driver 2. This information includes address information indicating the display position on the CRT screen and character display codes such as ASCII codes.
The above address information is transmitted to the address decoder 10,
It is input to the refresh memory 5 through the address selector 4.

The refresh memory 5 has addresses corresponding to character display addresses assigned on the CRT screen. Therefore, the refresh memory 5 has a memory capacity capable of storing code information for the total number of characters that can be displayed on the CRT screen.

For example, if the number of characters is 32 characters horizontally and 16 lines vertically,
A storage capacity of 32 x 16 bytes is required for each screen. In this embodiment, the refresh memory 5 has a storage capacity of 2048 bytes,
It is possible to write over four screens. Therefore, the address information has an 11-bit configuration.

Generally, the address information in a microcomputer system has a 16-bit configuration, so the address information of the CPU, etc. is converted into a refresh memory address of 11-bit configuration, and an address signal that specifies the readout circuit 12, which will be described later, is formed. This is the address decoder 10 mentioned above.

The address selector 4 will be described later.
Address information from CRT controller 3,
This is for switching address information from an input source such as the CPU 1.

Reading the refresh memory 5 is as follows:
Timing pulses (MA) corresponding to character addresses on the CRT formed by the CRT controller 3 are used as address information, and processing is performed sequentially for each character.
This read code information is converted by the pattern generation circuit 6 into a pattern signal in which each character is composed of dots.

This pattern generation circuit 6 is a read-only memory (ROM) in which pixels such as characters are written.
Consisted of. Therefore, by giving the character code to be displayed from the refresh memory 5 to the pattern generation circuit 6, that is, by specifying the character address of the pattern generation circuit 6 and the raster address, its output can be changed. becomes a character pattern signal synchronized with the raster scan timing.

This pattern output is converted into a serial video signal by a parallel/serial conversion circuit 7. This serial video signal is synthesized by the video control circuit 8 with a synchronization pulse (SYNC) and a display timing pulse (DISPTMG) forming an effective display screen to display characters on the CRT screen.

The timing controller 9 has a built-in oscillation circuit, and controls the address timing pulse (MA) of the refresh memory 5 and the pattern generation circuit 6.
It forms the character lock (CLK), which is the basis of the raster address timing pulse (RA), and the video clock (VCLK) for obtaining serial pixel data.

The CRT controller 3 controls various control registers such as a horizontal display character register and a vertical display character register, and a refresh memory 5, in other words,
Consists of a character and line counter for specifying addresses in synchronization with the raster on the CRT screen, a CRT horizontal and vertical synchronization signal generation circuit, a raster control circuit, a cursor control circuit, etc., and a refresh function synchronized with the CRT raster. Address specification of memory 5 (MA), raster specification of pattern generation circuit 6 (RA)
This is used to form the pixel data as described above, as well as to form synchronizing pulses and the like for the CRT.

As this CRT controller 3, for example, a monolithic integrated circuit under the trade name "HD46505" can be used.

Note that 11 is a timing pulse generation circuit that forms an access timing signal from an input source to the refresh memory 5, which inputs the display timing pulse (DISPTMG), extracts the vertical blanking period, and generates the timing pulse ( STATUS). Reference numeral 12 denotes a readout circuit for reading out this output.

In the CRT display device as mentioned above,
For example, as shown in Figure 3, the number of rasters that make up the display screen section 13 of a CRT in non-interlaced mode is 240, and border areas (shaded areas) of 10% of the screen each on the top, bottom, left and right sides. It is assumed that the effective display screen 17 is configured by providing the following. This border section is necessary to prevent displayed characters from being displayed off the screen due to variations in the horizontal and vertical driving capabilities of the CRT.

In a CRT such as a home television receiver, the horizontal scanning time H is approximately 63.5 MS (milliseconds). If the blanking time _t4 is 9.3 MS, one horizontal scanning time for forming the display screen 13 is 54.2 MS. Therefore, as mentioned above,
Assuming that border portions of 10% t ₁ and t ₂ are provided on the left and right sides, t ₁ and t ₂ are 5.4 MS, and the scanning time (t ₃ ) for forming the effective display screen 14 is 43.36 MS.

Therefore, the CRT controller 3 sets the effective display time (t ₃ ) to "1" and sets the other border times and blanking times (planking time) to "0" per horizontal scanning time (H). This will form the display timing (DISPTMG).

On the other hand, in the vertical direction, the number of rasters on the display screen 13 is 240, and 10% (t ₅ , t ₆ ) border areas are provided on the top and bottom, so t ₅ and t ₆ are as follows.
The time is equivalent to 24 rasters (24×63.5MS), the number of rasters forming the effective display screen 14 is 192, and the time (t ₇ ) is 192×63.5MS.

Therefore, the display timing (DISPTMG) is such that the effective display time (t ₇ ) is set to "1" and the others are set to "0" (blanking) per display screen (V).
will be formed.

This display timing pulse (DISPTMG) is formed as shown in FIG. This timing pulse (DISPTMG) is, as shown in the figure, when configured in non-interlace mode using an NTSC CRT, one display screen (V) is 1/60 seconds, and in this, the horizontal display timing pulse The pulse signal has 192 horizontal display timing pulses (H) and a vertical blanking portion corresponding to 70 horizontal display timing pulses (H).

In the vertical blanking section, the number of rasters is 525 in the NTSC system, and the number of rasters is 525/2 in the non-interlace mode.
The horizontal display timing corresponds to 262.5−192≒70 pieces. Of these, 48 pieces took the above time (t ₅ + t ₆ )
, and 22 times corresponds to the vertical retrace time (t ₃ ).

In this embodiment, the effective display screen 14
The CPU uses blanking timing, which consists of border timing to form and blanking timing, to change the CRT display content.
The purpose of this approach is to allocate access timings from input sources such as . That is, during the above-mentioned blanking period, the CRT display device stops reading the refresh memory, in other words, it stops the operation for displaying characters, so it is possible to read the refresh memory without causing flashing in a part of the display screen. The contents can be changed. In this case, the horizontal blanking period is as short as 20 MS, as is clear from the above, and even if this is an accessible time period, no substantial write operation can be expected from the input source such as the CPU. Therefore, in order to prevent the CPU from performing unnecessary operations, this horizontal blanking period is deleted and only the vertical blanking period (4.4 MS) is used as the access timing.

FIG. 2 is a circuit diagram showing an embodiment of a circuit that erases this horizontal blanking period and forms the access timing signal.

This circuit consists of an inverter (IN) that forms an inverted signal of the above-mentioned display timing signal (DISPTMG), a one-shot multivibrator (OS ₁ ) that forms a "0" level output pulse at the rising timing of this inverter output, and It is composed of a one-shot multivibrator (OS ₂ ) that forms a "0" level output pulse at the rise timing of the output.

The front-stage one-shot multivibrator (OS ₁ ) is a retriggerable one-shot multivibrator to eliminate horizontal blanking, and has a time constant circuit that determines the output pulse width.
Set the values of R ₁ and C ₁ to be longer than the horizontal scanning time (H). Due to these time constants R ₁ and C ₁ , the output pulse is activated one after another before it changes to the "1" level, so the output pulse (OS ₁ ) with horizontal blanking removed is as shown in Figure 4. can get.

The multivibrator (OS ₂ ) at the latter stage is for forming the access timing pulse (STATUS) mentioned above, and the time constant circuits R ₂ and C ₂ provide
A “0” level pulse (OS ₂ ) of approximately 4 MS is formed. Since the one-shot pulse (OS ₁ ) includes the first display period, the one-shot multivibrator (OS ₂ ) is provided to form a true vertical blanking pulse.

As shown in FIG. 1, this timing signal (STATUS) is used as a switching signal for the address selector 4, and is also outputted to the data bus (DATA) via the readout circuit 2. Accordingly, when changing the contents of the refresh memory 5, the CPU or the like first specifies the address of the readout circuit 12, reads out the signal (STATUS), and determines whether writing is possible. When writable (“0”),
Address information and data of the refresh memory 5 are sent and written. After writing, the read circuit 12 is designated again to determine whether writing is possible or not. When the signal (STATUS) is "0", it is confirmed that the write operation has been completed, and a series of operations are performed. The write operation shall be completed.

The above confirmation operation is performed during the blanking period when making a judgment before writing, but when a write operation is performed, it is during the display period and writing may not be performed, so such confirmation operation is performed. It is something that allows you to do this.

When a display device is used for program dayback, etc., if there is a writing error like the one mentioned above, it can be confirmed by the display, but if there is a writing error like the one mentioned above while executing a program in a video game, etc., the content of the game will be affected. Since the program does not follow the program and causes malfunctions, this can be prevented by the above-mentioned simple confirmation operation.

The present invention is not limited to the embodiments described above, and the means for erasing horizontal blanking can be modified in various ways, and the horizontal and vertical pulses can be modified depending on the display character configuration.

The present invention can be widely used in raster scan type CRT display devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a CRT display device showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the timing pulse generation circuit in FIG. 1, and FIG. A diagram illustrating the configuration and timing of a display screen showing one embodiment,
FIG. 4 is an operational waveform diagram of the circuit of FIG. 2. 1...CPU, 2...Bus driver, 3...
CRT controller, 4...address selector,
5... Refresh memory, 6... Pattern generation circuit, 7... Parallel/serial conversion circuit, 8...
...Video control circuit, 9...Timing controller, 10...Address decoder, 11
...Timing pulse generation circuit, 12...Reading circuit, 13...Display screen, 14...Valid display screen.

Claims (1)

[Claims] 1 a microprocessor, a bus line coupled to the microprocessor, a refresh memory in which information to be displayed on a display device is stored, and a vertical blanking period to the refresh memory via the bus line; a flip-flop, which is made accessible by the microprocessor via the bus line to which a control signal is applied, meaning permission to write information in the display; 1. A display control device comprising a display control circuit for forming a synchronization signal for the device, an address signal for the refresh memory, and a control signal for the flip-flop.