JPS643066B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit that achieves high density by terminating a source or drain diffusion junction in an insulator isolation layer.

There is a complementary MOS (hereinafter abbreviated as C-MOS) circuit that uses MOS field effect transistors, and in this circuit, when one transistor is conducting, the other transistor is non-conducting, so the power consumption is extremely small. Although it is expected to operate at high speed and is an excellent circuit format, when integrating it, it is difficult to
It was said that the degree of integration was inferior to that of C-MOS, and this was one of the major problems in integrating C-MOS. C-MOS
Isolation is one of the reasons why they are inferior to single-channel MOS/ICs in terms of integration. That is, C
-For MOS, for example, as shown in Fig. 1, after P diffusion 2 is performed on an N-type silicon substrate 1, an N-channel MOS
The transistor 3 and the P-channel MOS transistor 4 are formed, and the source and drain regions of each transistor are carefully controlled by mask alignment accuracy of substrate regions of opposite conductivity types and lateral expansion due to heat treatment of the P ^- region 2. In consideration, we were forced to design a pattern that guaranteed withstand voltage, and as shown in Figure 1.
The magnitude of L ₁ + L ₂ is the single channel shown in Figure 2.
This is approximately two to three times larger than the MOS/IC spacing L ₃ (this is the spacing that guarantees breakdown voltage).

Therefore, as a method to reduce the area of the isolation part as much as possible, there is a method to perform insulation isolation by etching the substrate and filling it with air isolation or silicon dioxide, but there is still no effective solution. Not given.

Here, the present invention provides an integrated circuit comprising semiconductor regions separated from each other by an insulator isolation layer on the surface of a semiconductor substrate, and in which a source or drain region is formed by terminating a diffusion bond in the insulator isolation layer. The isolation portion is formed in complete contact with the source or drain, thereby dramatically improving the degree of integration of C-MOS.

That is, the surface of the semiconductor substrate is provided with semiconductor regions separated from each other by an insulator isolation layer, and here, silicon gate technology or polycrystalline silicon doped with impurities is deposited and then removed by the distance between the gates. Pre-circuit for source and drain diffusion
By using aligned gate technology to automatically set the source and drain regions (referred to as self-alignment), at least one of the source and drain regions is formed in contact with an insulator isolation layer, increasing the degree of integration. It is something that enhances. This sauce,
If cell alignment of the insulator isolation layer is performed in addition to self-alignment of the drain, complete self-alignment of the isolation layer, source, and drain can be achieved, and the degree of integration can be significantly improved. Self-alignment of the isolation layer is achieved by making the diffusion mask used for low concentration diffusion to form isolated semiconductor regions part of the mask for thermal oxidation for isolation.

The details are described below.

This embodiment uses silicon gate technology and pre-aligned gate technology, and uses a self-alignment method to form the isolation layer.

In FIG. 3, an N-type silicon substrate 1 having a specific resistance of 1 Ω·cm is prepared, and a silicon nitride film 6 having a window 5 defining a separate semiconductor region is formed on the surface of the substrate.

When boron is deposited and diffused, a P ^- region 2 is formed and an oxide film 7 is generated within the window 5. Thereafter, the oxide film 7 is removed by immersing the substrate in a hydrofluoric acid etching solution. The surface concentration of region 2 can be set to approximately 10 ¹⁶ cm ^-3 and its depth can be set to approximately 1 μ.

In FIG. 4, a silicon nitride film 8 of the same type and the same film thickness as the film 6 is grown in a vapor phase, followed by a silicon dioxide film 9, which is patterned as shown in the figure. The silicon dioxide film 9 is within the window 5 and the interval between
L ₄ may be approximately 5μ.

The substrate is immersed in a boiled phosphoric acid solution, and the film 8 is patterned. The film 9 is then removed.

In FIG. 5, the silicon substrate is lightly etched, and in FIG. 6, it is thermally oxidized. The generated isolation layer 10 of silicon dioxide becomes almost parallel to the silicon surface and is flattened, and the PN junction extending on the surface is terminated at the layer 10, forming a nearly flat junction 11. .

Here, the diffusion mask 6 also functions as a mask for thermal oxidation to achieve self-alignment of the isolation layer 10, facilitating positioning and allowing the original window 5 to define the opposite conductivity type region. It is noteworthy.

Next, the silicon nitride films 6 and 8 on the surface are completely removed with the hot phosphoric acid described above, and as shown in FIG. Ru. In this state, a polycrystalline silicon layer 13 containing a large amount of phosphorus is grown in a vapor phase and removed by etching to determine the channel length of the N-channel transistor. A silicon nitride film 14 is formed on the surface as a diffusion mask.

In the process shown in FIG. 8, the film 14, layer 1
3. Pattern the oxide film 12.

Here, boron is diffused to form the source region 15 and drain region 16 of the P channel. Diffusion is performed in an oxidizing atmosphere to oxidize the exposed portions of the polycrystalline silicon 13 and the substrate, forming an insulating film 17.
With this heat treatment, within region 2, polycrystalline silicon layer 1
The phosphorus in 3 is diffused to form a source region 18 and a drain region 19 of an N-channel transistor. Since the diffusion treatment only needs to be performed once, the manufacturing process can be simplified and the reproducibility of manufacturing can be improved, which is particularly preferable. Drain region 19 is adjacent to isolation layer 10 and its diffusion bond is terminated in layer 10 and does not extend to the surface of region 2 . Thus, the junction area of the drain region is reduced, and as a result, the stray capacitance between the drain and the substrate is reduced. This, together with the miniaturization of the transistor element by the above manufacturing method, realizes high-speed operation of C-MOS.

After completing the process shown in FIG. 8, the entire surface mask 14 is removed, and the silicon surface in region 2 is exposed, so that an N-channel gate oxide film is formed there by thermal oxidation.

Thereafter, according to the usual process, electrodes are attached as shown in FIG. 9, and a phosphosilicate glass film 20 is formed as a protective film on the surface.

In this way, the P-channel transistor 4 is formed with a silicon gate, and the N-channel transistor 3 uses the polycrystalline silicon used for source and drain diffusion as a conductor, completely preventing alloy formation between the electrode metal and the silicon substrate. It is formed with a pre-aligned gate structure, and due to the circuit configuration, the source of the transistor 3 is connected to the substrate.

Although only three transistor elements are shown in the drawing, the transistor elements 3 and 4 are formed in close contact with the isolation layer 10 by employing the above-mentioned self-alignment method, and the diffusion regions of adjacent elements, for example 19 and 15 are approximately on the surface
Even though they are separated by only 10μ, the degree of integration in C-MOS has been significantly improved.

The following embodiment uses silicon gate technology to form N-channel and P-channel transistors.

In the step shown in FIG. 10, the silicon substrate obtained in the steps shown in FIGS. 3 to 6 is prepared.

A silicon substrate having such an isolation layer can also be obtained by performing P ^- diffusion to form region 2 after forming the isolation layer 10, but during this diffusion, the surface of region 2 is not covered by normal diffusion. An oxide film is formed, and when this oxide film is removed, the layer 10 may be removed at the same time, so it cannot be said that this is a process with good reproducibility and reliability.
However, using the self-alignment method of FIGS. 3-6, layer 10 and a different type of diffusion mask can be removed independently without fear of etching away layer 10, which is reproducible and reliable. It is highly sexual.

After removing the diffusion mask on the surface, the silicon substrate is oxidized to form a gate oxide film 21, and then a polycrystalline silicon layer 22 is grown on the entire surface. Furthermore, a silicon dioxide layer 23 is generated, and this is made of P.
The gate spacing of the channel and the area of region 2 are left as is.

In the process shown in FIG. 11, first, layer 22 is patterned using layer 23 as a mask, and then a resist is deposited in the area of region 2 and gate oxide film 21 is patterned. At this time, layer 2 on the P channel side
The oxide film on 2 is also removed at the same time. After the resist is removed, boron is diffused. Through this diffusion, boron diffuses into polycrystalline silicon and the silicon substrate,
A source 15 and a drain 16 on the P channel side are formed, as well as a silicon gate. 24
is an oxide film produced by diffusion. Next is the formation of the N channel side. Leave the resist in the gate spacing,
The layer 22 is etched using the layer 23 as a mask, and then the gate oxide film 21 is patterned by covering areas other than the region 2 with resist. Layer 23 at the same time
remove.

Here, as shown in FIG. 12, phosphorus is diffused to form a silicon gate, a source 18, and a drain 19.

After that, wiring was done in the same way as the conventional method, and C-
Get MOS.

In this embodiment, as in the previous example, the source, drain, and gate are self-aligned, and the diffusion regions of adjacent transistors are separated from each other by layer 10, which facilitates pattern design.

The next embodiment uses pre-aligned gate technology.

In the step shown in FIG. 13, the silicon substrate obtained in the steps shown in FIGS. 3 to 6 is prepared. Next, polycrystalline silicon doped with a large amount of boron is deposited on the entire surface and then photo-etched to form a source electrode 25 and a drain electrode 26. Both of these may extend into the isolation layer 10. Next, polycrystalline silicon doped with a large amount of phosphorus is deposited on the entire surface and photo-etched to form the source electrode 27,
A drain electrode 28 is formed.

Figure 14 shows that boron and phosphorous are diffused into silicon in one diffusion process, and the source 1 of the P channel is
5. It is a sectional view when the drain 16 and the source 18 and drain 19 of the N channel are formed.

The oxide film on the silicon surface produced during diffusion can serve as each gate insulating film. Next, install each electrode to complete the process as shown in the figure.
An aligned gate MOS transistor and an N-channel pre-aligned gate MOS transistor are formed.

In this manner, an integrated circuit consisting of an insulated gate field effect transistor having source and drain diffusion regions is formed in a self-aligned manner on a semiconductor substrate having semiconductor regions separated from each other by an insulator isolation layer. Then, the source or drain diffusion region can be formed in close contact with the isolation region, and therefore, instead of L ₁ +L ₂ in the conventional arrangement shown in FIG.
The width of the insulator isolation layer is sufficient, and the degree of integration can be significantly improved.Furthermore, the insulator isolation layer 10 can also be formed in a self-aligned manner by the steps shown in FIGS. 3 to 6. For example, a PN junction extending on the surface can be reliably converted into an insulator, making its fabrication easy and reproducible.

As explained above, according to the present invention, CMOS
In an integrated circuit device, high integration can be achieved by shortening the distance between a P channel transistor and an N channel transistor. Furthermore, C-
In the case of MOS structure, P channel transistor and N
A PNPN structure is formed between the channel transistor and latch-up is likely to occur if both transistors are brought too close together, but if they are separated using insulator isolation as in the present invention, the lateral PNPN structure is particularly prone to latch-up. This prevents the formation of latches, resulting in the effect that latch-ups are less likely to occur.

[Brief explanation of drawings]

Figure 1 is a partial cross-sectional view of a conventional complementary MOS integrated circuit, and Figure 2 is a conventional single channel.
Partial cross-sectional views of MOS/IC, FIGS. 3 to 9 are complementary diagrams according to an embodiment of the present invention.
Figure 3 shows the manufacturing process of MOS/IC.
Cross-sectional view of the substrate after P ^- diffusion into the type silicon substrate,
Figure 4 shows the formation of a nitride film after opening the P ^- diffusion window.
Next, a cross-sectional view of the substrate on which an oxide etching mask was formed, FIG. 5 is a cross-sectional view of the substrate on which silicon was lightly etched using a nitride film, FIG. 6 is a cross-sectional view of the substrate after thermal oxidation, and FIG. A cross-sectional view of a substrate in which a nitride film on the surface is removed, a gate insulating film is formed, this is patterned, phosphorus-doped polycrystalline silicon is formed, this is removed at the gate interval, and the surface is covered with a nitride film, Fig. 8 is a cross-sectional view of a substrate patterned with polycrystalline silicon for self-alignment, Fig. 9 is a partial cross-sectional view of a completed MOS IC, and Figs. 10 to 12 are other embodiments of the present invention. This shows the manufacturing process of a complementary MOS/IC according to an example. Figure 10 shows a substrate in which a gate oxide film is formed on the substrate shown in Figure 6, a polycrystalline silicon layer is formed, and a silicon dioxide mask is further provided. Figure 11 is a cross-sectional view of a substrate with one silicon gate formed to form the source and drain, and Figure 12 is a cross-sectional view of the completed substrate with the other silicon gate formed and the source and drain formed. Figures 13 to 14 show the manufacturing process of a complementary MOS/IC according to another embodiment. Figure 14 shows a polycrystalline silicon layer containing various impurities applied to the substrate shown in Figure 6. Cross-sectional view of the substrate, 1st
FIG. 4 is a cross-sectional view of the substrate which was subsequently subjected to diffusion treatment and wiring. In the drawing, 1 is a silicon substrate, 2 is a P ^- region,
3 is an N-channel transistor, 4 is a P-channel transistor, 6, 8, and 14 are silicon nitride films,
9 is a silicon dioxide film, 10 is an oxide isolation layer, 12 and 21 are gate oxide films, 13 is a phosphorous-doped polycrystalline silicon layer, 15 and 18 are source regions, 16 and 19 are drain regions, and 22 is a Polycrystalline silicon layer, 25 and 27 are source electrodes, 2
6 and 28 are drain electrodes.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, an insulator isolation layer formed on the semiconductor substrate with a desired pattern, and a PN junction that terminates in the insulator isolation layer is formed with the semiconductor substrate. and an element in which at least a portion of a junction in each of the semiconductor substrate and the opposite conductivity type region terminates in the insulator isolation layer.
MOS integrated circuit device.