JPS643364B2 - - Google Patents
Info
- Publication number
- JPS643364B2 JPS643364B2 JP56053412A JP5341281A JPS643364B2 JP S643364 B2 JPS643364 B2 JP S643364B2 JP 56053412 A JP56053412 A JP 56053412A JP 5341281 A JP5341281 A JP 5341281A JP S643364 B2 JPS643364 B2 JP S643364B2
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- voltage
- operational amplifier
- circuit
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明はバイアス回路に関し、その目的とする
ところはたとえば増幅器の安定な動作状態への立
上り時間を短縮できるようなバイアス回路を提供
することにある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bias circuit, and an object of the present invention is to provide a bias circuit that can shorten the rise time of an amplifier to a stable operating state, for example.
従来のバイアス回路について第１図を例に採つ
て説明すると、R1，R2は電源端子Ｔとアース間
に直列接続されて介在されたバイアス設定用抵抗
であり、その接続点の電位V1は電源電圧VCCの1/
２となるように設定されている。R3は上記抵抗
R1，R2相互の接続点と演算増幅器OAの正側入力
端との間に接続された電流オフセツトのキヤンセ
ル用抵抗、RS，Rf，CSは上記演算増幅器OAの出
力端子TOUTとアース間に直列に接続されて介在
された抵抗とコンデンサで、抵抗RS，Rfはその
相互接続点が演算増幅器OAの負側入力端に接続
されてゲイン設定用として機能し、コンデンサCS
はバイアス用コンデンサである。Ｓは入力信号
源、Ci，CBはカツプリング，デカツプリングコン
デンサである。そこで上記回路に電源電圧VCCが
印加された場合、電位V1は直ちに上記VCCの1/2
に立上がる。しかしながら、演算増幅器OAの負
側入力端とアース間の電位V2は、コンデンサCS
に電流IOが流れその充電が完了するまでは安定し
た値にならない。この場合、上記充電回路の充電
時定数はRf，CSで与えられ、Rfが大きくなつた
り、CSが大きくなつたりすると増幅器が安定な動
作状態に至るまでの時間がさらに長くなる。 To explain a conventional bias circuit using FIG. 1 as an example, R 1 and R 2 are bias setting resistors connected in series between the power supply terminal T and the ground, and the potential V 1 at the connection point is is 1/of the supply voltage V CC
It is set to be 2. R 3 is the resistance above
Current offset canceling resistors are connected between the connection point of R 1 and R 2 and the positive input terminal of the operational amplifier OA, and R S , R f , and C S are the output terminals T OUT of the operational amplifier OA. The interconnection point of the resistors R S and R f is connected to the negative input terminal of the operational amplifier OA and functions as a gain setting, and the resistors R S and R f are connected in series between S
is a bias capacitor. S is an input signal source, and C i and C B are coupling and decoupling capacitors. Therefore, when the power supply voltage V CC is applied to the above circuit, the potential V 1 immediately becomes 1/2 of the above V CC .
stand up. However, the potential V 2 between the negative input terminal of the operational amplifier OA and ground is the capacitor C S
A current IO flows through the terminal, and the value does not reach a stable value until the charging is completed. In this case, the charging time constants of the charging circuit are given by R f and C S , and as R f becomes larger or C S becomes larger, the time it takes for the amplifier to reach a stable operating state becomes longer.
そこで本発明はこのような従来の欠点を解消す
るものであり、以下にその一実施例について第２
図とともに説明する。第２図の回路は第１図の回
路とほぼ同じであるので、同一構成部分について
は同一番号を付して説明を省略する。 Therefore, the present invention is intended to eliminate such conventional drawbacks, and a second embodiment of the present invention will be described below.
This will be explained with figures. Since the circuit in FIG. 2 is almost the same as the circuit in FIG. 1, the same components are given the same numbers and their explanation will be omitted.
第２図の回路で第１図の回路と異なる点は、演
算増幅器OAの出力端と負入力端との間に抵抗Rf
を接続し、上記負入力端とアース間に抵抗RSと
コンデンサC2を直列接続し、この抵抗RSとコン
デンサC2相互の接続点と電源端子との間にコン
デンサC1を接続し、コンデンサC1，C2のみで電
源電圧を分割した電圧V2でもつてバイアス設定
をし、この電圧V2を先の電圧V1と同じになるよ
うにした点にある。 The difference between the circuit in Figure 2 and the circuit in Figure 1 is that a resistor R f is connected between the output terminal and the negative input terminal of the operational amplifier OA.
Connect a resistor R S and a capacitor C 2 in series between the above negative input terminal and ground, and connect a capacitor C 1 between the connection point of this resistor R S and capacitor C 2 and the power supply terminal. The advantage is that the bias is set using voltage V 2 , which is obtained by dividing the power supply voltage only by capacitors C 1 and C 2 , and this voltage V 2 is made to be the same as the previous voltage V 1 .
このような構成では、電源を投入した時、電圧
V1，V2がほとんど同時に立上り、抵抗及びコン
デンサの定数誤差によつて生じたV1とV2の電位
差が、抵抗Rfを通した充電電流で０になるよう
に補正されるので、電源を投入してから増幅器
OAが安定な動作状態に至るまでの時間が大幅に
短縮される。 In such a configuration, when the power is turned on, the voltage
V 1 and V 2 rise almost simultaneously, and the potential difference between V 1 and V 2 caused by the constant error of the resistor and capacitor is corrected to 0 by the charging current passing through the resistor R f , so the power supply and then turn on the amplifier.
The time it takes for OA to reach a stable operating state is significantly reduced.
なお上記実施例のバイアス回路は増幅器の一部
として適用したものであるが、これに限らず種々
の回路のバイアス設定に利用することができる。 Although the bias circuit of the above embodiment is applied as a part of an amplifier, the present invention is not limited to this and can be used for bias setting of various circuits.
以上説明したように本発明のバイアス回路は電
源電圧をコンデンサのみで分割した電圧でもつて
バイアス設定を行なうように構成したものであ
り、電源を投入してから所定のバイアス電圧が得
られるまでの時間が非常に短かくできるので、た
とえば増幅器のバイアス回路として用いれば、増
幅器が安定動作状態になるまでの時間を大幅に短
縮することができる。 As explained above, the bias circuit of the present invention is configured to perform bias setting using a voltage obtained by dividing the power supply voltage only by a capacitor, and the time from turning on the power until obtaining the predetermined bias voltage is Since it can be made very short, for example, if used as a bias circuit for an amplifier, the time it takes for the amplifier to reach a stable operating state can be significantly shortened.
第１図は従来のバイアス回路を示す増幅器の回
路図、第２図は本発明の一実施例におけるバイア
ス回路を示す増幅器の回路図である。
OA……演算増幅器、C1，C2……バイアス設定
用コンデンサ。
FIG. 1 is an amplifier circuit diagram showing a conventional bias circuit, and FIG. 2 is an amplifier circuit diagram showing a bias circuit in an embodiment of the present invention. OA...Operation amplifier, C1 , C2 ...Bias setting capacitor.
Claims (1)
力端の間に負帰還抵抗を設けた演算増幅器と、電
源端子とアース間に直列に接続され、分割電圧で
上記演算増幅器の正入力端をバイアスするための
２本の抵抗と、上記電源端子とアース間に直列に
接続され、分割電圧で上記演算増幅器の負入力端
をバイアスするための２ケのコンデンサとを備
え、前記抵抗の分割電圧に等しくなるように前記
コンデンサの分割電圧を設定したことを特徴とす
るバイアス回路。1. An operational amplifier having a positive input terminal and a negative input terminal, with a negative feedback resistor provided between the negative input terminal and the output terminal, and connected in series between the power supply terminal and the ground, and the voltage of the above operational amplifier with a divided voltage. Two resistors for biasing the positive input terminal, and two capacitors connected in series between the power supply terminal and the ground for biasing the negative input terminal of the operational amplifier with a divided voltage, A bias circuit characterized in that the divided voltage of the capacitor is set to be equal to the divided voltage of the resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56053412A JPS57168508A (en) | 1981-04-08 | 1981-04-08 | Bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56053412A JPS57168508A (en) | 1981-04-08 | 1981-04-08 | Bias circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57168508A JPS57168508A (en) | 1982-10-16 |
| JPS643364B2 true JPS643364B2 (en) | 1989-01-20 |
Family
ID=12942110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56053412A Granted JPS57168508A (en) | 1981-04-08 | 1981-04-08 | Bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57168508A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61161010A (en) * | 1985-01-09 | 1986-07-21 | Nec Corp | Feedback type amplifier |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS494606U (en) * | 1972-04-13 | 1974-01-16 | ||
| JPS5325337A (en) * | 1976-08-23 | 1978-03-09 | Hitachi Ltd | Amplifier circuit |
-
1981
- 1981-04-08 JP JP56053412A patent/JPS57168508A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57168508A (en) | 1982-10-16 |
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