JPS643379B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulator equipped with an automatic equalizer that compensates for distortion in a transmission path.

Some data modulation and demodulation devices (hereinafter referred to as modems) are equipped with an automatic equalizer for the purpose of automatically equalizing distortion that varies from transmission path to transmission path and fluctuations in distortion for the same transmission path. When data is transmitted between modems equipped with automatic equalizers, the transmitting modem transmits a learning pattern to the receiving modem prior to data transmission. An automatic equalizer provided in the modem on the receiving side calculates the distortion of the transmission path based on this learning pattern and compensates for this distortion within the transmission band.

By the way, in conventional modems, the automatic equalizer starts learning from the moment the carrier detection signal output from the carrier detection circuit turns on. That is, from the time the level of the received carrier exceeds the carrier detection level specified by the modem, the demodulator performs learning processing assuming a turn-on sequence. However, in such a demodulator, if the input noise level exceeds the carrier detection level or a momentary line interruption occurs and the carrier detection signal changes from off to on, the modem will detect signals unrelated to the learned pattern. This caused the automatic equalizer to malfunction. In particular, automatic equalizers with increased equalization sensitivity, such as those used in high-speed modems, have the disadvantage that errors are magnified and it takes a long time to return to normal operation. Ta.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a demodulator that can prevent malfunctions of an automatic equalizer.

In the present invention, the demodulator is provided with a turn-on sequence detection circuit for detecting a turn-on sequence,
The above-mentioned object is achieved by causing the automatic equalizer to perform the learning process after the turn-on sequence is detected.

The present invention will be explained in detail with reference to Examples below.

FIG. 1 shows the configuration of the main parts of a demodulator equipped with an adaptive automatic equalizer. The main parts of this demodulator include a memory 1 for temporarily storing received signals;
A product-sum circuit 2 that calculates an equalized output based on the received signal stored in the memory 1, a judgment circuit 3 and a learning judgment circuit 4 that judge the equalized output, a switch 5 that selects the judgment output, and a switch 5 that selects the judgment output. a subtracter 6 for calculating the difference between the determined output and the equalized output; a correlator 7 for calculating the correlation between the output of the subtracter 6 and the received signal; a coefficient unit 8 for adjusting the gain of the signal output from the correlator 7;
It is comprised of a memory 9 that rewrites the coefficients of the equalizer based on the signal output from the coefficient multiplier 8, and a turn-on sequence detection circuit 10 that detects a turn-on sequence, changes the gain of the coefficient multiplier 8, and switches the switch 5.

Now, when a transmission side modem (not shown) starts transmitting a carrier, a carrier detection circuit (not shown) detects its arrival and starts the operation of an automatic equalizer. First, memory 1 consists of shift registers.
temporarily stores the received signals sampled at the Nyquist rate and supplied to the input terminal 11 in a number corresponding to the order of the equalizer. These received signals are then sequentially supplied to the product-sum circuit 2.

The product-sum circuit 2 includes a multiplier 2A that calculates the product of the received signal using coefficients set in the memory 9, a memory 2B that temporarily stores the calculated product, and a memory and the product similarly calculated for the next received signal. It is composed of an adder 2C that adds the values accumulated in 2B. Therefore, when received signals sampled in a number corresponding to the order of the equalizer are supplied to the product-sum circuit 2, the sum of the products of each received signal is stored in the memory 2B. The sum of the products of the respective received signals obtained in this manner is supplied as an equalized output to the determination circuit 3, the learning determination circuit 4, and the subtracter 6.

By the way, if the transmitting modem in this embodiment performs data transmission using the 4-phase phase modulation method,
The spatial arrangement of each signal point corresponding to each type of modulation phase is as shown in FIG. The determination circuit 3 performs a predetermined complex operation and determines a signal point corresponding to the input equalized output. For example, if the equalized output corresponds to the first quadrant, the determination circuit 3 supplies a determination result representing the signal point 21 to the normally closed contact NC of the switch 5. Similarly, the equalized outputs are the second, third, and fourth outputs, respectively.
If the signal points correspond to the respective quadrants, the determination circuit 3 supplies the determination results representing the signal points 22, 23, and 24 to the normally closed contact NC.

On the other hand, the learning determination circuit 4, which also receives the equalized output, makes an optimal determination for a predetermined turn-on sequence. For example, in the turn-on sequence defined in CCITT recommendation V27bis/ter, an equalizer adjustment pattern of 0 degrees to 180 degrees two phases is transmitted. Therefore, if signal point 21 is taken as a reference, only the input corresponding to signal point 21 or signal point 23 exists in the turn-on sequence. In this case, the learning judgment circuit 4 detects both signal points 2
It is sufficient to use the perpendicular bisector 25 of 1 and 23 as the determination boundary and determine in which region the equalized output exists. The determination result regarding the signal point 21 or 23 thus obtained is supplied to the normally open contact NO of the switch 5.

In this way, the operation of the switch 5, which is supplied with two types of determination results, is controlled by the turn-on sequence detection circuit. The turn-on sequence detection circuit 10 is composed of a plurality of band filters that receive the received signal and a logic circuit that turns on and off the detection signal based on the signals output from these band filters, and determines the spectral density of the received signal. Perform analysis. If this substantially matches the spectral density of the synchronization signal in the turn-on sequence, a detection signal is output.

If the turn-on sequence is now started, the switch 5 is operated by the detection signal output from the turn-on sequence detection circuit 10, and the determination result of the learning determination circuit 4 is supplied to the subtracter 6. The subtracter 6 calculates the error between this determination result and the equalized output, and supplies the calculated result to the correlator 7 as an error signal. The correlator 7 calculates the correlation between the error signal and the received signal stored in the memory 1 and outputs a correction signal for correcting the coefficients of the equalizer. The correction signal is supplied to a coefficient unit 8. In this state where the coefficient multiplier 8 is being supplied with the detection signal, it increases its gain and supplies a signal to the memory 9 for making a significant correction. The memory 9 corrects the stored equalizer coefficients based on this signal. In this way, in the turn-on sequence, the gain of the coefficient multiplier 8 is set large, so that learning can be accomplished at high speed.

On the other hand, when the turn-on sequence ends and data transmission begins, the detection signal output from the turn-on sequence detection circuit 10 is disconnected. In this state, the switch 5 has recovered, and the judgment circuit 3
The determination result output from the subtracter 6 is supplied to the subtracter 6. Therefore, automatic equalization is performed based on this determination result. In this case, the gain of the coefficient multiplier 8 is lowered to an extent that corresponds to gradual fluctuations in line conditions.

Now, suppose that a momentary line interruption occurs while data is being transmitted in this manner. The carrier detection circuit stops the operation of the automatic equalization circuit when a carrier disconnection is detected. Then, when the carrier is detected again, the automatic equalization circuit is activated. In this case, unlike the case where new data transmission is started, the turn-on sequence detection circuit 10 does not output a detection signal. Therefore, the inconvenience of aggravating errors in received data due to malfunction of the automatic equalizer does not occur. Similarly, when the carrier detection circuit temporarily detects the arrival of a carrier due to noise during a time when no data transmission is being performed, the turn-on sequence detection circuit 1
0 does not output a detection signal. Therefore, in this case as well, the automatic equalizer will not malfunction assuming the turn-on sequence, and there is no possibility that its characteristics will be disturbed.

As described above, according to the present invention, by detecting the carrier, the stability of the equalizer is improved compared to the conventional demodulator that performs assumed learning. Therefore, it is highly effective as a countermeasure against instantaneous line interruptions when used on noisy lines or when transmitting carriers for long periods of time on specific communication lines or dedicated lines.

In the embodiment, a demodulator equipped with an adaptive automatic equalizer has been described, but it goes without saying that the present invention can be similarly applied to a demodulator equipped with a preset automatic equalizer. In the case of the latter demodulator, a reference code generator that generates a reference code may be used instead of the learning determination circuit.

It goes without saying that the turn-on sequence detection circuit can be changed as appropriate depending on the type of turn-on sequence. Of course, even in the case of the same turn-on sequence as in the embodiment, the present invention is not limited to a circuit that utilizes spectral density, and various circuits such as a circuit that utilizes the output of an equalizer can be used. In the modem using the automatic equalizer of the present invention, it is also effective to preset a turn-on sequence that facilitates detection.

[Brief explanation of drawings]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a block diagram showing the main parts of a demodulator equipped with an adaptive automatic equalizer, and FIG. FIG. 3 is a spatial arrangement diagram of different types of signal points. 3... Judgment circuit, 4... Learning judgment circuit, 5...
...Switch, 10...Turn-on sequence detection circuit.

Claims (1)

[Claims] 1 A carrier detection circuit that detects the arrival of a carrier, a turn-on sequence detection circuit that detects the arrival of a turn-on sequence sent from the transmitting modem prior to data transmission, and a carrier detection circuit that detect the arrival of a carrier. When the turn-on sequence detection circuit detects the arrival of a turn-on sequence in the state, equalization of the turn-on sequence consists of increasing the equalization coefficient correction sensitivity and detecting an equalization error signal corresponding to specific data of the transmitted data. and an automatic equalizer that performs automatic equalization without depending on the equalization of the turn-on sequence when the turn-on sequence detection circuit does not detect the arrival of the turn-on sequence while the carrier detection circuit detects the arrival of the carrier. A demodulator comprising: