JPS644688B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control circuit. In particular, a variable gain amplifier, an error detection circuit that generates a first signal indicative of the difference between the output of the variable gain amplifier and a reference level, and an error detection circuit that integrates the first signal to generate a second signal; The present invention relates to an automatic gain control circuit including a loop filter having an integrator that controls the gain of a variable gain amplifier according to a signal of the present invention.

Conventionally, in such automatic gain control circuits using analog circuits, the time constant of the integrating circuit included therein has been fixed to a constant value. Therefore, if for some reason no signal is present for a period longer than this time constant, the gain of the variable gain amplifier will fluctuate to a very large value. This often causes inconvenience in the following cases: For example, when such an automatic gain control circuit is used in a communication line receiving device, if there is a momentary interruption of the input signal that is longer than the time constant of the integrating circuit, the gain of the automatic gain control circuit will fluctuate to a very large value. , when it receives the input signal again, it outputs a very high level signal. This phenomenon also occurs when reception is temporarily interrupted for transmission on a half-duplex line. In a two-wire half-duplex line, when a transmitting end starts transmitting, the receiver's automatic gain control circuit at that transmitting end receives a high-level transmission signal, so the gain of the automatic gain control circuit is set very low. It will be done. In addition, in a demodulator that receives and demodulates a data signal such as a facsimile signal, in order to adapt each device such as an automatic equalizer included in the demodulator to line characteristics, for example, Receive a predetermined training sequence specified in the International Telegraph and Telephone Consultative Committee (CCITT) Recommendations V.20bis/ter and V.29, etc. The automatic gain control circuit must respond quickly to the first alternation included in this training sequence;
Steady-state conditions such as the binary random step following alternation and the subsequent reception of data signals must be immune to momentary noise that may be contained in those signals. Therefore, such a gain control circuit is
At the beginning of the training sequence, the time constant of the integrator circuit is set short so that it responds quickly, and in a steady state, the time constant is set long so that it operates slowly.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to overcome the drawbacks of the prior art and to provide an automatic gain control circuit in which the time constant of the integrating circuit is variable.

Another object of the present invention is to provide an automatic gain control circuit that can maintain the gain.

These objectives are achieved by an automatic gain control circuit according to the present invention as follows. That is, this automatic gain control circuit is inserted between a storage means for temporarily storing the level of the first signal, an error detection circuit and an integrator, and a first gain control circuit that connects the error detection circuit to the storage means. and a second state in which the integrator is connected to the storage means, the switching means being configured to vary the frequency of switching between the first and second states. The time constant of the integrator is made variable by this, and the gain of the variable gain amplifier is maintained by stopping this switching.

Such storage means and switching means are realized by a switch capacitor.

Next, an embodiment of an automatic gain control circuit according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an example in which the automatic gain control circuit according to the present invention is applied to a demodulator that receives and demodulates a line signal such as a facsimile signal. In the figure, this demodulator includes a bandpass filter BPF connected to a terminal 10 that receives a line signal from a communication line, and an output 1 of this filter BPF.
2, and a multiplier MLT1, one input of which is connected to the output 14 of the automatic gain control circuit AGC. this multiplier
An oscillator OSC is connected to the other input 16 of MLT1, and a low-pass filter LPF is connected to the output 18 of multiplier MLT1. filter
An automatic equalizer AAE is connected to the output 20 of the LPF,
The automatic equalizer AAE has an output terminal 22 for generating an equalized data signal.The details of the demodulator shown in FIG. 1 are omitted as they are not directly relevant to the understanding of the present invention. The line signal transmitted through the communication line has unnecessary noise in the band removed by the filter BPF, and is made into a signal at a constant level by the automatic gain control circuit AGC. This constant level signal is demodulated into a baseband signal by the oscillator OSC, multiplier MLT1, and low-pass filter LPF, and is then demodulated by the equalizer AAE that automatically adapts to the line characteristics.
The signal is equalized by , and output to the high frequency 22 as an equalized analog data signal.

However, when first receiving a data signal such as a facsimile signal, such a demodulator is
It is optimized by a predetermined training sequence specified in V.27bis/ter and V.29.
As is well known, the beginning of this training sequence is an alternation of alternating 0 and 1 symbols, but the automatic gain control circuit AGC included in the demodulator quickly adjusts to the first symbol of this alternation. We must respond. Therefore, in this case, the response time, ie, the time constant, of the automatic gain control circuit AGC needs to be shortened. Furthermore, after the binary random step that follows this alternation, the time constant must be made long so that the automatic gain control circuit AGC does not respond to instantaneous noise contained in the line signal. This also applies to the data signal reception operation after the training sequence.

The automatic gain control circuit AGC shown in Fig. 1 has a function that satisfies these requirements, and the details are explained in the
This will be explained with reference to the figures.

FIG. 2 is a circuit diagram showing details of the automatic gain control circuit AGC, in which a variable gain amplifier VGA is connected between leads 12 and 14 shown in FIG. A full-wave rectifier FWR is connected to lead 14, and its output 100 is connected to operational amplifier OP2 via resistor RA1.
Connected to the inverting input (+) of the amplifier OP
A reference voltage REF is supplied to the inverting input (-) of the amplifier 2 via a resistor RA2, and is also connected to the output 102 of the amplifier via a capacitor CA and a resistor αRA. Resistors RA1 and RA2 have the same value, and resistor αRA has a value α times the resistance value of resistor RA1 or RA2. Further, the non-inverting input (+) of the amplifier OP2 is grounded. These operational amplifier OP2, resistors RA1, RA2 and αRA,
The circuit consisting of the capacitor CA adds the voltage V ₁ at the output 100 of the full-wave rectifier FWR to the reference voltage REF and multiplies the loop gain α, and the capacitor CA also functions as a low-pass filter.

The output 102 of the operational amplifier OP2 is connected to one contact 104 of the analog switch SW, and the other contact 106 is connected to the inverting input (-) of the operational amplifier OP1. The inverting input of amplifier OP1 is connected via capacitor C to its output 108, which is connected to the gain control terminal of variable gain amplifier VGA.

A terminal 110 of the switch SW is grounded via a capacitor CS. This will cause the switch SW to
and capacitor CS is "switch capacitor"
Configure. Further, an integrator 111 is formed by the operational amplifier OP1, the capacitors C and CS, and the switch SW. This integrator 111 functions as a loop filter.

The control lead 112 of the switch SW is the frequency divider DIV
One input 114 of this frequency divider DIV is connected to the output of an AND gate 116, and the other input 118 is supplied with a time constant control signal TC. One input 120 of AND gate 116
is supplied with a clock f _C , and the other input 122 is supplied with a holding signal HOLD via an inverter 124 . Control signals such as the holding signal HOLD and the time constant control signal TC are supplied from a training sequence control device (not shown). The frequency divider circuit DIV is a circuit that divides the frequency of the clock f _C supplied to the input 114 by 1/n and outputs the frequency f _S to the output 112. This frequency division ratio n is the time constant control of the lead 118. Can be changed by signal TC.

The analog switch SW performs a switching operation in response to a control signal f _S supplied to the lead 112. That is, the capacitor CS connected to the terminal 110 of the switch SW is connected to the inverting input (-) of the operational amplifier OP1 through the contact 106,
Output 10 of operational amplifier OP2 through contact 104
2, and this operation is repeated at the frequency _fS . Therefore, the frequency f _S of this capacitor CS
The equivalent resistance R due to switching at is R=1/CS・f _S. Therefore, the time constant T of the integrator 111 is T=CS=C/CS·f _S. As mentioned above, the switching frequency f _S of the lead 112 is the clock f _C divided by n, so f _S = f _C /n, and therefore the time constant T of the integrator 111 is T = Cn/ It becomes CS・f _C. Since the frequency division ratio n is variable by the time constant control signal TC, the time constant T of the integrator 111 can be changed by the time constant control signal TC.

In operation, the full-wave rectifier FWR adjusts the output voltage V ₀ at the output 14 of the variable gain amplifier VGA.
Full-wave rectifier and lead its negative half-wave V ₁ 100
, and V ₀ =−|V ₁ |. capacitor ca
As mentioned above, functions as a low-pass filter and removes the alternating current component of this voltage _V1 . Therefore, it functions as part of the loop filter of the AGC loop. The operational amplifier OP2 adds the voltage on the lead 100 and the reference voltage REF, and outputs the sum multiplied by the loop gain α to the output 102 as a voltage V ₂ . Therefore, this circuit has a signal level error detection and multiplication function that calculates the difference between the average level of the output voltage V ₀ of the lead 14 and the reference voltage REF, and adds the loop gain α to this difference. lead 1
02 voltage V ₂ is integrated by an integrator 111 having a time constant T determined by the frequency f _S of the lead 112, and outputted to the lead 108 as an amplification factor control signal V _G. The summing gain amplifier VGA is configured such that its gain increases as the voltage of the amplification factor control signal V _G increases. If a gain amplifier
If the gain of the VGA is so high that the average level of the output V ₀ is greater than the reference level REF, then the operational amplifier
The output voltage V ₂ of OP2 becomes positive, which is the integrator 1
As a result of integration by 11, the amplification factor control signal
The voltage of V _G gradually decreases, and thereby the gain of variable gain amplifier VGA gradually decreases. In the opposite case, the operation is reversed, and the gain of the amplifier VGA gradually increases. Therefore, in this automatic gain control circuit AGC, the gain of the amplifier VGA is controlled so that the voltage V ₂ becomes 0, that is, the average level of the output voltage V ₀ becomes equal to the reference level REF.

By the way, the holding signal HOLD is normally logic "0"
Therefore, the clock f _C passes through the AND gate 116, is divided by the frequency divider DIV, and is supplied to the switch SW as the frequency f _S. But hold signal HOLD
When becomes logic “1”, the inverter 124
Since the level at input 122 of AND gate 116 is a logic "0", clock f _C is not provided to frequency divider DIV. Therefore, the switch SW is a control signal.
f _S also stops, which causes the analog switch SW to
stops with capacitor CS connected to contact 104 or 106. Therefore, the capacitor C continues to be charged to the level of the voltage V _G immediately after that. Therefore, the amplification factor control signal
The voltage of V _G is fixed at that state, and the gain of variable gain amplifier VGA is maintained as it is. This effectively means that the switching frequency f _S becomes 0 and the integrator 111
This corresponds to the time constant T becoming infinite.

Although the automatic gain control circuit according to the invention has been described in terms of the particular implementation shown, the invention is not necessarily so limited. For example, a power calculator, half-wave rectifier, peak detector, etc. can be used instead of the full-wave rectifier FWR. If the switching frequency f _S of the analog switch SW is sufficiently higher than the signal frequency of the loop of the automatic gain control circuit AGC, the low-pass filter characteristic by the capacitor CA is not necessarily required. But if this is not the case, i.e. the signal frequency is
If the SW switching frequency f is close to _S , the switch
This low pass filter characteristic is necessary to avoid aliasing caused by sampling the voltage V ₂ by SW. Note that this low-pass filter may be a first-order filter as shown in the illustrated embodiment, but a high-order filter may also be used. Further, each of the resistors RA1, RA2, αRA, etc. can also be replaced by a switch capacitor.

By configuring the automatic gain control circuit according to the present invention in this manner, it can be effectively applied to a demodulator for facsimile signals, for example. For example, in a training sequence, the time constant of the integrator can be set small in the alternation to obtain quick tracking performance, and the time constant can be set large in the subsequent steady state to obtain high stability. In response to momentary interruptions, the gain can be maintained by stopping the switching clock of the switch capacitor, so that malfunctions of the automatic gain control circuit due to momentary interruptions can be minimized. Furthermore, when restarting after interrupting reception, the gain immediately before the interruption can be maintained, so the time conventionally required for the automatic gain control circuit to follow the restart can be eliminated. Furthermore, since the resistor that determines the time constant of the integrator is implemented by a switched capacitor, an automatic gain control circuit suitable for integrated circuits, particularly MOS integrated circuits, is provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a demodulator to which an automatic gain control circuit according to the invention is applied, and FIG. 2 is a circuit diagram showing an implementation of the automatic gain control circuit according to the invention. Explanation of symbols of main parts, CS...capacitor,
DIV...Frequency divider, FWR...Full wave rectifier, OP1,
OP2... operational amplifier, SW... analog switch, VGA... variable gain amplifier, 111... integrator.

Claims (1)

[Claims] 1. A variable gain amplifier; an error detection circuit that generates a first signal indicating the difference between the output of the variable gain amplifier and a reference level; and an error detection circuit that integrates the first signal and generates a second signal. and a loop filter having an integrator for controlling the gain of the variable gain amplifier by a second signal, the automatic gain control circuit temporarily controlling the level of the first signal. interposed between the error detection circuit and the integrator,
switching means for selectively selecting a first state in which the error detection circuit is connected to the storage means and a second state in which the integrator is connected to the storage means; The time constant of the integrator is made variable by making the frequency of switching between the first and second states variable, and the gain of the variable gain amplifier is maintained by stopping the switching. automatic gain control circuit.