JPS646592B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that divides a horizontal video period and a vertical video period of one television signal into a plurality of parts and configures one screen using a plurality of television receivers.

Usually, this is realized using a digital memory, but in that case, the method of configuring the frame memory is a big problem. The present invention provides means for efficiently utilizing a frame memory when obtaining television signal outputs with a plurality of time axes expanded for one television signal input.

The present invention relates to a device for displaying one television image shown in a of FIG. 1 as one image using, for example, 16 television receivers a ₁₁ to a ₄₄ as shown in b of FIG. .

Suppose that the input television signal is A/D converted by appropriately selecting the sampling frequency _S ( _S 10MHz), the number of effective pixels in one horizontal video period is 512 (the horizontal address is 0 to 511), and the effective vertical scanning is If the number of lines is 480 (vertical addresses are 0 to 479), the input television image can be divided into 16 areas as schematically shown in FIG.

For example, images in the areas of horizontal addresses 128-255 and vertical addresses 120-239 are enlarged and displayed on the television receiver _a22 . That is, although there is one input television signal system, 16 output television signal systems are required.

As a means for performing such processing, there is one that has one digital frame memory for one television receiver, that is, a total of 16 digital frame memories. A conventional configuration using this means will be explained using FIG. 3. Figure 3 shows a television receiver.
This figure shows one digital frame memory system compatible with _A22 .

A luminance signal separated from a color television signal is applied to an input terminal 1, encoded into 8 bits at a sampling frequency _S using an A/D converter 2, and applied to a series/parallel switching circuit corresponding to each bit. That is, the most significant bit is added to the 4-bit serial/parallel switching circuit 3, and the least significant bit is added to the 4-bit serial/parallel switching circuit 4. Here, only the most significant bit and least significant bit series are shown for the sake of explanation.
3, 14, 15, 16, the output of the serial/parallel switching circuit 4 is applied to memories 17, 18, 19, 20 via registers 9, 10, 11, 12. Digital frame memory compatible with TV receiver _A22 ,
As shown in FIG. 2, horizontal addresses 128 to 255 and vertical addresses 120 to 239 of the input television signal.
memorize the signal. That is, the horizontal addresses 128 to 255 and the vertical addresses 120 to 255 of the input television signal
When the 239 signal arrives at input terminal 1, the A/D
A converter 2 encodes it into 8 bits, and the most significant bit is applied to a serial/parallel exchanger 3, the least significant bit is applied to a serial/parallel exchanger 4, respectively.

The output signal of the serial-parallel exchanger 3 is sent to registers 5, 6,
Temporarily stored in 7 and 8. That is, register 5 has horizontal addresses 128, 132, 1
36, ..., 252 signals, register 6 has horizontal addresses 127, 133, 1
37, ..., 253 signals, register 7 has horizontal addresses 130, 134, 1
38, ..., 254 signals, register 8 has horizontal addresses 131, 135, 1
The signals of 39, ..., 255 will be stored respectively, and the registers 5,
6, 7, 8 output signals to memories 13, 14, 1
5 and 16, respectively. A write operation to the memory is performed at horizontal addresses 128 to 131, 1, for example.
32-135, ..., 252-255 4
This is performed every time signals for pixels are stored in the registers 5, 6, 7, and 8. That is, the write operation is performed at a frequency of _S /4.

Such a write operation to the memory is performed for each of the vertical addresses 120 to 239 of the input television signal, and the memory 13, 14, 15, 16 is
Horizontal addresses 128-25 of the input TV signal to
5. Store signals of vertical addresses 120-239.

In this way, the signal written to the digital frame memory corresponding to the TV receiver _A22 is read out by expanding the time axis four times in both the horizontal and vertical directions, so that the signal is 1/16th of the input TV signal. A signal for one screen is used as a signal for one screen. Expansion of the time axis in the horizontal direction is done by reading the signal from the memory at a frequency of 1/4 of the writing frequency, that is, 1/4 × 1/4 = 1/16・_S , and expanding the time axis in the vertical direction. The time axis is expanded by treating the signal of one scanning line as the same signal across four scanning lines, that is, by reading out the signal written at the horizontal scanning frequency _H at _{the H} /4 frequency.

The signals read out from the memories 13 to 16 in this way are transferred to the 4-bit parallel/serial switching circuit 21 from the memories 17 to 16.
The signals read from 20 are applied to a 4-bit parallel-serial switching circuit 22, and the signals at horizontal addresses 128 to 255 of the input television signal are read out in order, and the output is applied to a D/A converter 23 to convert it into an analog signal. After that, the output is supplied to the television receiver _A22 .

As explained above, the storage capacity of each of the memories 13 to 20 is (120÷4)×120=3840, or about 4K bits. Therefore, in the configuration of FIG. 3, 4 (phases) x 8 (bits) = 32 4k-bit memories are required, and for 16 systems, 32 x 16 = 512 memories are required.

The present invention aims to provide an image enlargement multi-screen display device that requires less memory by making it possible to use a large capacity memory, and embodiments of the present invention will be described below with reference to the drawings.

Figure 4 shows an example in which the horizontal and vertical periods of one system of color television image signals are each divided into four, and one image is displayed using 16 television receivers as shown in Figure 2. It is. The color television signal applied to the input terminal 30 is processed by the decoder circuit 31 into a luminance signal Y and two color difference signals (R
-Y) and (BY). The luminance signal Y is filtered through a low-pass filter (LPF) 32 to a band of approximately 4MHz, and the color difference signals (RY) and (B-Y) are filtered to approximately 500K by a low-pass filter (LPF) 33 and 34, respectively.
It shall be limited to the Hz band. 32, 33, 3
4 to A/D converters 35, 36,
In addition to 37 bits, a 3-bit encoded signal is obtained. A/
In the D converter 35, the sampling frequency _S (10M
Hz), and the A/D converters 36 and 37 perform encoding at a sampling frequency of _S /8. A/D
The respective outputs of the converters 35, 36, and 37 are applied to video enlargement circuits 41, 42, 43, and 44 shown by dashed lines. The video enlargement circuit 41 creates four systems of television signals to be supplied to the television receivers a ₁₁ , a _{12 ,} a ₁₃ , and a 14 shown in FIG. 1b. Similarly, 42, 43,
44, the television receivers a ₂₁ , _{a 22} , _{a 23} , a ₂₄ shown in FIG _.
A ₃₄ and four channels of television signals to be supplied to the television receivers a ₄₁ , a ₄₂ , a ₄₃ , and a ₄₄ are created. Since the basic operations of 41, 42, 43, and 44 are the same, only 41 will be explained here. The memory circuit 38 receives an 8-bit encoded signal of the luminance signal Y.
An 8-bit encoded signal of the color difference signal (RY) is applied to the memory circuit 39, and an 8-bit encoded signal of the color difference signal (BY) is applied to the memory circuit 40. The operation of the memory circuit 38 according to the present invention will be explained using FIG. In FIG. 5, the 8-bit signal encoded by the A/D converter 35 is sent to registers 64 and 6.
Add to 5, 66, 67. Furthermore, the register 64,
The outputs of 65, 66 and 67 are applied to buffer memories 84, 85, 86 and 87, respectively.

Here, four buffer memories 84, 85, 8
At 6 and 87, the 8-bit encoded signal of the luminance signal Y for one horizontal video period is stored.

As shown in FIG. 2, the number of pixels in one horizontal video period is 512, so the buffer memory 84 stores encoded signals at horizontal addresses 0 to 127, 85 stores encoded signals at 128 to 255, and 86 stores encoded signals at 25
The encoded signals of addresses 6 to 383 and 87 store the encoded signals of addresses 384 to 511, respectively. That is, horizontal addresses 0 to 12 are stored in the buffer memory 84.
After writing the signal of 7 at the same frequency as the encoding frequency _S , the horizontal address 128 is written to the buffer memory 85.
Writing to the buffer memories 86 and 87 is performed in the same way as writing the signals of .about.255. In this way, after writing to the buffer memories 84, 85, 86, and 87 is completed in one horizontal scanning period, writing to the buffer memories 84 to 87 is completed in the next horizontal scanning period, and at the same time, writing is performed in the horizontal scanning period. Read out the signal.

Reading from the buffer memories 84 to 87 is performed at 1/4 of the writing frequency _S. For example, the buffer memory 85 is read out by reading signals from horizontal addresses 0 to 127 written in 1/4 horizontal scanning period in one horizontal scanning period, thereby expanding the horizontal time axis by four times. In this way, the 8-bit signal of the buffer memory 84 read out at the frequency of 1/4 _S is read out at the same frequency of 1/4
Write to memories 69-76 with _S. Memory 69-7
Writing to 6 is performed for signals at vertical addresses 0 to 119 of the input television signal.

Since horizontal time axis expansion is performed in the buffer memory 85 when reading from the memories 69 to 76, signals at horizontal addresses 0 to 127 are read at the same frequency of 1/4 _S as writing. Vertical address 0-119
In reading out the signals, the vertical time axis is expanded four times by reading out signals at the same vertical address during four horizontal scanning periods in the same manner as in the conventional example shown in FIG. In this way, the 8-bit signal 60 read from the memories 69-76 is converted into an analog signal by the D/A converter 45. The output of the D/A converter 45 is obtained by expanding the horizontal and vertical time axes of the luminance signal Y of the input television signal by four times, respectively.
Although only the memory block 80 has been described above, the basic operations of the memory blocks 81, 82, and 83 are the same as that of the memory block 80, so a description thereof will be omitted. Output signals 60, 6 of memory blocks 80, 81, 82, 83
1, 62, and 63 are the analog processing circuit 5 in FIG.
Add to 2, 53, 54, 55.

The basic operation of the memory circuits 39 and 40 is similar to that of the memory circuit 38, but the difference is that the buffer memory and memory block may have smaller storage capacities.

One of the output signals of the memory circuits 39 and 40 is applied to, for example, D/A converters 46 and 47, respectively, to obtain analog signals of color difference signals (RY) and (BY). Each output signal of the D/A converters 45, 46, 47 is applied to an encoder circuit 51 via low-pass filters 48, 49, 50. Encoder circuit 51
Then, the color difference signals (RY) and (BY) are subjected to quadrature two-phase modulation using color subcarriers, and the luminance signal Y, burst signal, and synchronization signal are multiplexed. Encoder circuit 5
1 is added to the television receiver a ₁₁ shown in FIG. 1b to obtain an image whose horizontal and vertical time axes are expanded four times. The other output signals of the memory circuits 38, 39, 40 are sent to the analog processing circuits 53, 54, 55, and the output signals are sent to the television receiver shown in FIG. 1b.
Add to a ₁₂ , a ₁₃ , a ₁₄ . Video enlargement circuit 42, 4
The operations of 3 and 44 are the video enlargement circuit 41 which has already been explained.
The output signal of 42 is sent to the television receivers a ₂₁ , a ₂₂ , a _{23 , a 24} shown _in FIG. a ₃₄ , 4
The output signals of 4 are the TV receivers a ₄₁ , a ₄₂ , a ₄₃ , a ₄₄
Add to each. By the operation explained above,
One system of television images shown in a of FIG. 1 can be expanded to 16 systems of television images as shown in FIG.

Considering the Y signal system of color television signals, in the present invention, the frame memory corresponding to one receiver consists of eight memories as shown in memories 69 to 76 in FIG. In order to construct one screen using a television receiver, 16 frame memories, that is, 8×16=128 memories are required. Here, the capacity of one memory is 128×
128≒16K bits, writing frequency is 1/4・_S
It is.

On the other hand, in the conventional example, the frame memory corresponding to one television receiver is 4×8 as shown in Figure 2.
= 32 memories, so if 16 television receivers constitute one screen, 16 frame memories, or 32 x 16 = 512 memories, are required. Here, the capacity of one memory is (128≒4)
×128≒4K bits, and the writing frequency is 1/4.
It is _S.

In the present invention, instead of increasing the memory capacity used by four times compared to the conventional example, the required number of memories is reduced to one fourth. In the conventional example, a 1-bit encoded signal is converted to 4 bits using a serial-parallel switching circuit 3 in order to reduce the memory write frequency to 1/4 _S , as shown in Figure 2. In contrast, in the present invention, buffer memories 84 to 87 as shown in Fig. 5 are used to lower the memory write frequency to 1/4 _S , so a 1-bit encoded signal is converted to 4 bits. This is because there is no need.

In addition, in the example, an example was shown in which one screen is configured with 4×4 television receivers, but one screen is configured with m×n television receivers (m and n are integers of 2 or more). It can also be applied when configuring.

As already explained, in the conventional example and the present invention, the writing frequency of the memory is the same, so the operating frequency required for the memory is the same. The difference is that in the past, the capacity of each memory was, for example, about 4K bits, whereas in the present invention, each memory capacity was, for example, about 16K bits, and it was difficult to generate a signal corresponding to one receiver. The number of memories required is 1/4. That is, the number of memories used can be reduced without increasing the operating frequency required for the memories. Therefore, the circuit scale can be greatly reduced, and considering that memory prices become more economical as the capacity increases, costs can be reduced significantly. Moreover, the larger the enlargement ratio, the greater this effect. In the embodiment of the present invention, the number of memories is 1/4 of the conventional one, but when the horizontal and vertical time axes are expanded eight times, the number of memories becomes 1/8 of the conventional one.

[Brief explanation of drawings]

Figure 1 is a screen diagram of a television receiver to explain how the image is enlarged, Figure 2 is a diagram to explain how the input television image is divided and the correspondence between horizontal and vertical addresses, and Figure 3 is a diagram to explain how the input television image is divided and the correspondence between horizontal and vertical addresses. FIG. 4 is a block diagram of a conventional image enlarging multi-screen display device, FIG. 4 is a block diagram of an image enlarging multi-screen display device according to an embodiment of the present invention, and FIG. 5 shows a detailed configuration of the memory circuit in FIG. 4. It is a block diagram. 31... Decoder circuit, 32-34... Low pass filter, 35-37... A/D converter, 41-44
...Video enlargement circuit, 38-40...Memory circuit, 45
~47...D/A conversion circuit, 48~50...Low pass filter, 51...Encoder circuit.

Claims (1)

[Claims] 1 an A/D converter that encodes a television signal; 1
The horizontal period of one television signal is divided into m and the vertical period is divided into n (m and n are integers of 2 or more) m×n.
a frame memory that stores encoded signals corresponding to each screen portion divided into three screen portions, and converts m×n encoded signals corresponding to each screen portion read from the frame memory into analog signals. In a device equipped with a D/A converter that converts the sampling frequency to An encoded signal of the television signal encoded at _S is written at a write frequency _S , and an encoded signal written one horizontal period ago is read out at a read frequency _S /m for each of the m×n screen parts. The buffer memory read by m and the m read from this buffer memory.
The encoded signals for each of ×n screen parts have a horizontal writing frequency _S / m and a vertical writing frequency _H ( _H
m×n frame memories written at a horizontal scanning frequency) and read out at a horizontal readout frequency _S /m and a vertical readout frequency _H ;
m read from each of the frame memories
A D/A converter that converts each of the xn encoded signals into an analog signal is provided, and the m x n analog signals are supplied to the m x n television receivers respectively, so that the overall signal is integrated. A video enlargement multi-screen display device characterized in that it is configured to display two enlarged images.