JPS646632B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Description of the Prior Art The present invention relates to a control method for turning on and off a bypass pair in a polyphase controlled rectifier configured by connecting a plurality of unit controlled rectifiers in parallel. .

(b) Description of Prior Art Conventionally, in low ripple controlled rectifiers and large current controlled rectifiers, polyphase controlled rectifiers in which a plurality of unit controlled rectifiers are connected in parallel have been used.

Figure 1 shows the main circuit configuration of a controlled rectifier with two unit controlled rectifiers in parallel and a 12-phase configuration.
In Figure 1, 1 is the AC bus bar 2-1, 2-2 is a rectifier transformer, and the secondary side voltage phase of the rectifier transformer 2-2 is the secondary side voltage of the rectifier transformer 2-1. It is configured to be 30° behind the phase. 3
-1 and 3-2 are rectifier transformers 2-
1, 2 - A unit control rectifier that inputs the secondary side voltage and converts it into a DC voltage. A DC reactor, 6 is a load. 4-
1 to 4-6 are controlled rectifying elements that constitute the unit controlled rectifier 3-1. For convenience of explanation, 4-1 is
Phase, 4-2 is V phase, 4-3 is W phase, 4-4 is X
Phases 4-5 are called Y-phase and 4-6 are called Z-phase. Similarly to the unit control rectifier 3-1, the phases of the unit control rectifier 3-2 are referred to as U, V, W, X, Y, and Z phases.

In a controlled rectifier as shown in Fig. 1, in a normal control method, the firing angle of the controlled rectifier is set to U according to the control amount (Ec) corresponding to the output voltage obtained from a constant current control circuit, etc. ,Z,V,X,
The W and Y phases are sequentially controlled in order to obtain the required output voltage, but in order to reduce the DC output voltage to zero and the reactive power to zero, or short-circuit both ends of the load and separate it from the AC side. For a pair of phases connected to the same AC phase, i.e. UX phase, VX
It is generally known that bypass pair closing control is performed, in which the WZ phase or WZ phase is fired simultaneously, and bypass pair release control, which returns to normal control from the bypass pair state.

FIG. 2 shows a block diagram of a conventional control circuit.
Blocks in the figure having the same functions as those in FIG. 1 are designated by the same reference numerals and explanations will be omitted. In Fig. 2, 7 is an instrument transformer, and 8 is a synchronizing signal (AC input voltage of unit control rectifiers 3-1, 3-2) that receives the output of the instrument transformer and serves as a reference signal for firing angle control. This is an auxiliary instrument transformer that outputs a three-phase alternating current signal having the same phase to phase-specific control circuits 12-1 and 12-2, which will be described later. 9 is a current detector that detects the load current;
10 is an adder that takes the difference between the current reference value and the load current;
11 is a constant current control circuit, and its output signal 53
is the control amount (Ec) corresponding to the output voltage.
12-1, 12-2 are synchronization signals 52-1, 52-
2 and a control amount (Ec) 53 corresponding to the output voltage, the ignition timing and ignition phase are determined, normal ignition angle control is performed, and upon receiving the bypass pair release signal 51, the bypass This is a phase control circuit that controls pair release. In a commonly used phase control circuit, bypass pair activation and cancellation are controlled as described below. In other words, when the firing angle is controlled in the order of U, Z, V, X, W, Y, when a bypass pair input signal is received, the pulse to the next phase is cut and the next phase is activated. Outputs a pulse to. For example, when receiving a bypass pair input signal after ignition of the U phase, a pulse to the Z phase is cut, a pulse is output to the V phase, and a bypass pair is formed in the VY phase.

The pulse to the next phase to be output is cut, the pulse to the next phase to be output is cut, and the ignition pulse is output to the next phase to be output. For example, if a bypass pair input signal is received after U phase ignition, Z phase,
The pulse to the V phase is cut, the ignition pulse is output to the X phase, and the UX phase is used as a bypass pair.

or the bypass pair. Since there is no difference in the explanation of the present invention between the two methods, the following method will be used for explanation.

Various methods have been used to release the bypass pair state, but since there is no difference in the explanation of the present invention no matter which method is used, the following method will be used as a typical example. That is, when a bypass pair release signal is received, a firing pulse is given to the next phase of the phase that was fired immediately before being turned on to the bypass pair, and the bypass pair state is released.

To summarize the above, phase control circuits 12-1, 12
-2, the bypass pair release signal 51 is “1”
When the bypass pair input signal is received, the pulse to the next phase to be output is cut, and the pulse is output to the next phase to enter the bypass pair state, and the bypass pair input release signal 51 becomes "0", which is the bypass pair release signal. When the bypass pair is turned on, a pulse is output to the phase that was cut when the bypass pair was turned on to release the bypass pair, and the process then proceeds to normal firing angle control.

By the way, when the conventionally used bypass pair release control method as explained above is applied to a multi-phase controlled rectifier configured by connecting multiple unit control rectifiers in parallel, when releasing from the bypass pair state, , a problem occurs in that a large current imbalance occurs between each unit control rectifier.
FIG. 3 shows phase voltage waveforms of the unit control rectifiers 3-1 and 3-2 and a time chart of the bypass pair release signal 51 in the case of the conventional control method shown in FIG. As described above, the bypass pair release signal 51 is "1" as a bypass pair release signal, and "0" as a bypass pair release signal. As shown in Figure 3, an ignition pulse is output to a certain phase (U phase in the figure) of unit control rectifier 3-1 whose AC side input voltage phase is leading, and a unit whose AC side input voltage phase is lagging. If a bypass pair input signal is received before the ignition pulse is output to the corresponding phase of the control rectifier 3-2, the bypass pair formation phases of the unit control rectifiers 3-1 and 3-2 will be different. In Fig. 3, a bypass pair is formed in the VY phase in the unit control rectifier 3-1, but in the unit control rectifier 3-2,
A bypass pair is formed in the WZ phase. Therefore, the phase to which a pulse should be output when exiting the bypass pair state is Z in the unit control rectifier 3-1.
phase, it becomes the U phase in the unit control rectifier 3-2. Therefore, when receiving the bypass pair release signal at the timing shown in Fig. 3, the unit control rectifier 3-1 immediately shifts to normal operation from the bypass pair.
Since the unit control rectifier 3-2 shifts to normal operation with a delay of one cycle, the output voltage becomes unbalanced and a large current imbalance occurs between the unit control rectifiers.

(c) Purpose of the Invention The purpose of the present invention is to solve the problems of the conventional system as explained above, and to control each unit when the bypass pair is released, regardless of the timing when the signal to release the bypass pair is received. An object of the present invention is to provide a bypass pair closing/release control method for a controlled rectifier that suppresses current imbalance between rectifiers to the same level as the current imbalance that occurs during normal firing angle control.

(d) Structure of the invention FIG. 4 shows an embodiment of the invention. In the figure, blocks and signals having the same functions as those in FIG. 2 are designated by the same reference numerals and their explanations will be omitted. In Fig. 4, 13-1 and 13-2 are OR elements that take the OR of all the output pulses from the phase control circuits 12-1 and 12-2, respectively, and 14 is the unit for which the input voltage phase on the AC side is delayed. A one-shot circuit 15-1 generates a one-shot signal by a pulse train from an OR element 13-2 that ORs all the output pulses of the phase control circuit 12-2 that controls the control rectifier 3-2, and a one-shot circuit 15-1 releases the bypass pair input. The AND element 16-1, which takes the AND condition of the signal 51 becoming the closing side (“1”) and the output signal of the one-shot circuit 14, inverts the bypass pair closing signal and cancels the bypass pair closing. The inverter element 17-1, which outputs a signal of "1", is set by the output of the AND element 15-1, reset by the output of the inverter element 16-1, and inputted into the phase control circuit 12-1 by inputting the bypass pair. A flip-flop circuit 15-2 outputs a signal of "0" when the flip-flop circuit 15-2 is released from the OR element 13-2.
1 output signal and flip-flop circuit 17-1
An AND element that takes an AND condition between the output signal and the inverter signal; 16-2 is a flip-flop circuit 1;
The unit control rectifier 3-1 inverts the output signal of 7-1 and has a leading AC side voltage phase.
When a bypass pair release signal is output to the phase control circuit 12-1 that controls the phase control circuit 12-1, the inverter element 17-2 that outputs "1" is set by the output signal of the AND element 15-1, and the output signal of the AND element 15-2 is set. It is reset by the output signal and becomes “1” when the bypass pair is applied to the phase control circuit 12-2, and “0” when the bypass pair is released.
a flip-flop circuit that outputs a signal of 18
is a hold circuit that, when receiving a signal of "1" when the bypass pair is turned on, holds the control amount (Ec) for normal firing angle control at the value at that timing.

(e) Operation of the invention The operation of the present invention will be explained below with reference to FIG.

The OR elements 13-1 and 13-2 take the OR of all the firing timing pulses output to each phase from the phase control circuits 12-1 and 12-2, respectively, and the phase control circuits 12-1 and 12-2 The series signal 54, 5 of the ignition timing pulse outputted by
Get 5. The signal 55 is input to the one-shot circuit 14, and a one-shot signal for a bypass pair input permission period is output. In other words, in the case of a 12-phase configuration with two unit control rectifiers, by setting the one-shot signal time to a time slightly smaller than the time corresponding to 30° of the AC side input voltage, the AC side input voltage phase can be adjusted. Bypass from when the ignition pulse is output to the unit control rectifier 3-2 that is lagging until just before the pulse is output to the unit control rectifier 3-1 whose AC side input voltage phase is ahead. It can be a period of permission for input. When the signal 51 becomes "1" and the signal 56 becomes "1", the output of the AND element 15-1 becomes "1",
Flip-flop circuits 17-1 and 17-2 are set, their output signals 57 and 58 become "1", and a bypass pair input signal is input to phase control circuits 12-1 and 12-2. At this time, due to the change in the control amount Ec, before the bypass pair release signal 57 becomes "1", the phase control circuit 12-1
The control amount Ec is fixed by the hold circuit 18 at the timing when the signal 51 becomes "1" so that the next pulse will not be generated. When controlled as described above, when the phase control circuits 12-1 and 12-2 receive the bypass pair input signal, they output firing pulses to the same phase, so the unit control rectifiers 3-1 and 3- 2 always form a bypass pair with the same phase.
Next, when the signal 51 becomes "0" and the bypass pair is released, the flip-flop circuit 17-1 is reset by the output of the inverter circuit 16-1, and the input signal 57 to the phase control circuit 12-1 becomes "0". , a pulse for canceling the bypass pair is output from the phase control circuit 12-1. When the signal 57 becomes "0", the AND element 15-2 confirms that the phase control circuit 12-1 outputs a pulse for canceling the bypass pair, resets the flip-flop circuit 17-2, and the signal 58 becomes "0". Then, a bypass pair release signal is input to the phase control circuit 12-2, and the unit control rectifier 3-2 is released from the bypass pair. When controlled as described above, after the unit control rectifier 3-1 is released from the bypass pair, the unit control rectifier 3-2 is released from the bypass pair, and a release pulse is output to the same phase, so the bypass pair is released. The difference in release timing is always
30°, which is not much different from the difference in output voltage during normal firing angle control, and the current imbalance is much smaller than in the conventional method.

FIG. 5 shows the phase voltage waveform of each unit control rectifier when the bypass pair release control method of the present invention is used, and the time chart of each signal according to the embodiment of the present invention shown in FIG. As explained with reference to FIG. 4, even if the bypass pair release signal 51 becomes "1", until the signal 56 becomes "1",
That is, when a U-phase pulse is output to the unit control rectifier 3-1, the phase control circuits 12-1 and 12-2 continue until the U-phase pulse is output from the unit control rectifier 3-2.
Since the bypass pair release signals 57 and 58 to the unit control rectifiers 3-1 and 58 do not become "1",
3-2 both form a bypass pair in the VY phase. Next, when the signal 51 becomes "0", the bypass pair release signal 57 to the phase control circuit 12-1 immediately becomes "0", and the firing phase (Z A pulse is output to the phase). After confirming that unit control rectifier 3-1 has been released from the bypass pair, phase control circuit 1
The bypass pair connection release signal 58 to 2-2 becomes "0", and the unit control rectifier 3-2 is released from the bypass pair. Comparing the phase voltage waveform of the conventional example shown in FIG. 3 and the phase voltage waveform of the present invention shown in FIG.
It is clearly seen that the present invention greatly reduces the current imbalance when the bypass pair is released.
In the embodiment of the present invention shown in FIG. 4, the bypass pair injection permission period is set by the one-shot circuit 14, but the same effect can be obtained by using a flip-flop circuit that sets the bypass pair input period using the signal 55 and resets it using the signal 54. be able to.

(e) Overall effect As explained above, according to the present invention, the phase control circuits 12-1 and 12-2 are completely the same as the conventional ones, and only a few logic operation elements are added to the outside. By simply adding , even if a multi-phase controlled rectifier configured by connecting multiple unit control rectifiers in parallel is connected to and released from a bypass pair, the bypass of the controlled rectifier will have less current imbalance when the bypass pair is released. A pair entry/release control method can be provided.

[Brief explanation of drawings]

Figure 1 is a main circuit configuration diagram of a 12-phase controlled rectifier constructed by connecting two unit controlled rectifiers in parallel, Figure 2 is a block diagram showing the control method of a conventional controlled rectifier, and Figure 3 is a block diagram showing the control method of a conventional controlled rectifier. FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. 5 is a time chart of an embodiment of the present invention. 1... AC bus, 2-1, 2-2... Rectifier transformer, 3-1, 3-2... Unit control rectifier, 4
-1 to 4-6... Control rectifying element, 5-1, 5-2
... DC reactor, 6 ... Load, 7 ... Instrument transformer, 8 ... Auxiliary instrument transformer, 9 ... Current detector, 10 ... Adder, 11 ... Constant current control circuit, 12 - 1, 12-2...phase control circuit, 13
-1, 13-2...OR element, 14...One shot circuit, 15-1, 15-2...AND element,
16-1, 16-2...Inverter element, 17-
1, 17-2...Flip-flop circuit, 18...
...Hold circuit, 51...Bypass pair release signal, 52-1, 52-2...Synchronization signal, 53...
...Controlled amount (Ec), 54, 55...Ignition pulse series signal, 56...Bypass pair input permission period signal,
57, 58... Bypass pair release signal according to the present invention.

Claims (1)

[Claims] 1. In a multi-phase controlled rectifier configured by connecting multiple unit control rectifiers in parallel, when controlling bypass pair input and release, the bypass pair forming phase of all unit control rectifiers should be the same and A bypass pair input/release control method for a controlled rectifier, characterized in that the bypass pair release phases of all unit control rectifiers are controlled to be the same.