JPH0126261B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bypass pair control system for a power conversion device that supplies current flowing to a coil used in an accelerator such as a cyclotron or synchrotron.

When supplying power to accelerator coils such as cyclotrons and synchrotrons, or coils for tokamak-type fusion reactors, the inductance of the load is generally large, so the current fall and fall period,
The required DC voltage differs greatly depending on the constant current period. For this reason, power converters used in accelerator coils, etc., have a configuration in which unit power converters are connected in a cascade, and during periods when voltage is not required, unit power converters are inserted into bypass pairs as appropriate to improve the power factor. Generally, the aim is to reduce DC voltage ripple.

FIG. 1 shows a block diagram of an accelerator coil power supply constructed by connecting two series 12-phase power converters in cascade.

In Figure 1, 1 is an AC bus, 2-1, 2-
2 is a converter transformer, and 3-1 and 3-4 are unit power converters. Unit power converters 3-1 and 3-
2, 3-3 and 3-4 have AC voltage phases shifted by 30 degrees, and the unit power converters 3-1 and 3-4
2 (3-3 and 3-4) constitute a series 12-phase power converter. 4 is a load coil, and 5 is a DC current detector. 6 is an instrument transformer that detects the AC voltage waveform in order to detect the AC voltage phase; 7
8 is a subtraction circuit that calculates the difference between the current reference signal 51 and the current obtained from the DC current detector 5, and 8 is a current control circuit that controls the power converter so that the output ΔI of the subtraction circuit 7 becomes zero. , 9 is the instrument transformer 7
and a phase control circuit which inputs the output of the current control circuit 8 and the output of the current control circuit 8 and determines the firing phase and firing timing;
Reference numeral 10 indicates a bypass pair control circuit that receives the bypass pair (BPP) command signal 52 and inserts the target unit power converter into the bypass pair, and 11 indicates a pulse amplifier circuit that amplifies the ignition pulse signal to each phase. . Bypass pair is an operating mode in which a pair of controlled rectifying elements connected to one phase on the AC side are fired simultaneously.

FIG. 2 shows a block diagram inside the unit power converter. In the figure, 12-1 to 12-6 are controlled rectifying elements constituting a unit power converter, respectively.
They are called Z phase, V phase, X phase, W phase, and Y phase. A pair of controlled rectifying elements are U phase and X phase, V phase and Y phase
phase, and each pair of W phase and Z phase.

Figure 3 shows a typical load current pattern for accelerator coils. In FIG. 3, 53 is a proton or electron injection period, 54 is an acceleration period, 55 is an extraction period, and 56 is a deceleration period. Generally, each period is 1 to 2 seconds, and the same pattern is repeated for more than 10 hours. In such a load pattern, since the load in the accelerator is a large inductance, during the injection period 53 and the extraction period 55,
Only a small voltage corresponding to the resistance drop is required, and a large voltage of LdI/dt is required during the acceleration period 54 and the deceleration period 56 (L is the inductance value, I is the current value). For this reason, in the power supply configuration as shown in FIG. Generally, a method is used in which the current is controlled solely by the power source and the unit power converters 3-3 and 3-4 are released from the bypass pair immediately after entering the acceleration period 54 and the deceleration period 56.

By the way, in the conventional bypass pair control method, when a bypass pair command is received, the last fired phase is checked, the firing pulse to the next phase that outputs the firing pulse is cut, and the firing pulse is switched to the next phase. A common method is to output an arc pulse and input it to a bypass pair. In other words, during normal operation, U→Z→V→X→
The ignition pulse is output to each phase in the order of W → Y phase, but
If a bypass pair command comes while the U phase and Z phase are energized,
The ignition pulse to the V phase is cut, the ignition pulse is output to the X phase, and a bypass pair is formed by U phase and X phase ignition.

FIG. 4 shows phase voltage waveforms when a bypass pair command is received when the Z and V phases are energized and the W and Z phases become a bypass pair. In such a conventional bypass pair control method, which pair enters the bypass pair is determined by the timing of the bypass pair command, and therefore it is not possible to specify which phase becomes the bypass pair. During normal operation, each control rectifying element in the unit power converter conducts electricity through 120 degrees, but when it becomes a bypass pair, it conducts through 360 degrees, as is clear from Fig. 4.

Therefore, in the conventional bypass pair control method,
There was a problem in that the current rating of the control rectifying element of the unit power converter input to the bypass pair had to be tripled compared to normal.

It is an object of the present invention to provide a bypass pair control method for a power converter that eliminates the above-mentioned problems and is capable of controlling a repetitive load pattern as shown in FIG. 3 at the same current rating of the control rectifier as in normal operation. It provides:

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows an embodiment of the present invention. The main circuit configuration is the same as that in FIG. 1, so a description thereof will be omitted. In FIG. 5, the same functions as those in FIG. 1 are designated by the same reference numerals, and the explanation thereof will be omitted. 13 is a ternary counter that counts up at the rising edge of the bypass pair input command 52; 14 is a code conversion circuit that converts the output of the ternary counter 13; when the output of the ternary counter is "0", the signal 59 is When the output of the ternary counter is “1”, the signal 60 is “1”
Furthermore, the signal 61 is configured to be "1" when the output of the ternary counter is "2". 15 is a pulse generation circuit that outputs a pulse upon receiving the bypass pair command signal 52; 16 is an inversion circuit; 17-1 to 1;
7-6 is an inhibit circuit that cuts the normal firing pulse output from the phase control circuit 9 in response to the bypass pair command signal 52; 18-1 to 18-3;
19-1 to 19-6 are AND circuits that perform an AND operation on the output of the pulse generation circuit 15 and the output of the code conversion circuit 14, and output a pulse to the phase to be input to the bypass pair. This is an OR circuit that takes the logical sum of the ignition pulse at the time and the bypass pair input pulse. Figure 6 shows the code conversion circuit 14.
The internal block diagram is shown. Components with the same functions as those in FIG. 5 are given the same reference numerals. 16-1 and 16-2 are inverting circuits, and 18-4 to 18-6 are AND circuits.
When the output signals 57 and 58 of the ternary counter 13 are both "0", the signal 59 is "1", and when the signal 58 is "0", the signal 60 is "1", and the signal 57 is "1". When the signal 58 is "0" and the signal 58 is "1", the signal 61 becomes "1".

The operation of the present invention will be explained below with reference to FIGS. 5 and 6. In Fig. 5, when the output of the ternary counter is "2" (10), the bypass pair command signal 5
2 becomes "1", the normal ignition pulse outputted from the phase control circuit 9 is cut off by the inverting circuit 16 and the inhibiting circuits 17-1 to 17-6. At the same time, the output of the ternary counter 13 becomes "0" (00), and the signal 59 among the outputs of the code conversion circuit 14 becomes "1". In addition, upon receiving the bypass pair command signal 52, the pulse generation circuit 1
A pulse is generated from 5. Pulse generation circuit 15
and the output of the code conversion circuit 14,
A bypass pair input pulse is output from the AND circuit 18-1 to the U phase and the X phase, and the OR circuit 19-1,
It is output to the unit power converter via 19-4 and the pulse amplifier circuit 11. Next, when the bypass pair input command becomes "0", the output from the pulse generation circuit 15 becomes zero, the bypass pair input pulse signal disappears, and the output of the inverting circuit 16 becomes "1", so that the inhibit circuit 17 A normal ignition pulse is output via -1 to 17-6.

Next, when the bypass pair command signal becomes "1" again, the output of the ternary counter 13 becomes "1" (01), so the signal 60
becomes “1”, and the V phase Y from the AND circuit 18-2
A bypass pair input pulse is output to the phase. Similarly, when the bypass pair command signal comes next, the output of the ternary counter 13 becomes "2" (10), the signal 61 among the outputs of the code conversion circuit becomes "1", and the W
Outputs a bypass pair input pulse to phase and Z phase. FIG. 7 shows the relationship between the output of the ternary counter 13 and the output of the code conversion circuit 1. As is clear from the table in FIG. 7, the output signals 59, 60,
61 becomes "1" sequentially, and the phases to be input to the bypass pair are controlled in the order of UX phase, VY phase, and WZ phase.

The operation of the invention described above is shown in FIG. 8 by a time chart. 62 is the load current pattern, 5
2 is a bypass pair command signal, and 59, 60, and 61 are output signals of the code conversion circuit 14. The output of the 3-signal counter is shown in decimal notation.

When the load current is approximately constant, the unit power converters 3-3 and 3-4 shown in FIG. 1 are put into the bypass pair, and when the current changes significantly, they are released from the bypass pair. The three outputs of the code conversion circuit control which phase is put into the bypass pair, and when the signal 59 is "1", the U
When the phase and X phase signals 60 are "1", the V phase and Y phase signals 61 are "1", the W and Z phases are input to the bypass pair.

That is, since the phases applied to the bypass pair are sequentially controlled, an imbalance in current sharing between the phases that occurs when the same phase is successively applied to the bypass pair does not occur. Normally, the load current pattern of an accelerator coil is repeated for a long period of time per pattern, so by sequentially controlling the phases that are input to the bypass pair, the current rating of the unit power converter can be adjusted to approximately the same as that during normal operation. The current rating for 120° energization is sufficient, and the current rating is approximately 1/3 that of continuous bypass pair operation (360° energization).

In the above description, U phase, X phase, V phase, Y phase,
Although the W phase and the Z phase are controlled in this order, the same effect can be obtained by sequentially controlling them in any order.

FIG. 9 shows another embodiment of the present invention. In FIG. 9, blocks having the same functions as those in FIGS. 1 and 5 are designated by the same reference numerals and their explanations will be omitted. 20 is an ignition state detection circuit that receives an ignition pulse from the phase control circuit 9 and detects the phase that finally outputs an ignition pulse;
1-1 to 21-4 are AND circuits, and 22 is an OR circuit. The output signal 63 of the ignition state detection circuit 20 outputs "1" for a period from when an ignition pulse is generated in the W phase or the Z phase until the next pulse is generated. Similarly, the signal 64 outputs "1" for a period from when an ignition pulse is generated in the U phase or the X phase until the next pulse is generated. The signal 65 remains “1” from when an ignition pulse is generated in the V phase or Y phase until the next pulse is generated.
is outputting. The bypass pair control circuit 10 is
This is a circuit that has been commonly used in the past, and as mentioned above, when it receives a bypass pair command signal, it usually cuts the pulse of the next phase that gives the ignition pulse,
A firing pulse is applied to the next phase of the firing sequence. The order of giving ignition pulses is U phase, Z phase, V phase, X
Phase, W phase, and Y phase, so the reason why the U phase and the In this case, the bypass pair command signal is received and the X phase is fired immediately after the Z phase is fired. Similarly, the V-phase and Y-phase are applied to the bypass pair immediately after the U-phase or
Inputting the Z phase into the bypass pair is the V phase or Y
This is the case when a bypass pair command signal is received immediately after a phase is ignited. Signals 59, 60, and 61 are the same signals as explained in FIG. 5, and when signal 59 is "1", U phase, When 61 is “1”, W phase, Z
Inject the phase into the bypass pair. For this reason, signal 5
9 is "1", it is logically ANDed with the signal 63, and when the output signal of the AND circuit 21-1 is "1", the bypass pair command signal 52 is accepted and the bypass is output from the AND circuit 21-4. By inputting to the pair control circuit 10, the U phase and the X phase become a bypass pair. Similarly, if the bypass pair command signal is received when the AND circuit 21-2 which takes the logical product of the signal 60 and the signal 64 is "1", the V-phase, Y-phase
When the AND circuit 21-3, which takes the logical AND of the signals 61 and 65, is "1", when the bypass pair command signal is received, the W phase and the Y phase become a bypass pair, so the bypass pair input phase is expressed as a ternary value. counter 13
can be controlled sequentially. The ignition state detection circuit 20 can be easily constructed using a flip-flop circuit, and in this embodiment, the effects of the present invention can be obtained by simply adding a simple logic circuit to the conventional bypass pair control circuit.

As explained above, according to the present invention, in a power conversion device that controls a repetitive pattern of load current as required for an accelerator coil power supply,
Even when a specific unit power converter is repeatedly connected to and released from the bypass pair, the current rating of the unit power converter connected to the bypass pair is set to the same current rating as 120° energization during normal operation. It is possible to provide a bypass pair control method for a power conversion device that can perform the following steps.

[Brief explanation of drawings]

Figure 1 is a block diagram of a typical accelerator coil power supply, Figure 2 is a block diagram of a unit power converter, Figure 3 is a load current pattern diagram, and Figure 4 shows W and Z phases forming a bypass pair. FIG. 5 is a control block diagram showing an embodiment of the present invention, and FIG.
Figure 7 is a block diagram of the code conversion circuit, Figure 7 is a diagram showing the functions of the code conversion circuit, Figure 8 is a time chart for explaining the operation of the present invention, and Figure 9 is a diagram of another embodiment of the present invention. FIG. 3 is a control block diagram. 1... AC bus, 2-1, 2-2... Converter transformer, 3-1 to 3-4... Unit power converter, 4
... Load, 5 ... DC current detector, 6 ... Instrument transformer, 7 ... Subtraction circuit, 8 ... Current control circuit,
9... Phase control circuit, 10... Bypass pair control circuit, 11... Pulse amplifier circuit, 12-1 to 1
2-6... Control rectifying element, 13... Ternary counter, 14... Code conversion circuit, 15... Pulse generation circuit, 16, 16-1, 16-2... Inverting circuit, 17-1 to 17- 6...inhibit circuit,
18-1 to 18-6...AND circuit, 19-1 to
19-6...OR circuit, 20...ignition state detection circuit, 21-1 to 21-4...AND circuit, 22...
... OR circuit, 51 ... Current reference, 52 ... Bypass pair command signal, 53 ... Input period, 54 ... Acceleration period, 55 ... Extraction period, 56 ... Deceleration period, 57 ... Ternary counter lower bit , 58...
Upper bit of ternary counter, 59...U phase, X phase bypass pair input order signal, 60...V phase, Y phase bypass pair input order signal, 61...W phase, Z phase bypass pair input order signal, 62... ...Load current pattern, 63...W phase or Z phase is the final firing phase period signal, 64...U phase or X phase is the final firing phase period signal, 65...V phase or Y phase is the final firing phase period signal.

Claims (1)

[Claims] 1. A power conversion device in which at least two or more unit power converters are connected in cascade to supply a repeating pattern current to a load, and a predetermined unit power converter is connected to a bypass pair during a period when the current is approximately constant. A bypass pair control method for a power converter, characterized in that phases of the predetermined unit power converters input to the bypass pair are sequentially controlled according to a repeated load pattern.