JPS64669B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed control device in a microprogram control circuit for an electronic watch.

A microprogram control circuit is a circuit that reads instructions from the peripheral program memory (ROM) and executes them using data memory (RAM), input/output devices (I/O), logic operation circuits (ALU), etc. be. The speed and speed of a clock is to correct the advance or lag of the clock. However, the microprogram control circuit for electronic watches is 1Hz.
In many cases, the high-frequency part is constructed using hardware, such as dividing the frequency up to 1.0, and the adjustment device that processes at high frequencies may have to be constructed using hardware. When speeding up and down is performed from the set terminal or reset terminal of the flip-flop that constitutes the counter of the frequency divider circuit, it is necessary to perform speeding up and down only when the counter reaches a predetermined value, but the speeding up and down command issued from the ROM is extremely Since it is very fast and requires a complex circuit to synchronize with the counter value, it is usually output without synchronization with the counter value. Therefore, when a speeding-up command is issued, speeding-up must not be performed at that time, but only when the counter reaches a predetermined value for the first time.

An object of the present invention is to provide a simple system for a speed control device in such a microprogram control circuit for an electronic timepiece.

Examples will be explained below.

FIG. 3 is a block diagram of a microprogram control circuit according to the present invention.

31 is an oscillation/frequency dividing circuit, which supplies necessary signals to each block. 32 is a ROM section, which includes a program counter that counts the reference signal obtained from the oscillation/frequency divider circuit and specifies the ROM address, a ROM, an instruction register that stores the output of the ROM, and instructions for the instruction register. It has an instruction decoder that decodes the . The command output from 32 is 3
It performs various processing by making full use of 3 RAM and 34 ALU. Reference numeral 35 denotes a speed control circuit according to the present invention. When a speed control instruction is output from the ROM section 32, the command is not executed immediately, but is held once, and the output of the oscillation/frequency dividing circuit 31 is output from a specific speed control circuit. The command is executed only when the value is reached and a signal is issued.

FIG. 1 shows the adjustment device in the present invention, and the second
The figure shows the timing chart. 1 is an inverter, and 2 to 7 are negative trigger master slave flip-flops (hereinafter abbreviated as F.F), which form part of a frequency dividing circuit. One of these days,
3 to 5 have set terminals, and 6 and 7 have reset terminals. The NOR gates 12 and 13 and the inverter 14 are a holding circuit A that holds the speed/speed command issued from the ROM until the speed/speed command is actually slowed down, and in this embodiment, it is composed of a latch circuit. B is a slow/sudden timing forming circuit that forms slow/sudden timing for slowing/fastening. In B, the NAND gate 24 and the inverter 25 are circuits that form the timing to speed up and down from the outputs of the F/Fs 6 and 7. This is a differential circuit that generates a differential signal for resetting the 14 latch circuits. C is a speed control circuit that sets or resets F/F of a specific stage of the frequency dividing circuit. In C,
The inverter 15, the latch circuit 16, and the NOR gate 17 are differentiating circuits that differentiate the outputs of the latch circuits 12 to 14 to form a slowing/fastening signal necessary for slowing down. Reference numeral 22 denotes a circuit that sets or resets F and F in accordance with the speed and speed data of S2 to S4 when the speed and speed signal is obtained. Further, S1 is a 32KHz signal obtained from an oscillation circuit that is a reference signal source, and S5 is a speed/speed command signal output from the ROM 32.

The operation shown in FIG. 1 will be explained based on the timing chart shown in FIG. The 32KHz signal of S1 is frequency-divided by 2 to 7 F.F. The output Q2 of F・F is
16KHz, output Q3 of F.F3 is 8KHz signal, F.
F4 output Q4 is a 4KHz signal, F/F5 output Q
5 is a 2KHz signal, the output Q6 of F/F6 is a 1KHz signal, the output Q7 of F/F7 is a 512KHz signal,
This Q7 is connected to the frequency dividing circuit at the lower stage.
In addition, signals Q2 to Q6 are shown in FIG.
Q7 is not shown. Q11 is the output of the inverter 11 of the slow/sudden timing forming circuit B, and a differential signal is output when the slow/sudden timing comes. Q
Reference numeral 14 is the output of the inverter 14 of the latch circuit A, from which a falling signal is obtained when the speed is slow or fast. Q
Reference numeral 17 is the output of the NOR gate 17 of the adjustment circuit C, and adjustment is performed when a signal is obtained at this Q17. Further, S6 is a signal for controlling reading of the ROM 32. The timing of the slowdown is (Q
3, Q4, Q5, Q6, Q7) = (0, 0, 0,
1,0), which is Q6,7
It is time for the rise of The output Q25 of the inverter 25 becomes Q6,7. 8-11 is Q25
The output Q11 of the inverter 11 is as shown in the timing chart of FIG. 2. S5 is a slow/fast command output from the ROM; when S5 is input, the output Q14 of the inverter 14 becomes HIGH level (hereinafter abbreviated as H level), and when Q11 is output, Q1
4 becomes LOW level (hereinafter abbreviated as L level). Since Q14 falls at the rising edge of Q11 as shown in FIG. 2, the falling differential signal of Q14 may be used as the slow/sudden signal. That is NOR gate 1
7, and is outputted as shown in FIG. The ROM is controlled by the signal S6 in FIG. 2, and the command is output when S6 is at the L level, so that the slow/fast commands S5 and Q11 do not overlap. As is clear from Figure 2,
Instructions are read out from the ROM at high speed, and the readout cycle is completely different from the cycle at which the slow and fast timing occurs. Therefore, when adjusting speed in the microprogram control circuit for a timepiece, it is necessary to hold the adjustment command in the latch circuit A and perform adjustment when the adjustment timing is obtained, as in the present invention. Based on the data of (S2, S3, S4), the outputs of Q3 to Q7 after speeding up and down are as follows. (S2, S3, S4) = (0, 0, 0)
When , (Q3, Q4, Q5, Q6, Q7) = (0,
0, 0, 1, 0) and does not change. (S2,S
3, S4) = (1, 0, 0), (Q3, Q4,
Q5, Q6, Q7) = (1, 0, 0, 1, 0) and progresses for 1/16K seconds. Similarly (S2, S3, S4)
= (0, 1, 0), (1, 1, 0) are each 2/16
K seconds, 3/16K seconds progress. (S2, S3, S4)=
When (0, 0, 1), (Q3, Q4, Q5, Q6,
Q7) = (0, 0, 1, 0, 0), resulting in a delay of 4/16K seconds. Similarly, (S2, S3, S4) = (1,
0, 1), (0, 1, 1), (1, 1, 1),
They are delayed by 3/16K seconds, 2/16K seconds, and 1/16K seconds, respectively.

According to the present invention, the speed and speed can be reliably performed at a predetermined timing no matter when a speed or speed command is issued, and can be configured with a small number of circuits.

[Brief explanation of drawings]

FIG. 1...Example of the slowing/slowing circuit in the present invention,
Fig. 2: Timing chart of the circuit shown in Fig. 1.
FIG. 3: Block diagram of the present invention.

Claims (1)

[Claims] 1. An oscillation circuit that outputs a reference signal, a frequency dividing circuit that is made up of a plurality of cascaded flip-flops that divides the frequency of the reference signal, a program memory that stores instructions, and a logical operation circuit. In a watch microprogram control circuit that processes the execution of read instructions by making full use of the logic operation circuit, etc., a flip-flop at a specific stage of the frequency dividing circuit is set or reset to delay the frequency division or slow down the advance. an adjustment circuit that performs adjustment, a adjustment timing forming circuit that forms adjustment timing that performs adjustment based on the output signal of a flip-flop in a predetermined stage of the frequency dividing circuit, and instructions that are read out from the program memory at a cycle different from the adjustment timing. and a holding circuit that holds a speed/speed command, and the speed/speed circuit performs speed/speed control when the speed/speed command is held in the holding circuit and the speed/speed timing is obtained from the speed/speed timing forming circuit. Microprogram control circuit for watches.