JPS647351B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for adjusting an electronic timepiece.

At present, watches can be mutually divided into two categories. The first class includes primary clocks with autonomous time references. This class includes all wristwatches and widely used alarm clocks.

The second class includes main driven synchronized clocks that receive radio or television signals and secondary clocks that are controlled by a master clock in a clock distribution system.

The first class of clocks includes an oscillator that must generate frequencies as accurate as possible. Mechanical watches require various manipulations of the balance and the balance spring that counterbalances the balance in order to adjust the time and ensure regular running. An analog operation must be performed on the resonator of an electronic clock. Even though the resonator of a quartz clock is originally extremely accurate, precise and expensive operations are required to generate a frequency accurately regardless of temperature.

Fluctuations in frequency cause errors in time display, which increase linearly over time, so an oscillator that generates a frequency as accurate as possible is required.
Furthermore, frequency fluctuations cause the time display to become unstable, which also increases over time. Therefore, it is necessary to frequently set the clock to the correct time to prevent the creeping effects of a less than perfect oscillator.

There are two different types of correction for watches, especially wristwatches.

Frequently performed running adjustment of the clock.

This is done by displacing a regulator acting on the length of the balance spring and is applied to mechanical watches.

Clock time setting as phase adjustment.

This is done by rotating the crown in the pulled out position to drive the hands, and is applied to mechanical watches. Changing the time domain is a special case of time setting.

Various adjustment methods are known for electronic watches.

Adjustment of oscillator frequency by variable capacitance.

Adjustment of the division ratio by a logic mechanism (Swiss patent no. 534913) or an analog mechanism. US Patent No.
No. 3540207 states the principle of prohibition.
A special example using ``inhibition'' is shown.

The adjustment signal is stored in an electrically variable memory (Japanese Patent Laid-Open No. 48-48163, Swiss Patent No. 554015)
issue).

The method of setting the time on electronic watches depends on the display mechanism used. If the display is based on micromotor-driven hands, methods similar to those for mechanical watches can be used to set the time, and a mechanism for blocking high-frequency pulses can be used to ensure accurate adjustment. It can be added.

If the display is electronic, known time-setting mechanisms may employ push-buttons in various positions that allow for accelerations and stops for several seconds separated by minutes and tens of minutes. Yes (US Patent No. 3576099, Swiss Patent No. 510910).

Manual setting of the time setting data with a small number of input elements can be carried out by means of a sequential operating mechanism resulting in various different displays for the data introduced depending on the state of the display at the moment of energization (in particular 1974-8043, Swiss Patent No. 533332
issue).

The latter method stores the adjustment data in an electrically variable memory (Japanese Patent Laid-Open No. 48-48163, Swiss Patent No. 554015).
It can be applied to the running adjustment of electronic watches by storing it in

All of the above adjustment methods must be performed manually. The operator observes the time display for a relatively long period of time, determines the amount of correction, and finally manually adjusts ad hoc members such as regulators, capacitors, and contact sets to compensate for variations in running.

The second class of clocks mentioned above are synchronous clocks that receive time signals. This class does not include watches. There are several reasons for this. Firstly, it is difficult to downsize members such as antennas.
Second, the conditions for receiving the synchronization signal become unstable when the wearer moves around, travels by car, metal parts of buildings act as shields, or when the wearer is far from the city. Third
This is because a strong network covering a large area is required to synchronize the watch even when the wearer is far away.

The device described in Japanese Patent Publication No. 48-48059 and Swiss Patent No. 570651 performs automatic adjustment of the running of an electronic clock simply by applying a signal defining a reference period. This device is similar to the second class in which there is no need to observe the running of the watch before making adjustments. However, electronic watches of this known type often require adjustment at the factory before being put on sale. If adjustment becomes necessary after sale, it is not only necessary to open the watch, but also to send it back to the factory unless the wearer has a special adjustment device for creating a reference signal.

The object of the present invention is to use a telephone system and answering device to adjust the frequency of the time reference of an electronic watch to ensure correct running or to set the electronic watch to the correct time.

Another object of the present invention is to provide the above-mentioned 2 autonomous electronic timepieces with a structure that automatically adjusts an autonomous electronic timepiece by an external signal that can be received simply by making a telephone call without the user having to perform any operation inside the timepiece. It is possible to combine the benefits of two classes of watches.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an electronic timepiece and its adjustment system.
In order to receive the information necessary for adjustment, the electronic clock is used to adjust the output frequency of the split chain in the clock to change by 1 hertz or several hertz (hereinafter referred to as frequency setting), and to set the clock display to the correct time. To match (hereinafter referred to as time setting)
A corresponding input mechanism must be provided. This input mechanism will be described along with the frequency and time settings of the regulation system.

An automatic adjustment circuit 2 and a receiver 3 are provided in the case of an electronic watch 1. The receiver 3 is located in the subscriber's building and connected by line 6 to a telephone system 7 such as a central office.
It is possible to receive a signal 4 extracted by a telephone handset 5, such as a known telephone set, coupled to a telephone. A signal generator 10 is installed in a particular subscriber's premises connected by line 8 to a similar telephone system 7.
and an automatic response device 9 connected to a tape recorder 11
will be established. Tape recorder 11 can supply synchronization pulses to signal generator 10 by line 12.

This system allows an electronic clock to be adjusted via any telephone handset in the manner described below.

In the normal method of operation of a telephone system, a person with an electronic watch 1 calls a particular subscriber corresponding to a line 8 by supplying the appropriate number or calling code to the telephone handset 5. An automatic response device 9 automatically answers the caller and sends a message recorded in advance on a tape recorder 11.
This message is sent to receiver 3 and telephone handset 5.
Instructs how to connect directly between the two. After this message a pulse is sent to the signal generator 10 via line 12. The signal generator 10 is driven by this pulse and sends to the automatic response device 9 a coded message containing the time information and/or reference frequency necessary to adjust the clock. This message is received by telephone handset 5 and sent via receiver 3 to automatic adjustment circuit 2.
The automatic adjustment circuit 2 automatically operates to set the electronic clock 1 according to the information contained in the message.

An electronic timepiece to be adjusted by the system of FIG. 1 must be able to receive information from the adjustment system. For regulating the running or setting the frequency, the frequency of the electronic watch must be set by receiving a signal reference or reference signal of a predetermined period. Such a timepiece, excluding the receiver 3 and the automatic adjustment circuit 2, is described in Japanese Patent Application Laid-Open No. 48-48059 and Swiss Patent No. 570651. In the case of time setting, the configuration of the clock for receiving the time setting signal and correcting it will be described later.

Tape recorder 1 after finishing the coded message
A second message prerecorded in 1 indicates that the clock adjustment is complete.

In other embodiments, each of the above mechanisms 9, 10,
11 in the system's telephone exchange instead of in the subscriber's building. The system operates continuously by means of what is called a "speaking clock," in which messages sent are received simultaneously by many subscribers.

System mechanisms 1, 5, 6, 7, 8, 9, 1
1 is already known and its detailed explanation will be omitted. The receiver 3 and the self-regulating circuit 2 will also be described as being configured for two types of signals: magnetic signals supplied as leakage flux of a transformer, or acoustic signals from the earphone of the telephone handset 5.

Signal generator 10 will also be described for these two types of signals. Signal generator 10 can be divided into two units 13, 14 as shown in FIG.

Unit 13 is driven by pulses sent via line 12 from tape recorder 11;
Three logical signals in the form of 0 or 1, namely the clock signal H, the signal M forming a message containing all the data and complementary data necessary for setting the time of the clock 1 and/or its frequency, and the message being completed. A third signal T indicating this is generated. As will be explained below, unit 14 acts as a radiator and converts these data into signals used in the telephone system and into acoustic or magnetic signals used to couple telephone handset 5 and receiver 3. Based on the extracted signal 4, the receiver 3 generates three logical signals H', M', T' containing the same data as the signals H, M, T, and sends them to the automatic adjustment circuit 2. Different radiators 14 and receivers 3 may be used depending on the type or shape of the signal 4 coupled therebetween. The radiator 14 and the receiver 3 will be described below in the case where the signal 4 is of two types or shapes.

FIG. 3 shows an example of a radiator 14 and a receiver 3 coupled by a signal 4 in the form of a magnetic flux. The corresponding signals are shown in FIG.

The radiator 14 consists of a phase modulator 15 and a binary-ternary converter 16. A phase modulator 15 controlled by a clock signal H and a message signal M receives a signal A.
make.

Message signal M is produced by sequential logic states of 1 and 0, each corresponding to one period of clock signal H, and is displayed only when signal T is 1. In this example, the message signal M is in the order of 100.
The phase modulator 15 is such that when the message signal M is 1 it is 1 during the first half of the clock period and 0 during the remaining half, and conversely when the message signal M is 0 it is 0 during the first half of the period. during the remaining half 1
The message signal M is converted into a signal A such that .

FIG. 5 shows an embodiment of this phase modulator 15,
This example has two inverters, two AND gates, and one OR gate, which function A
shows a circuit connected to achieve =M+H. With this circuit, signal A becomes equal to signal H when message signal M is 0, and equal to the inverted signal of signal H when message signal M is 1.

The binary-to-ternary converter 16, controlled by the signal A and the signal T indicating the transmission of the message, sends the signal B to the automatic response device 9.

That is, the binary-ternary converter 16 converts the signal A into
Signal B is positive when is 1, negative when signal A is 0, and is negative when there is no message (T = 0).
Convert to The average value of signal B is message signal M
It is always 0 regardless of the contents. signal B is signal D,
It is always transmitted without changing the content of the message via a telephone hand system that does not reproduce the C component.

FIG. 6 shows a circuit of the binary-to-ternary converter 16 of FIG. 3 including a pair of complementary transistors T ₁ and T ₂ connected in series between the positive and negative terminals of the power supply. The base of the NPN transistor _T1 is controlled by the output of an AND gate whose two input terminals are connected to the inverse of the signal A and to the signal T. The base of the PNP transistor T ₂ connects its two input terminals to the signal A
connected to the inverted signal of signal T and the inverted signal of signal T
Controlled by the output of the OR gate. Signal B is taken out from the collectors of T ₁ and T ₂ via a coupling capacitor C ₁ . When T is 0, the two transistors are cut off and the signal B becomes 0. If T=1 and A=1
If so, T ₁ is cut off, T ₂ is turned on, and B becomes a positive level. If T=1 and A=0, _T2 is cut off, _T1 is turned on, and B becomes a negative level.

The receiver 3 includes a pick-up coil 17 which takes out the leakage flux of the transformer typically incorporated in the telephone handset 5 or the leakage flux of the earphone of the telephone handset 5. Pick up coil 17
is fixed to the watch as a single coil of a defined size and number of turns to produce a signal of sufficient magnitude.

In order to obtain good coupling during adjustment operations, the electronic timepiece is preferably installed directly on the body of the telephone handset 5, as shown in FIG.

It has been found that the coupling is not so hindered even if the electronic watch has a metal case. The magnitude of the signal extracted by the coil is from tens of microvolts to tens of millivolts, depending on the size of the coil and the number of turns.

The signal B' taken out by the pickup coil 17 is amplified by the amplifier 18 and
The signal is sent to a decimal converter 19, and logic signals C and D are generated.

The signal B' taken out by the pickup coil 17 has substantially the same shape as the signal B. The number of rises or transitions is limited by the upper cutoff frequency of the telephone hand system. Signal B' is amplified by amplifier 18 to a level sufficient for controlling ternary-to-binary converter 19. The ternary-binary converter 19 produces two logic signals C, D. Signal C is 1 only when signal B' is positive, and signal D is
It is 1 only when B' is negative, and signals C and D are simultaneously 0 only when no message is transmitted (B'=0).

Figure 7 shows CMOS that is generally applied to electronic watches.
4 shows a circuit of the amplifier 18 of FIG. 3 using the technique.

The amplifier 18 is constituted by n stages in cascade, each comprising a p-channel transistor T ₄ (constituting the power supply) and an n-channel transistor T ₃ polarized by a resistor R ₂ . Successive stages are connected by capacitor _C2 . An auxiliary circuit consisting of a p-channel transistor _T5 and a resistor _R3 creates a common grid voltage for all transistors _T4 .

Figure 8 shows the ternary version of Figure 3 using CMOS technology.
The circuit of the binary converter 19 is shown. When there is no input signal, transistors T ₆ and T ₇ are connected to corresponding resistors R ₄ and R ₆
is blocked by the presence of Therefore, the output signal D is held at a negative potential (logic 0) by the ballast resistor _R5 . The drain of T ₇ is held positive (logic 1) by a ballast resistor R ₇ . The output signals C of the inverters (negators) T ₈ and T ₉ become 0. While the input signal is positive, T ₆ is cut off, T ₇ is conductive, and the output signal C becomes 1 and the output signal D becomes 0. While the input signal is negative, _T6 is conductive and _T7 is cut off, so that the output signal D becomes 1 and the output signal C becomes 0.

A synchronization unit 20 generates a clock signal H' and a signal T' from the signals C, D and an auxiliary clock signal H'' supplied by the electronic clock 1. A phase demodulator 21 generates a message signal from the signals C, D, H'. Play M′.

Although it is relatively easy to provide an electronic timepiece with a clock signal having a frequency equal to that of the reference clock signal H, it is necessary to create a synchronization mechanism to reliably synchronize these phases. In this example, the electronic watch 1 sends a signal H'' whose frequency is four times H to the synchronization unit 20.
A synchronization signal is generated every four pulses, starting from the first pulse that occurs after
Create H′.

Synchronization unit 20 reproduces a signal T' indicating that a message is being transmitted. The signal T′ is the signal
The first pulse of H' causes the signals C and D to become 1.
becomes 0 when both become 0. Signal H' acts on demodulator 21 to reproduce message signal M' by sampling the value of signal C during the pulse period of synchronization signal H'.

The message signal M' is fully reproduced only when the first bit of the message signal M is 1, and when the first bit of the message signal M is 0, the reproduced message signal M' is inverted (0 instead of 1). and vice versa). This is not a major drawback and it is easy to configure each message to start at 1.

As illustrated by the signal waveform shown in the lower part of FIG. 4, this initial Bits can be thought of as sign bits.

In fact, when signal B' is inverted, signals C and D are exchanged and the first clock signal H' is delayed by half a period. However, the message signal M' obtained by the sampled signal C is correctly reproduced.

FIG. 9 shows the circuit of synchronization unit 20 of FIG. This synchronization unit consists of two RS flip-flops 22, 23 and two T flip-flops 2.
4, 25 and two inverters (negators) 2
6, 27, an OR gate 28, and four AND gates 29-32.

When there is no message, the two input signals C and D are 0, and the four flip-flops 22 to 25 are 0.
is set to Therefore, when there is no message, Q ₁
= 0, T' = 0. This state is maintained as long as signal C remains at 0. When the signal C becomes 1, the output of the gate 29 follows the change of the inverse of H''. Thus, as shown in FIG. 10, when the signal H'' becomes 0, the output signal of the RS flip-flop 22 is delayed from the change in the signal C by half the period of the signal H''.
Q ₁ becomes 1. When the signal H'' changes from 0 to 1, the output of the gate 30 then becomes 1 and the output T' of the RS flip-flop 23 becomes 1. Thus, the signal T' changes from the change in the signal C to half the period of the signal H''. becomes 1 with the following delay: Signal T' and output signal _Q1 are 1 as long as either signal C or D is 1.
It becomes 0 when both signals C and D become 0 (no message). The obtained signal T′ is the fourth
The desired shape is shown in the figure. The remainder of the circuit of FIG. 9 produces the clock signal H'. While signal T′ is 1
An AND gate 31 generates a train of pulses F that follows changes in the auxiliary clock signal H''. These pulses correspond to the signals Q ₂ , Q ₃ and their inverses ₂ , ₃
Two T flip-flops 24, 25 generate
(2 divider). AND gate 32 has an output of 1 only when signals Q ₂ , Q ₃ controlled by signals F, ₂ , ₃ are 0 and signal F is 1, which corresponds to the desired form of signal H'.

When signals C and D become 0 (no message) at the same time, signals Q ₁ , T', Q ₂ and Q ₃ are all 0.
FIG. 10 shows the signal obtained by the circuit of FIG. 9 when the signal H'' becomes 1 and the signal C becomes 1. If the signal H'' becomes 0 at this moment, the signal Q ₁ becomes immediately 1
becomes.

FIG. 11 shows a circuit diagram of a phase demodulator 21 constituted by an RS flip-flop 33 controlled by two AND gates 34, 35. When clock signal H' appears, if signal C=1,
If signal D=0, message signal M' becomes 1 by set input; if signal C=0, signal D
If C=1, the message signal M' becomes 0 due to the reset input, and if C=D=0, that is, when no message is transmitted, the message signal M' does not change.

The radiator-receiver coupling shown in FIGS. 3 to 11 can be applied in the case of modes coupled by the acoustic signal 4. In this case, instead of the pickup coil 17, a microphone is placed adjacent to the telephone earphone during the adjustment operation.

The signal B transmitted in electrical form to the telephone system by the radiator 14 is converted by the telephone earphone into an acoustic signal of similar form. The microphone replacing the pickup coil 17 reconverts this acoustic signal into an electrical signal B.

Embodiments of the invention using acoustic coupling have the disadvantage that the telephone earphone and microphone must have a flat frequency response, ie, be non-resonant. Such a resonance is created by the overamplified component of signal B, and signal B' is distorted to such an extent that reproduction of message signal M' is impossible.

An example of the radiator 14 and the receiver 3 that eliminate such drawbacks is shown in FIG. 12, and the corresponding signal waveforms are shown in FIG. 13.

The radiator 14 includes two oscillators 39, 40 of frequencies f ₁ , f _{2 ,} respectively, connected via transistors 41 , 42 and a coupling capacitor 43 to output terminals that control the automatic response device 9 . Transistor 41, 4
2 are controlled by the outputs of AND gates 36 and 37 which are respectively controlled by signals M, T and T, respectively.

Receiver 3 includes a microphone 44 connected to the input terminal of amplifier 45 . The output terminal of the amplifier 45 is connected to the input terminals of two filters 46, 48 which will send corresponding outputs to detectors 47, 49. The output terminal of the detector 47 sends out the reproduced message signal M', and the output J of the detector 49 sends out the signal
It is connected to one input terminal of an OR gate 50 which controls a synchronization unit 51 which produces T' and H', and a message signal M' is applied to the other input terminal.

The operation of the emitter-receiver coupling is as follows (see Figure 13).

The message signal M to be transmitted is composed of an order of 1's and 0's, for example an order of 100. The signal T is 1 during messages and 0 between messages. When signal T is 0, transistor 4
1 and 42 are not conductive and the signal is 0. Signals T and M
When is 1, transistor 41 is conductive. The signal E thus has the frequency f ₁ of the oscillator 39. M=
0, when T=0, the transistor T ₂ is conductive and the signal E becomes the frequency f ₀ of the oscillator 40. The radiator 14 thus constitutes a frequency modulator which provides a signal E whose frequency changes from f ₁ to f ₀ when the message signal M changes from 1 to 0.

During the adjustment operation, microphone 44 is placed close to the earphone of telephone handset 5, as shown in FIG. The shape of the resulting signal E' is the same as the initial signal E. This signal is amplified by an amplifier 45 and separated into two frequency components f ₁ and f ₀ by filters 46 and 48. message signal M
An alternating current signal F is generated at the output terminal of the filter 46 only when the message signal M is 1, and the filter 48
An alternating current signal G is generated at the output terminal of. This signal is rectified and shaped separately by detectors 47 and 49. Detector 47 receives the reproduced message signal
Make M′ again. The signal C formed by the logical sum of the message signal M' and the output J is sent to the synchronization unit 5.
1 sends data indicating the existence of the message. Synchronization unit 51 is identical to synchronization unit 20 of FIG. 3 and operates similarly except that input signal D is not used.

All components of the radiator 14 of FIG. 12 are known and detailed description thereof will be omitted.

Microphone 44 is fixedly coupled to the watch.
For example, a watch glass can be used as a membrane to which a piezoelectric transducer is mechanically coupled.

In order to obtain good coupling during the adjustment operation, the watch must be placed in front of the telephone earphone as shown in FIG. 21.

Assume that the amplifier 45 is of the circuit shown in FIG. 7, for example. The bandpass filters 46, 48 are active filters that are known in the art, preferably using integrated technology.

The detectors 47 and 49 are, for example, ballast resistors 5 connected in parallel to a capacitor 56 as shown in FIG.
3, a p-channel MOS transistor 52 including
A diode 54 with the grid connected to its source.
and a coupling capacitor 55.

When no AC signal is applied to the input terminal, transistor 52 is cut off by diode 54 and its output becomes - (logic 0). An alternating current signal applied to the input terminal is sent to the grid. Diode 54 prevents the grid potential from rising above voltage + so that an amplitude twice the AC signal appears on the grid.
The transistor conducts each period. Output is voltage +
(logic 1) and is maintained by capacitor 56 until the AC signal disappears.

The above description relates to the part of the device which reproduces the logical message signal M' corresponding to the transmitted message signal M.

The above description includes techniques for transmitting data for adjusting a clock. However, details regarding this data (message signal M) are not explained.
This message signal M can contain extremely complex data necessary for frequency setting and time setting.

The automatic adjustment circuit 2 in Fig. 1 is a message signal.
This is for automatically adjusting the running or frequency of an electronic clock using M' and auxiliary logic signals H' and T'. As mentioned above, frequency adjustment is in state 1.
This is done by supplying the electronic timepiece with a reference signal in the form of a reference signal X as shown in FIG. An electronic timepiece having an input terminal for receiving this reference signal is described in detail in Japanese Patent Laid-Open No. 48-48059 and Swiss Patent No. 570651.

FIG. 15 shows details of the unit 13 and the automatic adjustment circuit 2 for producing such a reference signal to be supplied to the electronic timepiece. FIG. 16 shows signal waveforms at each part in FIG. 15.

The unit 13 generates a clock signal H of a set frequency, for example a clock signal H of exactly 1/16 of the reference signal to be supplied to the clock, as shown in FIG.
includes a time reference 63 that provides a time reference 63; This time standard 6
The clock signal H from 3 is passed through one input terminal of the AND gate 65 to the T flip-flops 66 to 66.
71. gate 6
The other input terminal of 5 is controlled by the output P ₁ of RS flip-flop 64. flipflop 6
The set input terminal S of No. 4 is connected to the tape recorder 11 via line 12, and its reset input terminal R is connected to the tape recorder 11 via line 12.
is controlled by the output P ₇ of flip-flop 71 and the output ₄ of flip-flop 68.
Connect to the output terminal of AND gate 72. Output terminal ₁ of flip-flop 64 is connected to the reset input terminals of T-flip-flops 66-71.
Each output of the T flip-flops 66-70 is coupled to a signal M, which is transmitted to the radiator 14 along with a clock signal H.
It is added to a logic circuit constituted by AND gates 73 to 75 and OR gate 76 to constitute T.

If no synchronizing pulse Y appears on line 12, the output _P1 of flip-flop 64 is 0, and gate 65 is closed so that no signal H reaches flip-flops 66-71, which are maintained at 0 by output ₁ .

The synchronization pulse Y supplied by the tape recorder causes output _P1 to be 1 and opens gate 65 to trigger flip-flops 66-71 which provide signals _P2 - _P7 as shown in FIG. flip flop
When the state of P ₇ =1 and P ₄ =0 is reached, the output of the AND gate 72 becomes 1 and the flip-flop 64 is set to 0.
Set to . Gate 6 by new pulse Y
Flip-flop 64 remains set to 0 until 5 is closed again and the next cycle begins.

During this cycle two successive messages are sent to the radiator 14, denoted by the variable T, which is changed to 1 when P ₄ and P ₅ are 1 at the same time. _P6
When P = 1, P ₂ = 0 or P ₆ = 0, P ₃ = 1, the message signal M becomes 1. The value of the message signal M has value only during the time of the message (T=1) and has no value at other times. In the example in Figure 16, the first message constitutes 1010 and the second message constitutes 1100.
Indicates that the These two messages are used by the automatic adjustment circuit 2 to define the beginning and end of the reference time.

The automatic adjustment circuit 2 receives via the receiver 3 the signals M', T', H' shown in FIG. Automatic adjustment circuit 2
includes a shift register formed by four D flip-flops 77-80 using H' as the clock signal. The input terminal of this register is
M′ is added. The outputs P ₉ to _{P 11} of the flip-flop shown in FIG. 16, their inverted outputs ₈ to ₁₀ , and the inverted output of the output T' obtained from the output terminal of an inverter (negator) 81 are combined in AND gates 82 and 83, respectively. The outputs of AND gates 82 and 83 are applied to an RS flip-flop 84 as its set and reset signals S and R, respectively, to produce a signal X to be supplied to clock 1.

the signal M′ received by the automatic adjustment circuit 2;
T' is equal to the signals M and T transmitted to each other.

The signal H' is very close in frequency to H, but is only present when a message is sent, and in this example consists of four pulses per message, each of these pulses being used to advance one of the shift registers 77-80. used. The states of the outputs P ₁₁ , P ₁₀ , P ₉ , P ₈ for the four pulses H' of the first message correspond respectively to the sequential states 1, 0, 1, 0 of the signal M, respectively. When T' becomes 0, AND gate 82
Since all the inputs of the signal are 1 and the output thereof is 1, the signal X changes to 1.

The states of the outputs P ₁₁ , P ₁₀ , P ₉ , P ₈ for the four pulses H' of the second message correspond to the sequential states 1, 1, 0, 0 of the signal M, respectively. When T' becomes 0, all the inputs of the AND gate 83 are 1 and its output becomes 1, so the signal X returns to 0.

Signal X thus remains at 1 for exactly 16 periods of clock signal H. A reference signal obtained from this clock signal H is supplied to the electronic timepiece 1.

Of course, the contents of the two messages forming the code indicating the beginning and end of the reference time can be changed other than this example. To this end, the combinational logic circuit formed by gates 74-76, 82, 83 in this example has to be modified. Flip-flops 66-70 and shift registers 77-
By increasing or decreasing 80, the number of bits and/or reference time of each message can be changed. Complex codes complicate the circuit, but sufficiently protect the clock adjustment system from interference. The reference time used must be short enough so that the adjustment time is not too long. The reference time must also be long enough to accurately make sufficient adjustments to account for the most abrupt transitions that can be conveyed by the telephone system.

Example: The upper cutoff frequency of a telephone system is approximately 3K
Let it be Hz. If the emitter-receiver shown in FIG. 3 is used, the transition time of signal B' picked up by pickup coil 17 is 100 .mu.s, resulting in an absolute accuracy of the order of 1 .mu.s of the received reference time.
50 to obtain a relative accuracy of 2.10 ^-5 (about 2 seconds per day)
A reference time of ms should be used.

If these values are applied to the circuit of FIG. 15, H will be 320 Hz, just the lower limit of the telephone system passband.

In order to obtain a relative accuracy of 10 ^-6 (1/10 second per day), a reference time of 1 second is required, and in the example of FIG. 15, the clock signal H must have a frequency of 16 Hz. However, such low frequencies cannot be transmitted by telephone systems.

Therefore, it is necessary to select a high frequency clock signal H and modify the flip-flops 66-70 and gates 73-76. However, in principle there is no need to simultaneously transform the start and end codes of the reference time or to modify the automatic adjustment circuit 2 associated with the clock.

FIG. 17 shows an example of a unit 13 and an automatic adjustment circuit 2 for automatically setting the time displayed by a clock having an electronic display according to the system of FIG. In this example, signal M is a signal for setting the time of a clock.

Clocks with electronic displays include electronic counters for seconds, minutes, hours, and date. Setting the time (date) of such a clock includes setting the status of these counters. For the sake of simplicity, in the example shown in Figure 17, only the adjustment of seconds will be considered. However, similar principles can be applied to setting minutes, hours, days, weeks, months and years by analog means.

Unit 13 of FIG. 17 includes a time base 85 providing clock signal H. This clock signal H
controls a series of frequency dividers 86-88, with divider 86 producing a seconds signal _S18 . The divider 87 for counting seconds includes four cells providing four signals S ₉ to S ₁₂ . Divider 8 that counts ten seconds
8 includes three cells providing three signals S ₁₃ to S ₁₅ . The above-mentioned time base 85, dividers 86-88 constitute an electronic clock excluding the display, the seconds being included in coded form in the signals _S9 - _S15 . Line 12 from tape recorder is RS flip-flop 9
0 set input terminal S. The output _S17 of the flip-flop 90 is the output of the RS flip-flop 93.
to AND gate 91 to control the set input S of
Added together with the inverted output of _S18 . The output _S16 of the flip-flop 93 is connected to the AND gate 94 with H and _S18 to generate the control signal CP for the counter decoder 95.
Added with. A first output terminal S0 of the counter decoder ₉₅ supplies the signal T, and the inverted output of the signal T is supplied to the reset input terminal R of the flip-flop 93.
is added along with S ₁₇ to AND gate 92 to control. Second output terminal of canter decoder 95
S ₁ is connected directly to one of the input terminals of OR gate 104. The outputs from the other seven output terminals S ₂ -S ₈ of the counter decoder 95 form the signal M, which corresponds to the corresponding AND gate 97 - 103 whose output terminal is connected to the OR gate _{104 .} ~Added with _S15 . The output terminal S ₂ of counter decoder 95 is coupled to the reset input terminal R of flip-flop 90.

The operation is as follows (see Figure 18).

Unit 13 is operated by conventional means to produce a time reference signal. In the example of FIG. 18, the frequency of clock signal H is 32 Hz. The division ratio of divider 86 for providing second signal S ₁₈ is 32.

When the tape recorder 11 issues the trigger pulse Y, the output _S17 of the flip-flop 90 becomes 1.
Then, as long as S ₁₈ is 0, S ₁₆ will be 1. When _S18 becomes 1, gate 94 opens, CP passes clock signal H, and counter decoder 95 starts counting. The signal _S0 becomes 1 and the signals _S1 to _S8 sequentially become 1 during the corresponding period of the clock signal H.
When S ₂ becomes 1, S ₁₇ is reset to 0. When S ₈ goes to 0, S ₀ goes to 0 and S ₁₆ goes to 0, and the counter decoder 95 stops counting until the next cycle when the gate 94 is closed and triggered by the pulse Y.

Through gates 97-104, sequential pulses S ₁ -S ₈ first sequentially produce 1's and produce corresponding values of S ₉ -S ₁₅ as message signal M. The 8-bit message signal M is thus divided by the states of the dividers 87 and 88, i.e. 1 corresponding to seconds and ten seconds indicating the actual time.
(sign bit) and sequential 0s and 1s.
In this example, message 11010111 corresponds to 57 seconds in binary code.

The automatic adjustment circuit 2 includes a seven cell shift register 105 which receives a clock signal H' and a regenerated message signal M'. A phase unit 106 of seven cells is arranged between a register 105 and counters 109 and 110 constituting the electronic timepiece 1.
Four cell counters 109 count seconds, and three cell counters 110 count ten seconds.

FIG. 19 shows details of the cells of transfer unit 106.

The signal S _o from the corresponding cell of register 105 is transferred to AND gate 113 to create a set signal corresponding to counter 109 (or 110).
Added with. Inverter (negator) 11
The inverted signal of the signal S _o produced by 1 is applied together with the signal TR to an AND gate 112 to produce a corresponding reset pulse.

The transfer signal TR is obtained by the unit 108 by differentiating the inverted output 'of the output T' obtained in the inverter (negator) 107.

In the automatic adjustment circuit 2, the corresponding message signal
M' is sent to shift register 105 and the first bit 1 disappears and is no longer used. At the end of the message, pulse TR controls the transfer of seven bits to counters 109, 110 when T' becomes zero. Their contents will thus be equal to the contents of the corresponding dividers 87, 88, indicating that the clock 1 is displaying the correct time.

The messages used for the adjustment generally contain the data necessary for both the running adjustment and the time adjustment of the electronic watch during the same telephone call. Combining these two adjustment functions of a watch can be easily accomplished by a person skilled in the art.

The embodiments of the present invention will be listed below.

(1) The receiver includes a pick-up coil that is magnetically responsive to a telephone handset.

(2) The receiver includes an element that is acoustically responsive to a telephone handset.

(3) Includes the step of automatically instructing the operator to continue the operation and end the adjustment by verbal messages recorded on a tape recorder.

(4) The telephone handset and the electronic clock are magnetically coupled by the leakage magnetic flux of the transformer of the telephone handset.

(5) A telephone handset and an electronic clock are acoustically coupled.

(6) Includes the step of generating data necessary for adjustment by a signal generator.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the system for adjusting an electronic clock, Figure 2 is a detailed diagram of the signal generator,
Fig. 3 is a block diagram of the radiator and receiver used for magnetic coupling, Fig. 4 is a signal waveform diagram of the radiator and receiver, Fig. 5 is a circuit diagram of the phase modulator, and Fig. 6 is a binary diagram. The circuit diagram of the ternary converter, Figure 7 is the circuit diagram of the amplifier, Figure 8 is the circuit diagram of the ternary-binary converter, Figure 9 is the circuit diagram of the synchronous circuit, and Figure 10 is the circuit diagram of Figure 9. The signal waveform diagram of the circuit, Figure 11 is the circuit diagram of the regenerator, and Figure 12 is the circuit diagram of the regenerator.
The figure is a block diagram of the radiator and receiver for acoustic coupling, Figure 13 is a signal waveform diagram of the radiator and receiver in Figure 12, and Figure 14 is the detector circuit of the receiver in Figure 13. Fig. 15 is a block diagram of the signal generator and automatic adjustment circuit of Fig. 1 for running an electronic clock or automatic frequency setting, Fig. 16 is a signal waveform diagram of the circuit of Fig. 15, Fig. 17 is a block diagram of the signal generator and automatic adjustment circuit shown in Fig. 1 for automatic time setting of a clock, Fig. 18 is a signal waveform diagram of the circuit shown in Fig. 17, and Fig. 19 is a detailed diagram of the cells of the transfer circuit. , FIG. 20 is an explanatory diagram showing the installation of a clock on a telephone handset in the case of magnetic coupling by magnetic flux leakage from a transformer, and FIG. 21 shows the installation of a clock on a telephone earphone in the case of acoustic coupling. It is an explanatory diagram. 1...Electronic clock, 2...Automatic adjustment circuit, 3...
Receiver, 5...Telephone handset, 7...Telephone system, 9...Automatic answering device, 10...Signal generator, 11...Tape recorder, 13, 14...Unit, 15...Phase modulator, 16 ...binary -3
decimal converter, 17...Pickup coil, 18...
...Amplifier, 19...Ternary-binary converter, 20...
Synchronization unit, 21...phase demodulator.

Claims (1)

[Scope of Claims] 1. An oscillator that supplies frequency pulses; and an adjustable frequency divider that receives and divides frequency pulses from the oscillator, the frequency division ratio of which is adjusted in accordance with a reference signal of a predetermined period. , a display mechanism coupled to said adjustable frequency divider for displaying time information; a receiver 3 for receiving a coded adjustment signal 4 emitted from a telephone handset 5 of a telephone system 7; an automatic adjustment circuit 2 coupled to said receiver 3 for sending to said adjustable frequency divider in accordance with a coded adjustment signal 4 necessary for automatically adjusting an electronic timepiece; incorporating into the telephone handset 5 of the telephone system 7 the calling code of the automatic telephone answering device 9 with a mechanism 10 for supplying the automatic telephone answering device 9; An automatic adjustment method for an electronic timepiece, comprising the steps of: installing an electronic timepiece; and causing the automatic adjustment circuit to adjust a division ratio of the frequency divider according to a value included in the coded adjustment signal 4. 2. an oscillator for supplying frequency pulses; a frequency divider for receiving and dividing the frequency pulses from the oscillator; a counter for counting the pulses from the frequency divider; and an electronic display mechanism for displaying the status of the counter. and a receiver 3 for receiving the coded adjustment signal 4 emitted from the telephone handset 5 of the telephone system 7.
and transmitting the state of the counter to the coded adjustment signal 4.
When automatically adjusting an electronic watch having an automatic adjustment circuit 2 coupled to said receiver 3 for correction to a value contained in incorporating the calling code of the automatic telephone answering device 9 into the telephone handset 5 of the telephone system 7; installing the electronic clock to receive the coded adjustment signal 4 sent from the automatic telephone answering device 9; An automatic adjustment method for an electronic timepiece, comprising the step of causing the automatic adjustment circuit to correct the state of the counter according to the value included in the signal 4.