JPS647436B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit between two digital devices whose respective operating frequencies are asynchronous.

Since this type of interface circuit performs writing and reading of the memory circuit asynchronously, it solves the problem of data being read from the wrong address if it is read within the setup time after the read address signal is input. In order to do this, the conventional interface circuit provides a flag signal to inform each other whether writing is possible or reading is possible.The writing side raises the flag after writing is completed, and the reading side raises the flag when the flag is raised. The data is read out from time to time, and the flag is lowered after the readout is completed. Further, information is exchanged by a method in which writing is prohibited on the writing side when the flag is raised, and reading is prohibited on the reading side when the flag is lowered. Therefore, in the conventional interface circuit, the writing side cannot perform the next write operation until after the reading side recognizes that the flag has been raised and finishes the reading operation. Further, the reading side cannot start the next reading operation unless the writing side recognizes that the flag is lowered and finishes the write operation. That is,
A disadvantage is that writing or reading must be controlled depending on the operation of the other side.

The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
To provide an interface circuit in which a write side and a read side are not affected by the operations of the other side, and furthermore, the read side can always execute read operations.

In the present invention, writing and reading of random access memory are performed after a set-up time or more has elapsed from the change point immediately before the change point of the write data signal and the write address signal. It is characterized in that control is performed so that read data is output after a setup time has elapsed after an address is given.

That is, the interface circuit of the present invention includes a first retiming circuit that inputs a write data signal and an address signal, retimes and outputs the signal at the trailing edge of the write signal, and outputs an edge pulse at the leading edge of the write signal. A differential circuit that generates an edge pulse, a first gate circuit that is opened and closed by a read-side control signal to pass or block the edge pulse output from the differential circuit, and a first gate circuit that is set by the edge pulse that has passed through the first gate circuit. A flip-flop is reset at the trailing edge of the read signal asynchronous to the write signal, and the flip-flop is opened and closed by the output of the flip-flop to allow the read signal to pass, thereby controlling the timing of the leading edge change point of the read signal. a second gate circuit that outputs a write enable signal as a write enable signal; and a second gate circuit that receives a write address signal output from the first retiming circuit and a read address signal input from the read side; a selection circuit that selects and outputs the output selectively by the gate circuit; and a selection circuit that uses the output of the selection circuit as an address input and outputs the data signal output from the first retiming circuit before the write enable signal output from the second gate circuit. The present invention is characterized in that it includes a random access memory that writes data according to the edge, and a second retiming circuit that inputs output data of the random access memory and outputs the retiming circuit according to the trailing edge of the read signal.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. That is, data signal _a1 and address signal _a2 input from the write side are input to the first retiming circuit 7 from input terminals 1 and 2, and are determined by the trailing edge of write signal b input from input terminal 3. retiming output. The first retiming circuit 7 is a D-type edge triggered flip-flop having a plurality of data input terminals and output terminals. The data signal _c1 output from the first retiming circuit 7 is supplied to the data input DI of the random access memory 13, and the address signal
c ₂ is supplied to the address input A of the random access memory 13 via the selection circuit 12 . A read address signal i input from the input terminal 6 is also input to the selection circuit 12, and the selection circuit 12 selectively outputs the above two inputs in response to a write enable signal j, which will be described later.

On the other hand, the leading edge of the write signal b is converted into an edge pulse d by the differentiating circuit 8 and input to the first gate circuit 9. The first gate circuit 9 is closed when the read-side control signal e inputted from the input terminal 4 is at a low level, and opened when it is at a high level.
It is a NAND gate. The flip-flop 10 is set by the output signal g of the first gate circuit 9, and the flip-flop 10 is reset by the leading edge of the read signal f input from the input terminal 5. The flip-flop 10 is a D-type flip-flop whose data input D is grounded, the set input S receives the output signal g, and the clock input T receives the read signal f. The inverted output h of the flip-flop 10 and the read signal f are input to a second gate circuit 11, and the output signal of the second gate circuit 11 is supplied to the selection circuit 12 and the random access memory 13 as a write enable signal j. . The second gate circuit 11 is composed of a NAND gate. Random access memory 1
3 is the leading edge (rising edge) of write enable signal j
Then, the write address signal output from the selection circuit 12
Write data signal _c1 to the address specified by _c2 . Thereafter, while the write enable signal j is at a high level, the selection circuit 12 selectively outputs the read address signal i. Therefore, the read data signal l is outputted from the read address of the random access memory 13 and sent to the second retiming circuit 14.
The read data signal m is supplied to the output terminal 15 after being retimed at the trailing edge of the read signal f.

Next, the operation of this embodiment will be explained with reference to the time charts of FIGS. 2 and 3. Second
The figure is a time chart showing the operation when the timing of the fall (leading edge) of the write signal b is within the low level period of the read side control signal e.
FIG. 3 is a time chart showing the operation when the leading edge of the write signal b is within the high level period of the read side control signal e.

First, the case shown in FIG. 2 will be explained. A data signal a as shown in FIG. 2a and a read signal b as shown in FIG.
is input. Address signal _a2 is also similar to data signal a. Trailing edge (rising edge) of write signal b
The data signal c shown in the figure c, in which the data signal a is retimed at
DI, and a similar address signal a ₂ (see FIG. 1) is input to the selection circuit 12. On the other hand, the leading edge (falling edge) of the write signal b is detected by the differentiating circuit 8, and an edge pulse d as shown in FIG.
is output. However, as shown in the figure e, since the read side control signal e is at a low level, the edge pulse d is blocked by the first gate circuit 9.
Therefore, the output signal g of the first gate circuit 9 is
As shown in FIG. 3, the level remains high and the flip-flop 10 is not set. That is, the inverted output h of the flip-flop 10 remains at a high level as shown in h of the figure. Therefore, the read signal f as shown in FIG. The random access memory 13 writes the data signal c input to the data input DI to the write address W at the leading edge (rising edge) of the write enable signal j. The leading edge of write enable signal j rises at the timing of edge pulse d. Then, during the period when the write enable signal j is at a high level, the selection circuit 12 selects and outputs the read address signal i (see i in the same figure), and selects and outputs the read address signal i (see i in the same figure).
Data is output from read address R of . The address signal k output from the selection circuit 12 is shown in FIG.
As shown in FIG. 3, the write address W is shown during the period when the write enable signal j is at the low level, and the read address R is shown when the write enable signal j is at the high level. The read data signal l of the memory 13 is output during the period when the write enable signal j is at a high level, as shown in FIG. The read signal m is output to the output terminal 15. The leading edge of the write enable signal j is before the change point of the data signal c, etc., and is at a point where more than the setup time has elapsed from the previous change point of the data signal c, so the memory 13 is correct. Correct data can be written to the address. Furthermore, since the second retiming circuit 14 performs retiming only after the low level period of the read signal f after the read address signal is applied to the memory 13, the second retiming circuit 14 retimes the data read from the correct address using the read data signal m.
It is possible to output as . Note that the input data signal is indicated by a' or a'' in FIG. 2a, and the write signal is indicated by b' or b'' in FIG. Even if the leading edges (falling edges) are located close to each other, the edge pulses d' and d'' output by the differentiating circuit 8 are similar to d in the same figure.
Since the write enable signal j cannot pass through the first gate circuit 9, the waveform of the write enable signal j is the same as in the previous case. Therefore, when the leading edge of the write signal b is within the low level period of the read side control signal e, operations on the write side and the read side can be performed asynchronously without being aware of the other side.

Next, the operation when the leading edge of the write signal b is within the high level period of the read side control signal e will be described with reference to FIG. The write-side data signal a shown in FIG. 3a is retimed by the first retiming circuit 7 in response to the write signal b shown in FIG. 3b, and the signal c is shown in FIG. 3c. It changes at the trailing edge (rising edge) of write signal b. The same applies to the address signal c ₂ (see FIG. 1) output from the first retiming circuit 7. At the leading edge (falling edge) of the write signal b, the differentiating circuit 8 outputs an edge pulse d as shown in FIG. 3d. Now, the first gate circuit 9 receives the read-side control signal e.
(see e in the same figure), the output signal g of the first gate circuit 9 is open due to the high level of g in the same figure.
The pulse will be as shown in . The flip-flop 10 is set by this pulse, and the read signal f
The flip-flop 10 is reset at the trailing edge (rising edge) (see f in the figure). Therefore, the inverted output h of the flip-flop 10 becomes as shown in FIG. The inverted output h and the read signal f are combined by the second gate circuit 11 to obtain a write enable signal j as shown in FIG. While the write enable signal j is at a low level, the selection circuit 12 selects and outputs the write address signal output from the first retiming circuit 7 and supplies it to the address input of the random access memory 13. Then, the memory 13 writes the data signal c to the write address W at the leading edge (rising edge) of the write enable signal j. During the high level period of the write enable signal j, the selection circuit 12 selects the read address signal i.
(see i in the same figure) is selectively output. Therefore, the address signal k output from the selection circuit 12 becomes as shown in FIG. In the figure, W indicates that a write address signal is selected, and R indicates a read address signal. Even if read address signal i is being selected, address signal k is not output during a period when read address signal i is not input as shown in FIG. The read address signal i is applied for at least a period corresponding to the low level period of the read signal f.
Then, a read data signal l as shown in FIG. 1 is read from the address R of the memory 13, and retimed at the trailing edge (rising edge) of the read signal f, and a read data signal m as shown in FIG. It is output to terminal 15. Therefore, read data m is
Since the data is output after the setup time has elapsed after the read address signal is applied to the memory 13, it is the correct read data from the correct address.
In Figure 3 a, b, c, d, g, h, j, k, a', a'', c', c'', d', d'', g', g'', respectively.
，
The signals indicated by h', h'', j', j'', k', k'', etc. are the signals when the leading edge of the write signal b is toward the end of the high level period of the read side control signal e. Although the signals of each part are shown, it is understood that the read address signal is applied to the memory 13 and output at retiming after the setup time has elapsed, as described above.Also, the rising point of the write enable signal j is before the change point of the write address signal and write data signal, and more than the setup time has elapsed since the previous change point, so the write operation is also performed accurately.In other words, the write operation is performed accurately. The risk of errors occurring when rewriting the memory 13 is avoided by setting the timing earlier than the change point of the data signal c etc. by the period during which the write enable signal is at a low level.

Therefore, no matter where the timing of the write signal b is in the read control signal,
Correct write operations and correct read operations are performed as illustrated. That is, even if the writing side and the reading side are asynchronous, there is an effect that writing and reading can be performed without being restricted by the other side.

As described above, in the present invention, first and second gate circuits and a flip-flop are provided, and the flip-flop is set by the edge pulse generated at the leading edge of the write signal, and the flip-flop is set at the trailing edge of the read signal. Therefore, the flip-flop is reset, the inverted output of the flip-flop and the read signal are combined by a second gate circuit to generate a write enable signal, and the write enable signal determines the write operation point of the random access memory. and a write address signal and a read address signal are switched and controlled by the enable signal and applied to the address input of the random access memory, and the data input and address input of the random access circuit are controlled by the enable signal. The write address is changed at the trailing edge of the write signal, and when the setup time has elapsed after the read address of the random access memory is given, it is retimed and output at the trailing edge of the read signal. A signal is written to the random access memory at least a set-up time after the address and data inputs of the random access memory change, and the read data is retimed after a set-up time has elapsed since the read address signal was applied. can be output. Therefore, there is an advantage that the writing side and the reading side can perform writing or reading operations asynchronously without each other being aware of the other's operation. The present invention assumes, for example, a digital device in which a microprocessor is used on the writing side, and the reading side is operated by an unrelated clock system. Therefore, it is likely to be used in many digital devices that require a control system using a microprocessor or the like, and the range of applications is wide.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIGS. 2 and 3 are time charts showing signals of various parts for explaining the operation of the above embodiment. In the figure, 1 to 6... input terminal, 7... first
retiming circuit, 8...differentiation circuit, 9...first gate circuit, 10...flip-flop, 1
1... Second gate circuit, 12... Selection circuit, 1
3... Random access memory, 14... Second retiming circuit, 15... Output terminal.

Claims (1)

[Claims] 1. A first retiming circuit 7 into which a write data signal and an address signal are input, whose output timing is retimed and outputted according to the rising edge of the write signal, and a read control signal, a read signal, and means 4, 5, 6 for inputting a read address signal; a random access memory 13 for temporarily storing the write data according to the write address and outputting the stored data according to the read address; and an output of the random access memory. An interface circuit comprising a second retiming circuit 14 that inputs data and outputs retiming according to the rising edge of the read signal, a differentiating circuit 8 that detects the falling edge of the input write signal, and this differentiating circuit. a first gate circuit 9 that outputs an output when the read control signal is in one logic;
and a flip-flop 10 which is set by the output of the first gate circuit and reset at the falling edge of the read signal; and a flip-flop 10 which is opened and closed by the inverted output of this flip-flop to allow the read signal to pass and control the rising edge change point of the read signal. a second gate circuit 11 which outputs the write enable signal to the random access memory as a write enable signal; An interface circuit characterized by comprising a selection circuit 12 for selectively outputting to an access memory.