JPS647499B2 - - Google Patents
Info
- Publication number
- JPS647499B2 JPS647499B2 JP16132881A JP16132881A JPS647499B2 JP S647499 B2 JPS647499 B2 JP S647499B2 JP 16132881 A JP16132881 A JP 16132881A JP 16132881 A JP16132881 A JP 16132881A JP S647499 B2 JPS647499 B2 JP S647499B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- electrode
- metal film
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 19
- 230000005611 electricity Effects 0.000 claims description 8
- 230000003068 static effect Effects 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
この発明は、特に集積回路の電極部を改善した
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a semiconductor device in which the electrode portion of an integrated circuit is improved.
一般に半導体集積回路には、電極部が設けら
れ、この電極部を介して例えば半導体素子と外部
配線間が接続される。このような集積回路（例え
ばＣ−MOS回路）は、例えば第１図に示すよう
にＮ型半導体基板（以下単に基板と称する）１１
の表面に所定の間隔をもつて形成されるN+層１
２ａ，１２ｂおよびP+層１３を備え、このN+層
１２ａおよびP+層１３のそれぞれとオーミツク
コンタクトを得るように、アルミニウム等の各金
属膜１４ａ，１４ｂが基板１１の表面に絶縁膜１
５ａ，１５ｂを介して形成される。さらに、この
金属膜１４ａ，１４ｂ間を絶縁する如く、基板１
１の表面に絶縁膜１５ｃが形成される。 Generally, a semiconductor integrated circuit is provided with an electrode section, and, for example, a semiconductor element and external wiring are connected via this electrode section. Such an integrated circuit (for example, a C-MOS circuit) is constructed using an N-type semiconductor substrate (hereinafter simply referred to as a substrate) 11, as shown in FIG.
N + layer 1 formed at a predetermined interval on the surface of
2a, 12b and a P + layer 13, each metal film 14a, 14b made of aluminum or the like is provided with an insulating film 1 on the surface of the substrate 11 so as to obtain ohmic contact with each of the N + layer 12a and P + layer 13.
5a and 15b. Furthermore, the substrate 1 is insulated between the metal films 14a and 14b.
An insulating film 15c is formed on the surface of 1.
このような半導体装置において、例えば入出力
ピン（図示せず）を介してP+層１３の電極であ
る金属膜１４ｂに高電位側の電源電圧が供給され
る。またN+層１２ａの電極である金属膜１４ａ
は低電位側、すなわち接地され、例えばＣ−
MOS回路のラツチアツプ対策として基板１１と
N+層１２ａの両者に接地電位を与える。このよ
うにして、集積回路が構成されるが、上記のよう
な従来の半導体装置の構造では、例えば入出力ピ
ンを介して金属膜１４ｂに過大な静電気が印加さ
れた場合、金属膜１４ｂに対して距離的に一番近
くて電位差の大きい場所である金属膜１４ａに放
電される。このとき、第１図に示す基板１１と絶
縁膜１５ｃの界面部１６等に放電の際の電荷の経
路が形成され、その経路の部分は放電の熱などに
よつて破壊され、すなわち静電破壊が起きる。こ
の静電破壊によつて、例えば金属膜１４ａと上記
界面部１６が電気的に導通状態になるなどの欠点
がある。このような点を防止するために、例えば
金属膜１４ｂに対してN+層１２ａの電極部、す
なわち金属膜１４ａとN+層１２ａのコンタクト
部を遠くに離すことなどが考えられるが、集積回
路の構成上大きな制約を受けることになり困難で
ある。 In such a semiconductor device, a high-potential power supply voltage is supplied to the metal film 14b, which is an electrode of the P + layer 13, for example, via an input/output pin (not shown). Also, a metal film 14a which is an electrode of the N + layer 12a
is on the low potential side, i.e. grounded, e.g. C-
As a measure against latch-up in MOS circuits, the board 11 and
A ground potential is applied to both of the N + layers 12a. In this way, an integrated circuit is constructed. However, in the structure of the conventional semiconductor device as described above, if excessive static electricity is applied to the metal film 14b through the input/output pin, for example, the metal film 14b will be damaged. The electric current is discharged to the metal film 14a, which is the closest place in terms of distance and has a large potential difference. At this time, a path for charges during discharge is formed at the interface 16 between the substrate 11 and the insulating film 15c shown in FIG. happens. Due to this electrostatic breakdown, there is a drawback that, for example, the metal film 14a and the interface portion 16 become electrically conductive. In order to prevent such a problem, it is conceivable to separate the electrode part of the N + layer 12a, that is, the contact part of the metal film 14a and the N + layer 12a, far from the metal film 14b. This is difficult because it is subject to major constraints on its configuration.
この発明は、上記の事情を鑑みてなされたもの
で、電極部に印加される過大な静電気に対して、
基板表面の静電耐圧を大きくして、静電破壊を確
実に防止できる安定で高い信頼性を有する半導体
装置を提供することを目的とする。 This invention was made in view of the above circumstances, and is designed to prevent excessive static electricity from being applied to the electrode section.
It is an object of the present invention to provide a stable and highly reliable semiconductor device that can reliably prevent electrostatic damage by increasing the electrostatic breakdown voltage on the surface of a substrate.
以下図面を参照してこの発明の一実施例につい
て説明する。第２図Ａ，Ｂは、この発明の一実施
例に係る半導体装置の構成を示すもので、図Ａに
示すように、例えばＮ型半導体基板１１の表面に
N+層１２ａ，１２ｂおよびP+層１３が設けら
れ、このN+層１２ａおよびP+層１３のそれぞれ
とオーミツクコンタクトを得るように、アルミニ
ウム等の各金属膜１４ａ，１４ｂが形成される。
そして、この金属膜１４ａ，１４ｂ間を絶縁する
酸化シリコン等の絶縁膜１５ｃが基板１１の表面
に形成され、この絶縁膜１５ｃの表面にアルミニ
ウム等の金属膜２１が形成される。この金属膜２
１は、接地電位を有する如く例えば集積回路の接
地電源ライン（図示せず）に接続される。なお、
他の構成は前記第１図に示す半導体装置と同様で
あるため、説明は省略する。 An embodiment of the present invention will be described below with reference to the drawings. FIGS. 2A and 2B show the structure of a semiconductor device according to an embodiment of the present invention. As shown in FIG.
N + layers 12a, 12b and P + layer 13 are provided, and metal films 14a, 14b, such as aluminum, are formed to make ohmic contact with N + layer 12a and P + layer 13, respectively.
Then, an insulating film 15c made of silicon oxide or the like for insulating between the metal films 14a and 14b is formed on the surface of the substrate 11, and a metal film 21 made of aluminum or the like is formed on the surface of this insulating film 15c. This metal film 2
1 is connected to, for example, a ground power supply line (not shown) of the integrated circuit so as to have a ground potential. In addition,
The rest of the structure is the same as that of the semiconductor device shown in FIG. 1, so the explanation will be omitted.
このような半導体装置において、例えば金属膜
１４ｂに過大な静電気が印加された場合、第２図
Ｂ（平面図で必要な部分のみを示す）に示すよう
に、金属膜１４ｂおよび１４ａ間に接地電位の金
属膜２１が絶縁膜１５ｃを介して設けられている
ため、金属膜１４ｂに対して距離が近く、電位差
の大きい場所である金属膜１４ａと共に接地電位
の金属膜２１にも放電がなされる。すなわち、静
電気による電気力線が分散され、例えば第２図Ａ
に示す基板１１の表面と絶縁膜１５ｃの界面部１
６への電荷の集中を大きく減少できる。したがつ
て、例えば基板１１の表面と絶縁膜１５ｃの界面
部１６の静電耐圧を結果的に大きくすることがで
き、静電気の印加による基板１１の表面の静電破
壊を防止することができる。 In such a semiconductor device, if excessive static electricity is applied to the metal film 14b, for example, the ground potential will drop between the metal films 14b and 14a, as shown in FIG. Since the metal film 21 is provided with the insulating film 15c interposed therebetween, discharge is generated not only in the metal film 14a, which is close to the metal film 14b and has a large potential difference, but also in the metal film 21 at the ground potential. In other words, the lines of electric force due to static electricity are dispersed, for example, as shown in Fig. 2A.
Interface part 1 between the surface of the substrate 11 and the insulating film 15c shown in
The concentration of charge on 6 can be greatly reduced. Therefore, for example, the electrostatic withstand voltage of the interface portion 16 between the surface of the substrate 11 and the insulating film 15c can be increased as a result, and electrostatic damage to the surface of the substrate 11 due to the application of static electricity can be prevented.
なお、上記実施例において、Ｎ型基板１１につ
いて述べたが、これに限ることなくＰ型基板でも
よい。 Although the N-type substrate 11 has been described in the above embodiment, the present invention is not limited to this, and a P-type substrate may be used.
以上詳述したようにこの発明によれば、集積回
路の電極部に印加される過大な静電気に対して、
電極間に接地電位の金属膜を設けることによつ
て、静電気による電気力線を分散し、基板表面の
静電耐圧を結果的に大きくして、静電破壊を確実
に防止でき、安定で高い信頼性を有する半導体装
置を提供できる。 As detailed above, according to the present invention, excessive static electricity applied to the electrode portion of an integrated circuit can be
By providing a metal film with a ground potential between the electrodes, lines of electric force due to static electricity are dispersed, and the electrostatic withstand voltage on the substrate surface is increased as a result. Electrostatic damage can be reliably prevented, making it stable and high. A reliable semiconductor device can be provided.
第１図は従来の半導体装置の構成図、第２図
Ａ，Ｂはこの発明の一実施例に係る半導体装置の
構成図で同図Ａは断面図、同図Ｂは平面図であ
る。
１１……Ｎ型半導体基板、１２ａ，１２ｂ……
N+層、１３……P+層、１４ａ，１４ｂ，２１…
…金属膜、１５ａ，１５ｂ，１５ｃ……絶縁膜。
FIG. 1 is a configuration diagram of a conventional semiconductor device, and FIGS. 2A and 2B are configuration diagrams of a semiconductor device according to an embodiment of the present invention, where FIG. 2A is a sectional view and FIG. 2B is a plan view. 11...N-type semiconductor substrate, 12a, 12b...
N + layer, 13...P + layer, 14a, 14b, 21...
...metal film, 15a, 15b, 15c...insulating film.
Claims (1)
の表面近傍に形成される第１の拡散層に対してオ
ーミツクコンタクトを得るように前記半導体基板
の表面に形成される高電位側の第１の電極と、前
記半導体基板の表面近傍に形成されて前記第１の
拡散層と異なる導電型の第２の拡散層に対してオ
ーミツクコンタクトを得るように前記半導体基板
の表面に形成される低電位側の第２の電極と、前
記第１の電極と第２の電極とを絶縁し前記半導体
基板の表面に形成される絶縁膜と、この絶縁膜の
表面に形成されて前記半導体基板の表面と前記絶
縁膜の界面部に対する静電気による電気力線を分
散させるための接地電位の金属線とを具備したこ
とを特徴とする半導体装置。1. In an input/output section of a semiconductor device, a first electrode on the high potential side formed on the surface of the semiconductor substrate so as to make ohmic contact with a first diffusion layer formed near the surface of the semiconductor substrate. and a low potential side formed on the surface of the semiconductor substrate so as to obtain ohmic contact with a second diffusion layer formed near the surface of the semiconductor substrate and having a conductivity type different from that of the first diffusion layer. an insulating film formed on the surface of the semiconductor substrate to insulate the first electrode and the second electrode; 1. A semiconductor device comprising: a metal wire at a ground potential for dispersing lines of electric force due to static electricity against an interface portion of an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16132881A JPS5861650A (en) | 1981-10-09 | 1981-10-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16132881A JPS5861650A (en) | 1981-10-09 | 1981-10-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5861650A JPS5861650A (en) | 1983-04-12 |
| JPS647499B2 true JPS647499B2 (en) | 1989-02-09 |
Family
ID=15732992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16132881A Granted JPS5861650A (en) | 1981-10-09 | 1981-10-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5861650A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175096U (en) * | 1988-05-30 | 1989-12-13 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS558814B2 (en) * | 1972-05-24 | 1980-03-06 | ||
| JPS5066187A (en) * | 1973-10-12 | 1975-06-04 |
-
1981
- 1981-10-09 JP JP16132881A patent/JPS5861650A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175096U (en) * | 1988-05-30 | 1989-12-13 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5861650A (en) | 1983-04-12 |
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