JPS647545B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention vertically divides a screen into a plurality of sections, generates an electron beam in each section, and deflects each electron beam in the vertical direction for each section. A device for displaying a plurality of lines on a screen to display a television image as a whole, and capable of performing accurate vertical deflection so that each line can be correctly displayed in a predetermined position on the screen. It provides:

Conventionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes have a very long depth compared to the screen size, making it difficult to create thin television receivers. It was impossible. In addition, FL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements.
All of them are insufficient in terms of performance such as brightness, contrast, and color reproducibility of color display, and have not yet been put into practical use.

Therefore, the aim was to create a device that could display color television images on a flat display device using electron beams, and the screen was divided vertically into multiple sections. For each section, each electron beam is deflected vertically to display a plurality of lines, and further divided horizontally into a plurality of sections to display R, G, The phosphors such as B are made to emit light in sequence, and the amount of electron beam irradiation to the phosphors of R, G, B, etc. is controlled by the color video signal, and the television image as a whole is displayed. Something to display was devised.

First, a basic configuration example of the image display element used here will be explained with reference to FIG.

This display element is arranged in order from the back to the front.
Back electrode 1, line cathode 2 as an electron beam source, vertical focusing electrodes 3, 3', vertical deflection electrode 4, electron beam flow control electrode 5, horizontal focusing electrode 6, horizontal deflection electrode 7, electron beam accelerating electrode 8 and screen. Board 9
These are housed in the evacuated interior of a flat glass bulb (not shown). Line cathode 2 as electron beam source
is stretched in the horizontal direction so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of such linear cathodes 2 are arranged vertically at appropriate intervals (here, 2 A to 2 D). (Only books shown) provided. In this embodiment, it is assumed that 15 pieces are provided. Do 2-2. These wire cathodes 2 are constructed by applying an oxide cathode material to the surface of a tungsten wire having a diameter of 10 to 20 μΦ, for example. Then, as will be described later, the electron beams are controlled to be emitted sequentially from the upper line cathode 2a for a fixed period of time. The back electrode 1 creates a potential gradient with a vertical focusing electrode 3, which will be described later, and prevents the generation of electron beams from other line cathodes 2 other than the line cathode 2 which is controlled to emit electron beams for a certain period of time. It has the function of suppressing the electron beam and pushing the generated electron beam forward only. The back electrode 1 may be formed by a coating of a conductive material applied to the inner surface of the rear wall of the glass bulb. Further, instead of the back electrode 1 and the linear cathode 2, a planar electron beam emitting cathode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 10 facing each of the line cathodes 2I to 2Y, and extracts the electron beam emitted from the line cathode 2 through the slit 10, and focus in a direction. The slit 10 may be provided with slits at appropriate intervals in the middle, or may be substantially configured as a slit by a row of many through holes arranged horizontally at small intervals (nearly touching intervals). may have been done. The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally in the middle of each of the slits 10, and are each composed of conductors 13 and 13' provided on the upper and lower surfaces of an insulating substrate 12. has been done. And the opposing conductors 13, 13'
A vertical deflection voltage is applied between them to deflect the electron beam in the vertical direction. In this configuration example, the electron beam from one line cathode 2 is vertically deflected to positions corresponding to 16 lines by a pair of conductors 13, 13'. And, by 16 vertical deflection electrodes 4, 15
Fifteen conductor pairs corresponding to each of the book line cathodes 2 are constructed, and the electron beam is ultimately deflected to draw 240 horizontal lines on the screen 9.

Next, the control electrodes 5 are composed of conductive plates 15 each having a vertically long slit 14, and a plurality of control electrodes 15 are arranged in parallel in the horizontal direction at predetermined intervals. In this configuration example, 320 control electrode conductive plates 15a to 15n are provided (only 10 are shown in the figure). Each of the control electrodes 5 extracts the electron beam horizontally by dividing it into one picture element at a time, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, if 320 control electrodes 5 are provided, 320 pixels can be displayed per horizontal line. In addition, in order to display images in color, each picture element is displayed using phosphors of three colors, R, G, and B, and each control electrode 5 sequentially receives each of the R, G, and B image signals. Added. In addition, 320 control electrodes 5
320 sets of video signals for one line are simultaneously applied to the screen, and one line of video is displayed at the same time.

The horizontal focusing electrode 6 is composed of a conductive plate 17 having a plurality of vertically long slits 16 (320 slits 16) opposite to the slits 14 of the control electrode 5. Each beam is focused horizontally into a narrow electron beam.

The horizontal deflection electrode 7 is composed of a plurality of conductive plates 18 arranged vertically in the middle of each of the slits 16, and a horizontal deflection voltage is applied between each conductive plate 18 for each picture element. The electron beams are each deflected in the horizontal direction, and the R, G, and B phosphors are sequentially irradiated on the screen 9 to cause them to emit light. In this embodiment, the deflection range is the width of one picture element for each electron beam.

The accelerating electrode 8 is composed of a plurality of conductive plates 19 provided horizontally at the same position as the vertical deflection electrode 4, and accelerates the electron beam so that it collides with the screen 9 with sufficient energy.

The screen 9 is constructed by coating the back surface of a glass plate 21 with a phosphor 20 that emits light when irradiated with an electron beam, and adding a metal back layer (not shown). The phosphor 20 is arranged for each slit 14 of the control electrode 5, that is, for each horizontally divided electron beam.
A pair of phosphors in each of the three colors R, G, and B are provided, and are applied in stripes in the vertical direction. In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view in Fig. 2, one section partitioned by these two has R, G, and B phosphors 20 for one pixel in the horizontal direction, and 16 lines in the vertical direction. It has a width of
For example, the size of one section is 1 in the horizontal direction.
mm, and the vertical direction is 16 mm.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

Further, in this embodiment, only one pair of R, G, and B phosphors 20 are provided for one picture element for one control electrode 5, that is, one electron beam, but two
Of course, two or more pairs for more than two picture elements may be provided, and in that case, R, G, and B video signals for two or more picture elements are sequentially applied to the control electrode 5.
Horizontal deflection is performed in synchronization with this.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen 9 with an electron beam to cause the phosphor to emit light and generate a raster will be described.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element,
-V ₁ to the back electrode 1, and -V 1 to the vertical focusing electrodes 3 and 3'.
DC voltages of V ₃ , V ₃ ', V ₆ to the horizontal focusing electrode 6, V ₈ to the accelerating electrode 8, and V ₉ to the screen 9 are applied.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and extracts a vertical synchronization signal V and a horizontal synchronization signal H. The vertical drive pulse generation circuit 25 is constituted by a counter etc. that is reset by the vertical retrace pulse and counts the horizontal pulse, and is configured to operate during an effective vertical scanning period (here, 240H) excluding the vertical retrace period of the vertical period. 15 drive pulses of length of 16H period [a], [b]...
[Y] occurs. This driving pulse [A]...[Y]
are applied to the line cathode drive circuit 26, where they are inverted so that the line cathode drive pulses [A'] and [RO] are brought to a low potential only during each pulse period and to a high potential of about 20 volts for the rest of the pulse period. ′〕…converted to [yo′],
It is added to each wire cathode 2a, 2ro, ...2yo. Each line cathode 2a,...2yo is its driving pulse [a]~
A current is passed during the high potential period of [Y'], and the heated state is maintained so that electrons can be emitted even during the low potential period of the driving pulses [A'] to [Y']. As a result, low potential driving pulses [A'] to [Yo'] were applied from the 15 line cathodes 2A to 2Y, respectively.
Electrons are emitted only during the 16H period. During the period when a high potential is applied, the potential at the line cathode 2 is lower than the potential at the position of the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the vertical focusing electrode 3. Since the applied high potential becomes positive, no electrons are emitted from the line cathodes 2I to 2Y. Thus, in the line cathode 2, electrons are sequentially emitted from the upper line cathode 2a toward the lower line cathode 2y every 16H period during the effective vertical scanning period. The emitted electrons are pushed forward by the back electrode 1, pass through the opposing slits 10 of the vertical focusing electrode 3, and are focused in the vertical direction to form a flat electron beam.

Next, as will be described later, the vertical deflection drive circuit 27 includes a counter that is reset by the vertical synchronizing signal and counts the horizontal synchronizing signal, a digital memory that is addressed by the count output, and a counter that reads data from the digital memory. It is composed of a conversion circuit that D/A converts the digital signal, and each vertical drive pulse [A] ~
During the 16H period of [Y], a pair of step-like waveform vertical deflection signals v and v' that change in 16 steps by 1H are generated. Vertical deflection signals v and v′ are both at the center voltage V ₄
They are designed to change in opposite directions, such that v increases sequentially and v' decreases sequentially. These vertical deflection signals v and v' are applied to the electrodes 13 and 13' of the vertical deflection electrode 4, respectively, and as a result, the electron beams generated from the respective line cathodes 2, 2, 2, and 4 are deflected in 16 steps in the vertical direction. is,
As mentioned above, on the screen 9, one electron beam is deflected so as to sequentially draw a raster line of 16 lines one line at a time from the top.

As a result of the above, electron beams are emitted from the top of the 15 line cathodes 2I to 2Y for a period of 16 hours, and each electron beam is sequentially emitted for one line from top to bottom within 15 sections in the vertical direction. By being deflected, the electron beam is vertically deflected one line at a time on the screen 9 from the first line at the top end to the 240th line at the bottom end, thereby drawing a total of 240 lines of raster.

The electron beam thus vertically deflected is horizontally deflected by 320 degrees by the control electrode 5 and the horizontal focusing electrode 6.
It is divided into sections and taken out. Figure 1 shows one of these categories. The amount of current supplied to each section of this electron beam is controlled by a control electrode 5, and horizontally focused by a horizontal focusing electrode 6 into a single narrow electron beam, which is then controlled by horizontal deflection means described below. The R, G, and B phosphors 2 on the screen 9 are deflected horizontally in three stages.
0 sequentially.

That is, the horizontal drive pulse generation circuit 28 is composed of three cascade-connected monostable multivibrators, etc., and is triggered by a horizontal synchronization signal to generate three horizontal drives with equal pulse widths within one horizontal period. Generate pulses r, g, b. Here, as an example, each pulse width is approximately 17 μsec.
3 during the effective horizontal scanning period of 50μsec.
Three pulses r, g, and b are generated. These horizontal drive pulses r, g, and b are applied to the horizontal deflection drive circuit 29. The horizontal deflection drive circuit 29 generates a pair of horizontal deflection signals h and h' that change in three stages by being switched by the horizontal drive pulses r, g, and b. Both horizontal deflection signals h and h' have a center voltage of V ₇ , and h increases sequentially,
h' change in opposite directions so that they decrease sequentially. These horizontal deflection signals h, h' are applied to electrodes 18 and 18' of the horizontal deflection electrode 7, respectively.
As a result, each horizontally divided electron beam is horizontally deflected so as to sequentially irradiate the R, G, and B phosphors of the screen 9 for 17 μsec during each horizontal period. However, in the display element of FIG. 1, one conductor 18 or one conductor in the horizontal deflection electrode 7
8' is used to deflect the electron beams of two adjacent sections, and the electron beams of 320 sections are deflected in opposite directions to each other. ,
If the objects in the even-numbered categories are deflected in the order of R → G → B, the ones in the even-numbered categories are deflected from B → G.
→R is deflected in the opposite direction every other section.

Thus, in each line raster, the electron beam is divided into R, G,
Each phosphor 20 of B is sequentially irradiated.

Therefore, a color television image can be displayed on the screen 9 by modulating the electron beam with R, G, and B video signals for each horizontal section of each line.

Next, the modulation control portion of the electron beam will be explained.

First, the composite video signal applied to the television signal input terminal 23 is applied to the color demodulation circuit 30,
Here, the color difference signals of R-Y and B-Y are demodulated,
The G-Y color difference signals are matrix-synthesized, and further, they are combined with the luminance signal Y, R,
G and B primary color signals (hereinafter referred to as R, G, and B video signals) are output. Each of those R, G, and B video signals is handled by 320 sample-hold circuit sets 31a.
~31n. Each sample-and-hold circuit set 31a to 31n has three sample-and-hold circuits for R, G, and B, respectively. The sample and hold outputs of these sample and hold circuit sets 31a to 31n are respectively stored in memory sets 32 for holding.
Added to a~32n.

On the other hand, the sampling reference clock oscillator 33
is composed of a PLL (phase locked loop) circuit, etc., and generates a reference clock of about 64 MHz in this embodiment. This reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H. This reference clock is applied to the sampling pulse generation circuit 34, where it is delayed by one clock cycle by a shift register, etc., so that 320 pulses are generated during an effective horizontal scanning period (approximately 50 μsec) of the horizontal period (635 μsec). Sampling pulses a to n are sequentially generated, and one transfer pulse is then generated. These sampling pulses a to n correspond to each picture element when one line of the video to be displayed is divided into 320 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronizing signal H. controlled by.

These 320 sampling pulses a to n correspond to the above 320 sample and hold circuit sets 31.
a to 31n, thereby providing one line to each sample and hold circuit set 31a to 32n.
When divided into 320 picture elements, the R, G, and B video signals of each picture element are individually sampled and held. The sampled and held 320 sets of R, G, and B video signals are stored in 320 sets of memories 32a to 32a after completion of sample and hold for one line.
32n all at once by a transfer pulse t,
Here, it is held for the next one horizontal scanning period.

One line of R, G, and B video signals held in the memories 32a to 32n are applied to 320 switching circuits 35a to 35n, respectively. The switching circuits 35a to 35n each have R, G,
B individual input terminals and a common output terminal that sequentially switches and outputs them, and the output of each switching circuit 35a to 35n is sent to the control electrode 5 of the display element as a control signal for modulating the electron beam.
are individually applied to each of the 320 conductive plates 15a to 15n. Each switching circuit 35a to 35
n are simultaneously switched and controlled by a switching pulse applied from a switching pulse generating circuit 36. The switching pulse generation circuit 36 receives the pulse r from the horizontal drive pulse generation circuit 28 mentioned above.
g and b, and the switching circuits 35a to 35n are switched by dividing the effective horizontal scanning period of about 50 μsec of each horizontal period into three and switching the switching circuits 35a to 35n for about 17 μsec each.
The R, G, and B video signals are time-divisionally output alternately and sequentially, and switching signals r, g, and b are generated to be supplied to the control electrodes 15a to 15n. However, among the switching circuits 35a to 35n, the odd numbered switching circuits 35a, 35c...
The switching circuits are switched in the order B, and the even-numbered switching circuits 35b, 35d...35n are switched in the reverse order B→G→R.

What should be noted here is that the switching circuit 3
The switching of the supply of R, G, and B video signals in 5a to 35n and the horizontal deflection of the horizontal deflection of the electron beam irradiation to the R, G, and B phosphors by the horizontal deflection drive circuit 29 are performed both in timing and order. This means that they are synchronously controlled so that they match perfectly. As a result, when the electron beam is irradiating the R phosphor, the irradiation amount of the electron beam is controlled by the R video signal, and G and B are similarly controlled, so that the R and G of each picture element are controlled in the same manner. , B phosphors are controlled by the R, G, and B video signals of the picture elements, and each picture element is displayed by emitting light according to the input video signal. This control is performed simultaneously on 320 picture elements for one line to display one line of video, and then
One video is displayed on the screen 9 by sequentially processing the 240-minute lines starting from the upper line.

The above operations are repeated for each field of the input television signal, and as a result,
The screen 9 is similar to a normal television receiver.
The television footage of the video is shown above.

As described above, television images are displayed on this display device.

Note that the terms "horizontal direction" and "vertical direction" in the above explanation refer to the horizontal direction, which is the direction in which line units are displayed when an image is projected, and the vertical direction, which is the direction in which the lines are stacked. It is used in this sense, and is not directly related to the vertical and horizontal directions on the actual screen.

As described above, television images are projected on this display device, but due to assembly errors of each electrode during the manufacturing of display elements, the vertical deflection is not uniform, and as a result, the screen The spacing between the lines on the top may become uneven, or the ends of each line may shift vertically.
The scanning lines of each line may overlap or there may be gaps.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a device that can correctly display each raster line on a screen at a predetermined position at a predetermined constant interval when using the above-mentioned image display element. The purpose is to

First, a conventional vertical deflection drive circuit will be explained. FIG. 4 shows the basic configuration of the vertical deflection drive circuit 27. The ring counter 37 receives vertical drive pulses [A]~ from the vertical drive pulse generation circuit 25.
It is reset at each leading edge of [Y], and then the horizontal synchronizing signal H is counted to sequentially generate switching pulses a to π from the 16 output terminals every horizontal period. On the other hand, the variable resistor 38 is provided with 16 output terminals, from which output voltages in 16 stages for vertical deflection are taken out via analog switches 39a to 39π. Each of the analog switches 39a to 39π is sequentially turned on for one horizontal period by switching pulses a to π, respectively, and the level is divided into 16 stages between the lowest terminal and the highest terminal, and the level gradually increases. Waveform output is obtained. The output voltage is taken out via a transistor 40 connected as an emitter follower, its amplitude is adjusted by a variable resistor 41, and further amplified by a class B amplifier circuit 45 composed of transistors 42, 43, and 44, and output. A vertical deflection signal V is produced from terminal 46. On the other hand, the vertical deflection signal V' is also created by a completely similar circuit, but unlike the above case, the analog switch 39
The only difference is that a' to 39π' are switched in the reverse order by the switching pulses a to π, thereby creating a step-like output V' with successively lower levels, which is output from output terminal 46'. Output.

The vertical deflection signals v and v' thus created are applied to the conductive plates 13 and 13' of the vertical deflection electrode 4,
As a result, the electron beam is deflected in 16 steps within each section in the vertical direction, and a raster of 16 lines is drawn with one electron beam.

However, if the distance between the conductive plates 13 and 13' and the position in the front-rear direction vary due to an error in the mounting dimensions of each electrode plate of the vertical deflection electrode 4 during assembly of the display element, the screen 9, each line of the raster is not drawn at the specified position and shifts upward or downward, making it impossible to correctly display each line of the raster at the specified position at a specified regular interval. With conventional circuits, it is difficult to correct or set the deflection position correctly.

In particular, if we decide to set the deflection signals for each of the 240 lines separately, 240 volumes will be required, and if we further correct both the vertical deflection waveforms v and v', twice the 240 volumes will be required. It's not very practical.

Further, the horizontal deflection drive circuit 29 also creates the horizontal deflection waveforms h and h' using the same method as the vertical deflection drive circuit 27, but the horizontal deflection position may vary due to assembly errors of each electrode when manufacturing the display element. deviation, for example R
If other colors (G or B) are irradiated at the time of signal, mislanding will occur and color reproducibility will deteriorate. As a method to eliminate this problem, the deflection waveform was corrected using a volume, but three correction volumes are required for one line, and if 240 lines are corrected, 720 volumes are required. If both horizontal deflection waveforms h and h' are corrected, twice as many volumes as 720 are required, which increases the circuit scale, increases cost, and makes adjustment difficult.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a device equipped with vertical and horizontal deflection circuits that can solve these problems.

An embodiment of the present invention will be described below with reference to FIG. Here, 50 is a microcomputer,
It consists of a CPU 52, an I/O port 53, a first memory 51, a control logic 55, and a key 54. This device will be explained using an 8-bit microcomputer.

56 is a vertical/horizontal deflection circuit, 60 and 61 are a microcomputer data bus and a second memory 6.
2. A bus transceiver for connecting the data bus of the third memory 63. The second memory 62 and the third memory 63 are memories that store data for creating vertical and horizontal deflection signals as digital signals. The first D/A converter 64 to the fourth D/A converter 67 are the second memory 6
The digital signals from 2 and 3rd memory 63 are
This is a D/A converter for A-converting and creating a deflection signal. Further, the first counter 58 is a presettable up counter that counts horizontal period pulses. The second counter 59 is a presettable up counter that counts pulses at three times the horizontal frequency.

The DMA logic 57 performs direct memory access, stops the microcomputer 50, extracts digital signals of deflection data from the second and third memories 62 and 63, and supplies them to the D/A converter.

The data in the second memory 62 and third memory 63 are rewritten and corrected by the microcomputer 50.

The data areas of the second memory 62 and the third memory 63 are as shown in FIG. In the second and third memories 62 and 63, the data areas for vertical deflection signals v and v' are 240 from address a, and deflection data for each line is stored in order. Also, the data area for horizontal deflection signals h and h' is 720 from address b (1 line is 3, 240 lines x 3
= 720), and the deflection data for each line is stored in order.

FIG. 7 shows the first counter 58 and the second counter 5.
9, the first counter 58 is set by the vertical pulse V _P and counts the horizontal pulse f _H ;
Generates a counted digital output. This counter 58 is presettable, from a to a+.
Count to 240. On the other hand, the second counter 59
counts the 3f _H signal created by series connection of monostable multivibrators from f _H , and counts from b to b+720. This counter 59
is also presettable, and the output of b+720 is extracted from b. Each output is time-divided and sent to the address bus (AB) of the microcomputer 50.
connected to.

FIG. 8 is for explaining the overall operation of the microcomputer 50 and the deflection/rotation 56. In FIG. 8, a is a vertical pulse V _P , b is a horizontal pulse f _H , and c is a pulse 3f _H that is three times the horizontal pulse. d is a pulse created by the gate outputs of pulse b (f _H ) and pulse c (3f _H ), and at a low level, the microcomputer 50 enters the operating state and corrects the data in the second memory 62 and third memory 63. be able to. At a high level, the microcomputer 50 stops and the deflection data is transferred from the second memory 62 and third memory 63 to the D/A converters 64 to 64.
7. e indicates the state of address bus AB. During the high level period of _fH , the count output of the counter 58 is supplied, and during the high level period of _3fH , the count output of the counter 59 is supplied.
In the shaded area, the microcomputer 50 is turned on, and the address selected by the microcomputer 50 is output. f is a data bus DB of the microcomputer 50, and data is output only when the microcomputer 50 is in the on state.

G is the data line _L1 of the second memory 62, and during the period when _fH is at a high level, the data D _V0 to D _V240 addressed by a+0 to a+240 are taken out and D/
It is supplied to the A converter 64 and latched at _fH to obtain a vertical deflection signal v as shown in FIG. On the other hand, during the period when 3f _H is at a high level, b+O~b+
Data D _h0 to D _h720 addressed at 720 are taken out, supplied to the D/A converter 65, and latched at 3f _H to produce a horizontal deflection signal h as shown in No. 10.
is obtained.

H is the data line _L2 of the memory 63, and during the period when _fH is at high level, data D _V0 ' to D V240' addressed by a+0 to a+ ₂₄₀ is taken out and supplied to the D/A converter 66, and is input at _fH. After latching, a vertical deflection waveform v' as shown in FIG. 9 is obtained. on the other hand,
During the period when 3f _H is at high level, data D _h0 ′ to D _{h720 ′ addressed by b+0 to b+720} are taken out and D/A
It is supplied to a converter 67 and latched at 3f _H to obtain a horizontal deflection signal h' as shown in FIG.

The memories 62 and 63 are corrected by the microcomputer 50 when the bus transceivers 60 and 63 are in the on state.
1. microcomputer 5
When 0 is in the stop state, bus transceivers 60 and 61 are turned off.

As described above, according to the present invention, the number of components can be reduced by storing deflection signal data in a memory as a digital signal, outputting the memory contents according to the deflection position, and performing D/A conversion. can be made simple and compact. Furthermore, since the data is corrected using a microcomputer, it becomes easy to correct and correct the data.

[Brief explanation of drawings]

Figure 1 is an exploded perspective view showing the basic configuration of the image display element, Figure 2 is an enlarged view of its screen, Figure 3 is a block diagram showing the basic configuration of its drive circuit, and Figure 4 is a conventional vertical drive circuit. 5 is a circuit diagram of a vertical/horizontal drive circuit used in an image display device according to an embodiment of the present invention, FIG. 6 is a memory area diagram thereof, and FIG. 7 is a timing diagram of its counter. , FIG. 8 is a timing diagram of the entire device, FIG. 9 is a waveform diagram of a vertical deflection signal obtained by this device, and FIG. 10 is a waveform diagram of a horizontal deflection signal obtained by this device. 2... line cathode as an electron beam source, 3,3'
...Vertical focusing electrode, 4... Vertical deflection electrode, 5...
Electron beam flow control electrode, 6...Horizontal focusing electrode, 7
...Horizontal deflection electrode, 8...Electron beam acceleration electrode,
9... Screen, 20... Fluorescent material, 23... Input terminal, 24... Synchronization separation circuit, 25... Vertical drive pulse generation circuit, 26... Line cathode drive circuit, 2
7...Vertical deflection drive circuit, 28...Horizontal drive pulse generation circuit, 29...Horizontal deflection drive circuit, 30...
...Color demodulation circuit, 31a to 31n...Sample and hold circuit group, 32a to 32n...Memory group, 34
...Sampling pulse generation circuit, 35a to 35
n... Switching circuit, 36... Switching pulse generation circuit, 50... Microcomputer, 56... Vertical/horizontal deflection circuit, 58, 59...
...First and second counters, 60, 61... Bus transceivers, 62, 63... Second and third memories, 64-67... First to fourth D/A converters.

Claims (1)

[Claims] 1. A screen surface is divided into a plurality of sections vertically and horizontally, an electron beam is generated in each section, and each electron beam is deflected vertically and horizontally for each section. In an image display device equipped with a display element configured to display an image on the screen using a display device, means for creating vertical and horizontal deflection signals for deflecting the electron beam in the vertical and horizontal directions, a digital memory that stores each of the deflection signals as digital signal data; a D-A converter that converts the digital signal read out from the digital memory into an analog signal to produce each of the deflection signals; and a D-A converter for controlling the digital memory. Constructed using vertical and horizontal address counters,
An image display device characterized in that data of each of the deflection signals stored in the digital memory is corrected using a microcomputer. 2 Using the horizontal synchronizing pulse as the input signal of the vertical address counter, access the address of the digital memory with the output of the vertical address counter, convert the digital signal output corresponding to that address from D to A, and input the vertical signal. 2. The image display device according to claim 1, wherein the image display device is configured to obtain a deflection signal of . 3 Use a signal with a frequency n times that of the horizontal synchronization pulse as the input signal of the horizontal address counter,
An address in a digital memory is accessed using the output of the horizontal address counter, and a digital signal output corresponding to the address is D-A converted to obtain a horizontal deflection signal. The image display device according to scope 1.