JPS647592B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a thermal head driving device having a plurality of heating elements, and more particularly to a thermal head driving device that can perform recording at a constant density even if the recording cycle or recording pattern changes. In conventional heat-sensitive type recording devices, when focusing on individual heating elements, if the recording cycle is different for each heating element, differences in recording density occur.
This method has the disadvantage that uneven shading occurs in the recording, reducing image quality. In other words, as the recording cycle becomes shorter, the heat from the previous recording is stored in the heating element, substrate, etc., so their temperature rises and the recording density decreases even though the same energy of recording power is supplied. gradually increases. Therefore, for example, when recording as black-black and when recording as white-black, the second black in the black-black case is recorded better than the second black in the white-black case. It has the disadvantage of high concentration. In order to eliminate the above-mentioned drawbacks, even when recording the same black color, the applied energy for black recording after white can be made larger than the applied energy for black recording after black. Conceivable. In this way, there is a recording method that adjusts the energy of black recording depending on whether the previous bit is black or white.
This method is effective when data is constantly being sent at high speed and is recorded at high speed and at regular intervals. However, if the recording cycle is irregular, it is obvious that the recorded image will have shading when recording is performed at a cycle different from the reference cycle. This will be explained with reference to FIG. 1st
The figure is a diagram showing an example of a temperature change of a heating element when recording black continuously. In the figure, the horizontal axis represents time, the vertical axis represents the temperature of the heating element, and t ₀ and t ₁ represent the recording time during which recording energy is supplied to the thermal head. Also,
T ₁ , T ₂ , and T ₃ are recording cycles, where T ₁ is a reference cycle, T ₂ is a shorter cycle, and T ₃ is a longer cycle. According to the method described above, in the first recording period, standard energy is supplied during time t ₀ , but in subsequent recording periods, energy less than the standard is supplied during time t ₁ (where t ₁ < t ₀ ). Therefore, in the recording period after the first recording period, the temperature rise of the thermal head becomes smaller. This compensates for the heat accumulation effect in the immediately preceding recording period and keeps the recording temperature at an optimum value, as in the second and second recording periods in FIG. However, when the recording cycle becomes _T2 , which is shorter than the standard (the 1st and 1st recording periods in Figure 1), the residual heat or heat storage effect left by the previous recording is large, so the recorded temperature will exceed the optimal value. As a result, the recording density becomes higher than the standard value. Conversely, when the recording cycle reaches T ₃ , which is longer than the standard (the 1st and 1st recording period in Figure 1), there is less residual heat left by the previous recording, so The recorded temperature does not reach the optimum value. Therefore, the recording density will not reach the standard value. As explained above, in the method of correcting and controlling the energy applied to a heating element in the current recording period depending on whether or not the heating element was energized in the immediately preceding recording period, it is possible to compensate for fluctuations in the recording cycle. Therefore, it has the disadvantage of causing uneven recording density. The present invention improves the above-mentioned drawbacks, and even when the recording cycle is indefinite, the energy applied to each heating element of the thermal head, that is, the amount of reduction in recording energy, is controlled in accordance with the cycle, so that recording can be performed. An object of the present invention is to provide a thermal head drive device that does not cause unevenness in density. In order to achieve the above object, the present invention controls (reduces) the recording energy in the current recording period according to the elapsed time from the previous recording to the current recording, and also reduces the recording energy applied in the immediately previous recording period. Additional recording energy is applied to the heating elements that have not been overwritten to perform overwriting. The present invention will be explained in detail below with reference to the drawings. FIG. 2 is a block diagram of one embodiment of the present invention. In the figure, 1 is a thermal head consisting of a large number of heating elements, 2 is a data buffer driver for applying recording energy corresponding to reproduced image data to each of the heating elements, and 3 is a data buffer driver for transmitting image data to the data buffer driver 2. This is a shift register that supplies 4 is an input terminal for a print pulse that determines the activation timing and activation time of each heating element; 5 is an input terminal for a data transfer completion pulse; 6 is a variable delay circuit to which the data transfer completion pulse is input; 7
is an OR circuit which receives the data transfer completion pulse and the output of the variable delay circuit 6 as input, and drives the data buffer driver 2 with its output. Further, 8 is a main line buffer that stores the image data of the main line (the line that is currently being recorded), 9 is a previous line buffer that stores the image data of the line recorded immediately before, and 10 is the image data of the previous line buffer 9. It is a NAND gate that controls the passage of. 11 is a pulse generator (for example, a one-shot multivibrator) that generates a pre-line data calculation pulse for controlling the opening/closing of the NAND gate 10; 12 is the logic of each data at the corresponding bit position of the main line and the previous line; An AND circuit for performing calculations, 13 an address counter for specifying addresses for the previous line buffer 9 and main line buffer 8, and 14 a clock input terminal. FIG. 3 is a detailed block diagram showing an example of the configuration of the variable delay circuit 6 of FIG. 2. In this figure, the same reference numerals as in FIG. 2 represent the same parts. In FIG. 3, 61 is a flip-flop which is set by the data transfer completion pulse supplied to the terminal 5, and 62 is the flip-flop 61.
63 is an integrating circuit that integrates the output of the drive amplifier 62. Further, 64 is a comparator that compares the output of the integrating circuit 63 (terminal voltage of the integrating capacitor C) with the reference voltage Eref, and 65 is a one-shot multivibrator triggered by the output of the comparator 64. Note that E _s is a bias power supply for the integrating circuit 63, and as described later, it can be used to correct the influence of ambient temperature. Next, referring to the time chart in Figure 4,
The operation of the variable delay circuit 6 shown in FIG. 3 will be explained. Fourth
The waveforms indicated by symbols a to d in the figure represent the signal waveforms of the portions with the same symbols shown in FIG. 3, respectively. One line of data is transferred to shift register 3 (second
A data transfer completion pulse a is input to the input terminal 5 every time data transfer is completed. By this,
Since flip-flop 61 is set, its Q output b goes high. Since the Q output is supplied to the integrating circuit 63 via the drive amplifier 62, the integrated output - that is, the terminal voltage of the integrating capacitor C gradually rises as shown in FIG. 4c. When the integrated output reaches the reference voltage Eref, comparator 6
4 becomes high level, and thereby the one-shot multivibrator 65 generates a pulse d as shown in FIG. 4d. This pulse d is input to the reset terminal of the flip-flop 61 to reset it, and at the same time is input to the OR circuit 7 as a delayed latch pulse. Therefore, as can be easily seen from FIG. 4, the delay time τ of the delayed latch pulse d from the data transfer completion pulse a depends on the immediately preceding recording cycle T. That is, the longer the immediately preceding recording cycle T is, the longer the delay time τ becomes, and conversely, the shorter the immediately preceding recording cycle T is, the smaller the delay time τ becomes. Here, the reference voltage Eref is set to a potential corresponding to the optimum recording temperature of each heating element of the thermal head, and the integration time constant of the integrating circuit 63 is equal to the time constant of the thermal response of each heating element of the thermal head. It is set so that If you do this, as is clear from the above explanation, the maximum output of the integrating circuit will always be at the reference voltage.
Since it matches Eref, even if the recording cycle changes, there will be no unevenness in recording density due to the thermal head. Note that it is clear that the delay time τ will change if the bias voltage E _s is changed. Therefore, by controlling the bias voltage E _s according to the ambient temperature, it is also possible to compensate for changes in recording density caused by changes in the ambient temperature. The above-mentioned control according to the ambient temperature can be easily realized by, for example, a voltage dividing resistor circuit including a thermistor as a part. FIG. 5 is a time chart illustrating the operation of the embodiment of the present invention shown in FIG. Each waveform shown in FIG. 5 represents the signal waveform of the portion shown in FIG. 2 with the same reference numeral. Now, image data D _o-1 for one (n-1)th line is stored in the line buffer 8 by an appropriate means, and on the other hand, at this time,
It is assumed that the previous line buffer 9 stores image data D _o-2 of the immediately preceding (n-2)th line. A clock is supplied to the input terminal 14 to operate the address counter 13 and read out signals at the same pixel position in the main line buffer 8 and the previous line buffer 9 at the same time. At this time, since the previous line data calculation pulse e is at the L (low) level, the output of the NAND gate 10 is always at the H (high) level, regardless of the image data D _o-2 . That is, data D _o-2 read from the previous line buffer 9 is prevented from passing. Therefore,
The AND circuit 12 becomes open, and the image data D _o-1 of the main line buffer 8 is transferred to the shift register 3. When the data transfer for one line to the shift register 3 is completed as described above, the data transfer complete pulse a _o-1 is supplied to the terminal 5. this pulse
a _o-1 passes through the OR circuit 7 and becomes the latch signal g,
The image data D _o-1 in the shift register 3 is latched into the data buffer driver 2. At this time, since a print pulse f _o-1 of a fixed duration is supplied to the terminal 4, the thermal head 1 is energized based on the image data D _o-1 , and the corresponding line is Recording is done. The data transfer completion pulse a _o-1 is also supplied to the variable delay circuit 6 and the pulse generator 11, as is clear from FIG. As described above with reference to FIGS. 3 and 4, the data transfer completion pulse a _o-1 supplied to the variable delay circuit 6 corresponds to the immediately preceding recording cycle - that is, in this case,
It is delayed by a time determined according to T _o-2 -, resulting in a delayed latch pulse do _-1 . On the other hand, the pulse generator 11 generates a previous line data calculation pulse e of a constant duration in response to the data transfer completion pulse a _o-1 . Almost simultaneously with the rise of the previous line data calculation pulse e mentioned above, the address counter 13 is activated.
As described above, the signals of the main line buffer 8 and the previous line buffer 9 at the same pixel position are read out at the same time. At this time, the previous line data calculation pulse e is H.
(High) level, the NAND gate 10 outputs data o _{-2, which is the inverted version of the previous line data D o-2 ,} and inputs it to the AND circuit 12. Therefore, the output of the AND circuit 12 is the inverted data _o-2 of the previous line and the data of the main line.
The logical product with D _o-1 becomes D _o-1・_o-2 . The truth table is shown in Table 1. As is clear from Table 1,

[Table] The logical product output of the AND circuit 12 is "1" (high level) only at the pixel position where the data of the previous line is white and the data of the main line is black, and is "0" (high level) at other pixel positions. low level). The AND outputs D _o-1 and _o-2 are supplied to the shift register 3 and stored. When the delayed latch pulse d _o-1 is applied to the data buffer driver 2 via the OR circuit 7, the data stored in the shift register 3 at this time is
D _o-1 and _o-2 are transferred to data buffer driver 2,
Latched. Therefore, if the print pulse f applied to the input terminal 4 is still sustained, the data
Thermal recording, ie overwriting, based on D _o-1 and _o-2 is carried out. However, in the example shown in Figure 5, the delayed latch pulse d _o-1 is generated and the data in the shift register is
D _o-1 and _o-2 are transferred to data buffer driver 2,
When latched, the print pulse f has already disappeared, so no recording (overwriting) is performed based on the data. In other words, in this case, the previous recording cycle
This is an example in which there is no need to compensate for the effects of heat storage because T _o-2 is long enough. Therefore, the heating element which is to record a black bit is supplied with standard energy. When the period of the print pulse f ends, the contents of the main line buffer 8 and the previous line buffer 9 are updated, and each buffer is filled with image data.
D _o and D _o-1 are stored. Next, using the same method as described above, (1) Transfer of the contents D _o of the line buffer 8 to the shift register 3 (2) Image data by the data transfer completion pulse a _o
Transfer _and latch of D _o to the data buffer driver 2 (3) Recording by print pulse f (4) Logical operation D _o・_{o -1} ( 5) Transfer of the data D _o・_o-1 of the logical operation result to the shift register 3 (6) Transfer of the data by the delay latch pulse d _o
Transfer of D _o · _o-1 from the shift register 3 to the data buffer driver 2, latching, etc. are executed one after another. In the timing relationship shown in FIG. 5, when the delayed latch pulse d _o is generated and the data D _o · _o-1 is transferred to the data buffer driver 2 and latched,
The print pulse f is still continuing. Therefore, during the remaining time S, the data D _o・_o-1
Thermal recording is carried out by That is, in this case, as the recording period T _o-1 becomes shorter than the reference value, the thermal recording time using the image data D _o of the main line is shortened (or cut). Then, during the time corresponding to the shortened (or cut) thermal recording time S,
Overwriting is performed by supplying recording energy only to heating elements corresponding to pixel positions where the previous line is white and the main line is black. Regarding the next data D _{o+1 , in} the example of FIG. Logical operation result of _o
Overwriting with the latter half of the record is done by D _o+1・_o . Also, when comparing the recording times of image data D _o and D _o+1 , in the example of Fig. 5, the recording period immediately before the former
Based on the fact that T _o-1 is longer than the latter's T _o ,
It can be seen that the recording time of data D _o is longer. According to experiments conducted by the present inventors, in a thermal head with a width of 216 mm, 8 dots/mm, and a total of 1728 dots, the shift register transfer rate was 2 MHz, the minimum recording period was 5 ms, and the maximum applied power per dot was Set to 0.6W, minimum recording cycle (5ms),
In other words, the main line recording time is 1.0 msec when the amount of heat storage is at its maximum, and the main line recording time is 1.3 m when the recording cycle is long enough and the amount of heat storage is considered to be 0.
When measured in seconds, a good quality record with no uneven shading was obtained. As is clear from the above description, according to the present invention, the shorter the recording cycle, the more the current Since the energy supplied to the heating element during line recording is reduced, the influence of heat accumulation in the thermal head on recording density can be reduced. Furthermore, for the heating elements that did not receive energy supply in the previous line, energy corresponding to the above-mentioned reduction amount was additionally supplied and overlapping recording was performed, so that changes in the black and white dot pattern It is also possible to eliminate unevenness in recording density due to According to the present invention, both of the above factors are combined to achieve extremely stable thermal recording without unevenness in density. In the embodiment described above, only the dot pattern of the previous line is considered, and only at pixel positions where the previous line is white and the main line is black,
Although overwriting was performed, the dot pattern of the previous line was also considered, and the energy applied to the heating element at the pixel position where white-black was recorded was compared to that at the pixel position where black-black was recorded. In addition to increasing the energy applied to the heating element at the pixel position where white-white-black is recorded, it is also possible to perform compensation control so as to further increase the energy applied to the heating element at the pixel position where white-white-black is recorded. Such control can be implemented using the following method and configuration. (1) In addition to the delayed latch pulse d shown in FIG. 2, a second delayed latch pulse having a different delay time is formed to switch the data buffer driver 2 into three stages. (2) A line buffer before the previous line is provided outside the previous line buffer 9, a NAND gate and an AND gate are added, and in addition to the logical operation D _o · _o-1 , an operation D _o · that takes into account the image data of the line before the previous line is performed. _{o-
1.o -2} is performed, data D _o , D _{o.o -1} and D _{o.o - 1.o-2} are transferred to the data buffer driver, latched, and overwritten in three stages. In addition to the above-mentioned circuit, as a means for changing the delay time of the delay latch pulse according to (or as a function of) the immediately preceding recording period T o-1, a counter _that measures the immediately preceding recording period T _o-1 can be used. Count and
It is possible to (1) subtract the count value from the set value and use the difference as the delay time, or (2) use a function generator that inputs the count value.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of temperature change of a heating element to explain the operation of a conventional thermal head drive device, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a detailed block diagram of the variable delay circuit in FIG. 2, FIG. 4 is a time chart for explaining the operation of the variable delay circuit in FIG. 3, and FIG. 5 is a detailed block diagram of the variable delay circuit in FIG. 2. This is a time chart for explanation. 1...Thermal head, 2...Data buffer driver, 3...Shift register, 6...Variable delay circuit, 8...Main line buffer, 9...Previous line buffer, 11...Pulse generator, 61...Flip-flop , 64... comparator, 65... one-shot multivibrator.

Claims (1)

[Claims] 1 Energy corresponding to the image data of the scanning line is applied to the plurality of heating elements that make up the thermal head.
It is a thermal head driving device that records one line at a time by supplying print pulses during the connection time, and includes a main line buffer that stores the image data of one scanning line to be recorded, and a main line buffer that stores the image data of one scanning line to be recorded, and a scanning line that was recorded immediately before. A previous line buffer for storing one line of image data; means for calculating the logical product of the inverted data of the contents of the previous line buffer and the image data at corresponding pixel positions of the contents of the main line buffer; and the image stored in the main line buffer. a means for recording the main line based on the data; and a means for recording the main line based on the image data stored in the main line buffer;
means for shortening the recording cycle as the recording cycle becomes shorter, depending on the recording cycle from line recording to main line recording;
A thermal head driving device characterized by comprising means for causing recording of the main line to be performed repeatedly during the shortened time based on the output of the logical product calculation means.