JPS648385B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a bus control system, and particularly to a bus control system that can simplify bus control means according to the priorities of various devices connected to the bus. It is something.

(2) Prior Art and Problems Conventionally, a synchronous bidirectional bus is used as a bus for implementing this type of bus control system. An example of its configuration is shown in FIG. 1, for example. This bidirectional bus consists of a bus line 1 that transfers addresses and data in a time-sharing manner, and a tag line 2 that identifies whether the information being transferred using bus line 1 is an address or data. and a bus request line 3, and this bidirectional bus has a master function and a slave function, and a plurality of devices D0 and D that mutually transfer data via the bus.
1,...Dn is connected. A plurality of bus request lines 3 are provided corresponding to the respective devices D0, D1,...Dn, and bus request signals from each device D0, D1,...Dn are sent to the corresponding bus request lines BR0, BR1,...BRn, respectively. Will be shipped.
For example, the devices D0, D1,...Dn include a printer,
There are displays, disks, memory control devices, etc., and even if each device D0, D1,...Dn requests the bus in the same way, there is a priority among the devices regarding bus use, and the bus is used in order from the device with the highest priority. It is generally allowed. In FIG. 1, device D0 is a memory control device (MAC) that controls writing and reading of data to memory (MEM) 6, which has the highest bus usage priority among various devices. An example is given. This memory control device D0 includes a bus control circuit 4 connected to a bus request line 3,
A tag circuit 7 connected to the tag line 2 to identify information carried on the bus line 1, a data transmitting/receiving circuit 8 connected to the bus line 1, a bus control circuit 4, a tag circuit 7, and a data transmitting/receiving circuit 8. and a memory control circuit 5 that controls the memory 6 based on the signal. The bus control circuit 4 includes a signal line 11 that sends a bus request signal to a bus request line BR0 corresponding to the memory control device D0 when the memory control device D0 operates as a master, and a signal line 11 that sends a bus request signal to the bus request line BR0 corresponding to the memory control device D0.
When operating as a slave, the bus request line
In addition to BR0, it has a signal line 12 for receiving bus request signals from other devices D1, . . . Dn through bus request lines BR1, . . . BRn.

The other devices D1, . . . Dn are devices that have a lower priority than the memory control device D0 in terms of bus use. These devices D1, ...Dn all have almost the same configuration, and when operating as a master, a bus request circuit sends a bus request signal to the bus request lines BR1, ...BRn corresponding to each device D1, ...Dn. 9, and if this bus request signal is also sent from another device, a bus arbitration circuit 1 detects the priority between the own device and the other device.
0, a tag circuit 7 connected to the tag line 2, and a data transmitting/receiving circuit 8 connected to the bus line 1 and exchanging information with the bus line 1. The bus arbitration circuit 10 detects the priority of the device D1 as described above when the device (for example, D1) operates as a master, and detects the priority of the device D1 as described above, while detecting the priority of the device D1 when the device D1 operates as a slave. Bus request line BR0, BR
1,...BRn to other devices D0, D2,...Dn
It also has the function of receiving bus request signals from.

That is, the memory control device D0 is connected to various devices D0,...
It has the highest priority among Dn, and the bus can be used immediately after sending a bus request signal, so it is only necessary to monitor the bus request line 3 when the slave is activated, whereas other devices D1,... Dn
Since the priority level is lower than second, the bus request line 3 must be monitored both during master operation and slave operation, and therefore the bus control circuit 4 and bus arbitration circuit 10 are They have different functions.

However, in such a conventional bus control system, when looking at the memory control device D0,
The bus control circuit 4 uses bus request lines BR1,...BRn only to monitor the bus request line 3 when the memory control device D0 operates as a slave.
It must be provided with a signal line 12 connected to
The problem was that it was mechanically useless. Also,
This situation runs counter to the recent trend toward LSI components.

(3) Purpose of the Invention The present invention has been made by focusing on the main problem of the prior art, and its purpose is to monitor the bus request line for high-priority devices such as memory control devices. The purpose of the present invention is to solve the above-mentioned conventional problems by providing a bus control system that can be easily configured.

(4) Structure of the Invention In order to achieve the above object, the present invention provides a
A bus line that transfers addresses and data in a time-sharing manner, a tag line that identifies the information being transferred, and a bus line that corresponds to each device, and bus request signals from each device are sent. In a synchronous bidirectional bus having a bus request line, the device with the highest priority in terms of bus usage among the above multiple devices operating as a master or slave is connected to the bus request line corresponding to the device. It has a bus control circuit and a tag circuit connected to the tag line.When operating as a master, the bus control circuit issues a request signal to the corresponding bus request line, while when operating as a slave, the tag circuit issues a request signal to the corresponding bus request line. The gist of this system is to use a circuit to monitor the bus request status of other devices through tag lines. Embodiments of the present invention will be described below with reference to the accompanying drawings.

(5) Embodiment of the Invention FIGS. 2 and 3 show a control circuit for implementing a bus control system according to an embodiment of the present invention. Of these, FIG. 2 is an overall configuration diagram of the bus control circuit, and FIG. 3 is a configuration diagram of the tag circuit, which is the main part of the present invention.

In FIG. 2, the bidirectional bus includes bus line 1, which transfers addresses and data in a time-division manner, and bus line 1.
It consists of a tag line 2 for identifying information transferred using the bus, and a bus request line 3, and this bidirectional bus has a master function and a slave function.
The configuration is basically the same as that of the bus control circuit according to the conventional example described above in that a plurality of devices D0, D1, . . . Dn that mutually transfer data via a bus are connected. However, unlike before, the memory control device (device with the highest priority regarding bus use) D0 is connected only to a specific bus request line BR0 among the bus request lines 3, and the bus request signal is sent to this bus request line BR0. The bus control circuit 14 is connected to the tag line 2 by a signal line 18 to identify the information carried on the bus line 1, while using this tag line 2 to transmit information from other devices D1,...Dn. The tag circuit 17 detects whether a calling command has been issued. That is, in this control circuit, the bus control circuit 14 of the memory control device D0 only has a signal line 11 connected to the bus request line BR0 for master operation, and a signal line (reference numeral in FIG. 1) for slave operation. 12) are omitted. Further, the tag circuit 17 sends a tag signal to the tag line 2 when the memory control device D0 operates as a master.
7, and is configured to detect the presence or absence of a call command through the tag line 2 when the memory control device D0 operates as a slave. This tag circuit 17 runs from the tag line 2 to the signal line 1.
a NAND gate 19 that inverts a signal input through 8; and a NAND gate 19 and bus control circuit 1;
A multiplexer 20 that selects signals from 4
, a tag register 21 that holds the output from the multiplexer, a bus request monitoring circuit 22 that detects the output held in the tag register, and a bus control circuit 1 when the memory control device D0 performs master operation.
A driver 23 sends identification information onto the tag line 2 based on a command from the tag line 2. A resistor 24 is connected to the tag line 2 as its termination circuit E, and a signal "11" is sent onto the tag line 2 when the bus is not in use.

An example will be explained in which the n-th device Dn writes data to the memory 6 using a bus control circuit having such a configuration. The time chart at that time is shown in Figure 4.

(1) Operation at clock timing T0 First, in order to obtain the right to use the bus, the device Dn sends a bus request signal to the bus request line BRn at the first clock timing T0, and also transmits a bus request signal to the bus request line BRn. Check to see if any devices are requesting bus use. At this timing T0, devices D0,...Dn
Since none of them are using the bus, bus line 1 and tag line 2 are in the Hiz state. The tag register 21 holds the state one clock before T0, and the state of the tag line 2 at that time (no signal is output) is held as "00". Further, in the data register (DTR: a register that receives data on the bus line), since no data has been placed on the bus line 1 yet, the data register (DTR) is invalid.

(2) Operation at clock timing T1 Device Dn is bus arbitration circuit 1.
When it recognizes that the right to use the bus is secured by the operation of 0, it sends address and command information on bus line 1 and also sends a tag signal "01" on tag line 2 to identify this address and command information. do. The tag register 21 has timing t.
The state of the tag line at 0 (ie, Hiz state) is held as "00". The data register (DRT) is the bus line 1 at timing T0.
is in the Hiz state and no data is placed on bus line 1, so it is invalid.

(3) Operation at clock timing T2 The device Dn sends write data onto the bus line 1 and also sends a tag signal "10" onto the tag line 2 for identifying this write data. At this timing T2, the signal "01" on the tag line 2 at timing T1 is inverted at the NAND gate 19, and the tag register 21 receives the signal "01" on the tag line 2 at timing T1.
The signal is held as “10”. Further, the data register (DTR) holds address/command information after it is placed on the bus line 1 at timing T1.

Note that the above series of clock timings T0,
At T1 and T2, the bus request monitoring circuit 22 in the tag circuit 7 of the memory control device D0 constantly detects the state of the tag register 21.
It monitors the presence or absence of bus requests from other devices D1, . . . Dn. If no device is using the bus, tag line 2 is in the Hiz state, but
Since the logic "11" is outputted by the final end circuit 24, this signal is inverted by the NAND gate 19 and the signal "00" is set in the tag register 21 (timing of T0 and T1).

Then, at this timing T2, "10" is set in the tag register 21, so
Memory controller D0 recognizes that a bus request exists. And the contents of the data register (DTR) that holds the contents of the bus (memory write commands and memory addresses are held)
Activate the memory 6 according to the following.

(4) Operation at clock timing T3 Since the write data was sent onto bus line 1 at the previous timing T2, bus line 1 and tag line 2 are at Hiz as before the start of this operation.
state, and the device Dn receives a response indicating that the write operation to the memory 6 has been completed. On the other hand, tag register 21
At timing T2, the signal "01" on the tag line 2 is inverted by the NAND gate 19 and held as the signal "01". In addition, in response to the write data being placed on the bus line 1 at timing T2, the data register (DRT)
This write data is retained.

Furthermore, looking at the memory control device D0,
This memory control device D0 is at this timing T3.
Confirm that the write data has been sent by detecting the tag register 21 at
Write the data to memory 6.

(5) Operation at clock timing T4 Bus line 1 and tag line 2 are operated at the previous timing T3.
As in the case of , it is in Hiz state. The signal "00" is held in the tag register 21 in response to the Hiz state of the tag line 2 at timing T3. Further, the data register (DTR) becomes invalid in response to the Hiz state of the bus line 1 at timing T3.

On the other hand, the memory control device D0 sends a bus request signal to the bus request line BR0, and then uses the bus line 1 to notify the device Dn that the data write operation to the memory 6 has been completed.

This completes the operation of the device Dn to write data into the memory 6.

In this way, in the present invention, when the device with the highest priority operates as a slave, it checks whether there is a bus request by monitoring the tag line 2. Therefore, compared to the conventional bus control device, the signal line is can be significantly reduced.

In this embodiment, the bus request circuit 9 is omitted for the device with the lowest priority (temporarily referred to as device Dn), so that no bus request signal is sent. And this device
Dn is all other devices D0 at the timing of T0,
...Check the Dn-1 bus request signal,
If none of the other devices listed above has issued a bus request, it is determined that they have the right to use the bus,
At the next timing T1, the address/command information is sent to the bus line 1 and the tag signal is sent to the tag line 2. The subsequent operations are similar to those described for each timing above.

(6) Effects of the Invention As explained above, according to the present invention, among devices connected to a bus and having a master function and a slave function, the device with the highest priority is assigned a bus corresponding to the device. It is equipped with a bus control circuit connected to the request line and a tag circuit connected to the tag line, and when the slave is activated, the tag line is monitored to check whether there is a bus request from another device. Various effects can be obtained, including the ability to reduce the number of signal lines and signal pins, and to fully meet demands such as LSI.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit for implementing a conventional bus control method, FIG. 2 is a diagram showing an embodiment of a control circuit for implementing the bus control method of the present invention, and FIG. 3 is a diagram showing a circuit for implementing a conventional bus control method. FIG. 4 is a diagram showing a configuration example of a tag circuit used in the control circuit shown in the figure, and FIG. 4 is a diagram showing a time chart in an example of use of the control circuit shown in FIG. 1... Bus line, 2... Tag line, 3... Bus request line, 4, 14... Bus control circuit, 5... Memory control circuit, 6... Memory, 7, 17... Tag circuit, 8... ...Data transmission/reception circuit, 9...Bus request circuit, 10...Bus arbitration circuit, 19...NAND gate section, 21...Tag register, 22...Bus request monitoring circuit, 23...Driver, D0, D1, …Dn……(master, slave).

Claims (1)

[Claims] 1 A bus line for time-sharing transfer of addresses and data between multiple devices having master and slave functions, a tag line for identifying the information being transferred, and a bus line for each device. In a synchronous bidirectional bus having a bus request line and a bus request line to which bus request signals from each device are sent, the device that has the highest priority in terms of bus use among the plurality of devices described above that selectively operate as master or slave. A device with a high value has a bus control circuit connected to the bus request line corresponding to the device and a tag circuit connected to the tag line, and when operating as a master, the device has a bus control circuit connected to the bus request line corresponding to the device, and a tag circuit connected to the tag line. A bus control system characterized in that, while operating as a slave, a tag circuit monitors the bus request status of other devices through a tag line.