JPS64854B2 - - Google Patents
Info
- Publication number
- JPS64854B2 JPS64854B2 JP17066382A JP17066382A JPS64854B2 JP S64854 B2 JPS64854 B2 JP S64854B2 JP 17066382 A JP17066382 A JP 17066382A JP 17066382 A JP17066382 A JP 17066382A JP S64854 B2 JPS64854 B2 JP S64854B2
- Authority
- JP
- Japan
- Prior art keywords
- retransmission
- pulse
- period
- pulses
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/18—Circuits for visual indication of the result
- H03K21/20—Circuits for visual indication of the result using glow discharge lamps
Landscapes
- Measuring Volume Flow (AREA)
Description
【発明の詳細な説明】
本発明は、入力パルスにスケーリングを施した
後再発信パルスとして出力する再発信パルス発生
装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a retransmission pulse generator that scales an input pulse and then outputs it as a retransmission pulse.
一般にタービン流量計等のパルス発信式流量計
では、通過流体の単位容積当りのパルス数が、例
えば1当り12.42発というような区切りのよい
値でない。このため積算流量を求める場合等にお
いては、パルス発信式流量計からの入力パルスに
スケーリングを行い、例えば1当り10発という
ような単位パルスに変換して再発信することが行
われている。この場合従来は、入力パルスを与え
られたスケーリング定数K(例えば10/12.42)に
対して決められた原則にしたがつてできるだけ等
間隔(定周期)に近いように間引いて、例えば入
力パルスが1000発入力されたとき、再発信パルス
を805発出力するようになつている。このように
従来は等間隔に近いように間引いているだけなの
で、正確な等間隔性が保たれておらず、いわばリ
ツプルを含んだ信号になつている。リツプルは低
周波になる程大きい。したがつて、再発信パルス
を混合調節計のデマンドパルス(設定値)として
用いた場合は、制御出力のリツプルが大きく、安
定性が悪かつた。 Generally, in a pulse generation flowmeter such as a turbine flowmeter, the number of pulses per unit volume of passing fluid is not a well-defined value, such as 12.42 pulses per unit volume. For this reason, when calculating the cumulative flow rate, the input pulses from the pulse emitting type flowmeter are scaled and converted into unit pulses, such as 10 pulses per pulse, and then retransmitted. In this case, conventionally, the input pulses are thinned out to be as close to equal intervals (fixed period) as possible according to the principle determined for a given scaling constant K (for example, 10/12.42), so that the input pulses are When a signal is input, it outputs 805 retransmission pulses. In this way, in the past, the signals were simply thinned out so that the intervals were close to equal, so accurate equidistantness was not maintained, resulting in a signal containing ripples, so to speak. The ripple becomes larger as the frequency becomes lower. Therefore, when the retransmitted pulse was used as a demand pulse (set value) of the mixing controller, the ripple of the control output was large and the stability was poor.
本発明の目的は、等間隔性にすぐれた再発信パ
ルスを連続的に発生できる再発信パルス発生装置
を実現するにある。 SUMMARY OF THE INVENTION An object of the present invention is to realize a retransmission pulse generator that can continuously generate retransmission pulses with excellent uniform intervals.
本発明は、入力カウンタで入力パルスを計数
し、この計数値を測定周期毎に読取りスケール定
数を乗じて再発信パルス数を得るとともに、入力
パルス周期にスケール定数の逆数を乗じて基準再
発信パルス周期を算出し、この基準再発信パルス
周期の逆数にあらかじめ設定した再発信パルス起
動周期を乗じて基準再発信パルス数を得、再発信
パルス出力回路に設定する再発信パルス数が基準
再発信パルス数に係数を乗じた値になるように再
発信パルス周期を制御するようにして、上述の目
的を達成できる再発信パルス発生装置を実現した
ものである。 The present invention counts input pulses with an input counter, reads this counted value every measurement period, multiplies it by a scale constant to obtain the number of retransmission pulses, and multiplies the input pulse period by the reciprocal of the scale constant to generate a reference retransmission pulse. Calculate the period, multiply the reciprocal of this standard retransmission pulse period by the preset retransmission pulse activation period to obtain the standard retransmission pulse number, and the number of retransmission pulses set in the retransmission pulse output circuit is the standard retransmission pulse. By controlling the retransmission pulse period so that the retransmission pulse period becomes a value obtained by multiplying the number by a coefficient, a retransmission pulse generator that can achieve the above-mentioned object is realized.
第1図は本発明装置の一実施例を示すブロツク
図である。図において、1は入力パルスPiを計数
する入力カウンタ、2は再発信パルス数演算回
路、3はバツフアレジスタ、4は入力パルス周期
検出回路、5は基準再発信パルス周期演算回路、
6は基準再発信パルス数演算回路、7は設定回
路、8は正規化回路、9はPI演算回路で、PI演
算部ΔPIと加算部Σとからなり速度形のPI演算を
行うものが例示されている。10は再発信パルス
周期演算回路、11は再発信パルス出力回路で、
パルス周期およびパルス数が設定されると、再発
信パルスPoを設定された周期で設定された数だ
け出力するとともに、出力し終えると再発信パル
スエンド信号Peを発生するものである。 FIG. 1 is a block diagram showing one embodiment of the apparatus of the present invention. In the figure, 1 is an input counter that counts input pulses Pi, 2 is a retransmission pulse number calculation circuit, 3 is a buffer register, 4 is an input pulse period detection circuit, 5 is a reference retransmission pulse period calculation circuit,
6 is a reference retransmission pulse number calculation circuit, 7 is a setting circuit, 8 is a normalization circuit, and 9 is a PI calculation circuit, which is composed of a PI calculation section ΔPI and an addition section Σ and performs speed type PI calculation. ing. 10 is a re-transmission pulse period calculation circuit; 11 is a re-transmission pulse output circuit;
When the pulse period and number of pulses are set, the retransmission pulse Po is outputted by the set number of retransmission pulses Po at the set period, and when the output is finished, a retransmission pulse end signal Pe is generated.
このように構成した本発明装置の動作を第2図
のタイムチヤートを用いて以下に説明する。第2
図において、イは正常状態のときのタイムチヤー
トで、ロは周期が早くなり過ぎたときのタイムチ
ヤートである。まず、再発信パルス数演算回路2
は測定周期Δt毎に入力カウンタ1の計数値を読
取りスケール定数Kを乗じて再発信パルス数Ni
を出力する。この再発信パルス数Niはバツフア
レジスタ3で加算される。一方入力パルス周期検
出回路4は、測定周期毎に入力カウンタ1の計数
値から入力パルスPiの周期Tiを検出して基準再
発信パルス周期演算回路5に与え、入力周期Ti
にスケール定数の逆数1/Kが乗ぜられ、基準再
発信パルス周期Tsが算出される。その値は測定
周期毎に更新される。この基準再発信パルス周期
Tsが基準再発信パルス数演算回路6に加えられ、
Tsの逆数にあらかじめ設定した再発信パルス起
動周期(例えば測定周期と同じ周期)Taを乗じ
て基準再発信パルス数Nsを出力する。この基準
再発信パルス数Nsが設定回路7に加えられ、あ
らかじめ設定した係数nを乗じて設定値SVを出
力する。ここで、係数nを乗じているのはSVに
位相遅れを持たせ、バツフアレジスタ3に溜めを
設けることによつて、第2図ロに示すように周期
が早くなり過ぎたときの待ち時間TLによる出力
リツプルが、安定状態で出ないようにするためで
ある。なおnを大きくすると位相遅れが大きくな
るので、本実施例ではn=2として、SVを1周
期遅れにし、バツフアレジスタ3に1周期分の溜
めを設けてある。この設定値SVと測定値PVであ
るバツフアレジスタ3の内容Nとの差が正規化回
路8に加えられ、
eo=nNs−N/Ns (1)
なる正規化演算を行つた後、PI演算回路9に加
えられる。PI演算回路9は正規化回路8の出力eo
に、比例ゲインをKp、積分時間をKIとして、演
算部ΔPIで、
Δα=Kp{(eo−eo―1)+KIeo} (2)
なる演算を行い、その結果Δαが加算部Σに与え
られ、速度形のPI演算を行う。ところで、SV値
nNsとPV値Nとの差を正規化回路8で正規化演
算を行つた後PI演算延回路9に加えているのは、
周波数によつてΔαが変らないようにするためで
ある。PI演算回路9の出力αが再発信パルス周
期演算回路10に与えられ、基準再発信パルス周
期Tsとの間で、
Tj=Ts(1−α) (3)
なる演算が行われ、再発信パルス周期Tjが算出
される。すなわち、再発信パルス周期Tjは再発
信パルス数が基準再発信パルス数Nsになるよう
にαが制御される。この再発信パルス周期Tjと
バツフアレジスタ3からの再発信パルス数Njが
再発信パルス出力回路11に再発信パルスエンド
信号Peに同期して設定される。このときバツフ
アレジスタ3からの再発信パルス数Njの設定は
バツフアレジスタ3に格納されている再発信パル
ス数Nと、基準再発信パルス数Nsとを比較して、
NNsであればNj=Nとなり、N>Nsであれば
Nj=Nsとなる。再発信パルス出力回路11は再
発信パルスPoを設定された周期で設定された数
だけ出力し終えると、再発信パルスエンド信号
Peを出力する。再発信パルスエンド信号Peがバ
ツフアレジスタ3および再発信パルス周期演算回
路10に与えられ、次に出力する再発信パルスの
周期Tjおよびパルス数Njを再発信パルス出力回
路11に設定させ、同様な手順で連続的にパルス
周期を変化させながら、再発信パルスPoの発生
を続ける。具体的には第2図イに示すようにl番
目にサンプリングした入力パルスPiの処理が終了
した後、l+1番目の周期にl−1番目の入力パ
ルスに対する再発信エンドが来るように制御され
る。 The operation of the apparatus of the present invention constructed as described above will be explained below using the time chart shown in FIG. Second
In the figure, A is a time chart under normal conditions, and B is a time chart when the cycle becomes too fast. First, retransmission pulse number calculation circuit 2
reads the count value of input counter 1 every measurement period Δt, multiplies it by the scale constant K, and calculates the number of retransmitted pulses Ni
Output. This number of retransmission pulses Ni is added by the buffer register 3. On the other hand, the input pulse period detection circuit 4 detects the period Ti of the input pulse Pi from the count value of the input counter 1 for each measurement period and supplies it to the reference retransmission pulse period calculation circuit 5.
is multiplied by the reciprocal of the scale constant 1/K to calculate the reference retransmission pulse period Ts. The value is updated every measurement cycle. This reference re-transmission pulse period
Ts is added to the reference retransmission pulse number calculation circuit 6,
The standard number of retransmission pulses Ns is output by multiplying the reciprocal of Ts by a preset retransmission pulse activation period (for example, the same period as the measurement period) Ta. This reference number of retransmission pulses Ns is added to the setting circuit 7, multiplied by a preset coefficient n, and a set value SV is output. Here, the reason why the coefficient n is multiplied is that the SV has a phase delay, and by providing a reservoir in the buffer register 3, the waiting time when the cycle becomes too fast as shown in FIG. This is to prevent output ripple caused by TL from appearing in a stable state. Note that as n increases, the phase delay increases, so in this embodiment, n=2, the SV is delayed by one cycle, and the buffer register 3 is provided with a reservoir for one cycle. The difference between this set value SV and the content N of the buffer register 3, which is the measured value PV, is added to the normalization circuit 8, and after performing the normalization calculation e o = nNs - N/Ns (1), PI It is added to the arithmetic circuit 9. The PI calculation circuit 9 is the output e o of the normalization circuit 8.
Then, with the proportional gain as Kp and the integration time as K I , the calculation section ΔPI performs the calculation Δα = Kp {(e o − e o ― 1 ) + K I e o } (2), and as a result, Δα is added. part Σ and performs velocity-type PI calculations. By the way, the SV value
The difference between nNs and PV value N is normalized in the normalization circuit 8 and then added to the PI calculation extension circuit 9 as follows.
This is to prevent Δα from changing depending on the frequency. The output α of the PI calculation circuit 9 is given to the retransmission pulse period calculation circuit 10, and the calculation Tj=Ts(1−α) (3) is performed between it and the reference retransmission pulse period Ts, and the retransmission pulse A period Tj is calculated. That is, α of the retransmission pulse period Tj is controlled such that the number of retransmission pulses becomes the reference number of retransmission pulses Ns. This retransmission pulse period Tj and the number of retransmission pulses Nj from the buffer register 3 are set in the retransmission pulse output circuit 11 in synchronization with the retransmission pulse end signal Pe. At this time, the number of retransmission pulses Nj from the buffer register 3 is set by comparing the number of retransmission pulses N stored in the buffer register 3 with the reference number of retransmission pulses Ns.
If NNs, Nj=N, if N>Ns
Nj=Ns. When the retransmission pulse output circuit 11 finishes outputting a set number of retransmission pulses Po at a set period, it outputs a retransmission pulse end signal.
Output Pe. The retransmission pulse end signal Pe is given to the buffer register 3 and the retransmission pulse period calculation circuit 10, and the retransmission pulse output circuit 11 is set to the period Tj and the number of pulses Nj of the retransmission pulse to be output next. The retransmission pulse Po continues to be generated while changing the pulse period continuously according to the procedure. Specifically, as shown in Fig. 2A, after the processing of the lth sampled input pulse Pi is completed, the retransmission end for the l-1st input pulse is controlled to occur in the l+1st period. .
また1回の再発信パルス数の最大値をNsとし
ているので、入力パルス数が急激に増え一時的に
バツフアレジスタ3の内容Nが大きくなつても、
短かい周期で再発信エンドして、周期をその都度
短かくしてゆき大き過ぎる分を速くはき出すこと
ができる。1回の再発信パルス数の最大値を制限
しない場合には、バツフアレジスタ3の内容が大
きくなると、その数分パルスが出力されるまで周
期を変えることができず、大き過ぎる分のはき出
しに時間がかかる。 Also, since the maximum value of the number of retransmitted pulses at one time is set to Ns, even if the number of input pulses increases rapidly and the content N of the buffer register 3 temporarily increases,
It is possible to end the re-transmission in a short cycle, shorten the cycle each time, and send out the excessively large amount quickly. If the maximum number of pulses to be retransmitted at one time is not limited, if the contents of buffer register 3 become large, the cycle cannot be changed until that many pulses have been output, and too many pulses will be exposed. it takes time.
以上説明したように本発明においては、入力パ
ルス周期およびスケール定数の逆数とから算出し
て得た基準再発信パルス周期と、あらかじめ設定
された再発信パルス起動周期とによつて基準再発
信パルス数を算出し、入力パルス数およびスケー
ル定数とから得た再発信パルス数が前記基準再発
信パルス数になるように再発信パルス周期を制御
しているので、等間隔性にすぐれた再発信パルス
を連続的に発生できる再発信パルス発生装置が得
られる。 As explained above, in the present invention, the number of reference retransmission pulses is calculated based on the reference retransmission pulse period calculated from the input pulse period and the reciprocal of the scale constant, and the preset retransmission pulse activation period. is calculated, and the retransmission pulse period is controlled so that the number of retransmission pulses obtained from the number of input pulses and the scale constant becomes the reference retransmission pulse number, so retransmission pulses with excellent uniformity can be generated. A retransmission pulse generator is obtained which can generate continuous pulses.
なお第1図に一点鎖線で囲まれた再発信パルス
数演算回路2、バツフアレジスタ3、入力パルス
周期検出回路4、基準再発信パルス周期演算回路
5、基準再発信パルス数演算回路6、設定回路
7、正規化回路8、PI演算回路9および再発信
パルス周期演算回路10としては、マイクロコン
ピユータを用い、これらの機能をソフトウエアの
プログラムで実現してもよい。この場合再発信パ
ルス出力回路11からの再発信パルスエンド信号
Peでマイクロコンピユータに割込をかけること
になる。 In addition, the retransmission pulse number calculation circuit 2, the buffer register 3, the input pulse period detection circuit 4, the reference retransmission pulse period calculation circuit 5, the reference retransmission pulse number calculation circuit 6, and the settings are surrounded by a dashed line in FIG. A microcomputer may be used as the circuit 7, the normalization circuit 8, the PI calculation circuit 9, and the retransmission pulse period calculation circuit 10, and these functions may be realized by a software program. In this case, the retransmission pulse end signal from the retransmission pulse output circuit 11
Pe will interrupt the microcomputer.
第1図は本発明装置の一実施例を示すブロツク
線図、第2図はその動作説明のためのタイムチヤ
ートである。
1…入力カウンタ、2…再発信パルス数演算回
路、3…バツフアレジスタ、4…入力パルス周期
検出回路、5…基準再発信パルス周期演算回路、
6…基準再発信パルス数演算回路、7…設定回
路、8…正規化回路、9…PI演算回路、10…
再発信パルス周期演算回路、11…再発信パルス
周期演算回路。
FIG. 1 is a block diagram showing one embodiment of the apparatus of the present invention, and FIG. 2 is a time chart for explaining its operation. DESCRIPTION OF SYMBOLS 1...Input counter, 2...Retransmission pulse number calculation circuit, 3...Buffer register, 4...Input pulse period detection circuit, 5...Reference retransmission pulse period calculation circuit,
6... Reference re-transmission pulse number calculation circuit, 7... Setting circuit, 8... Normalization circuit, 9... PI calculation circuit, 10...
Retransmission pulse period calculation circuit, 11...Retransmission pulse period calculation circuit.
Claims (1)
入力カウンタの計数値を測定周期毎に読取りスケ
ール定数を乗じて再発信パルス数を演算する再発
信パルス数演算回路と、この再発信パルス数演算
回路の出力を加算するバツフアレジスタと、前記
入力カウンタの計数値を測定周期毎に読取り入力
パルス周期を演算し、この入力パルス周期に前記
スケール定数の逆数を乗じて基準再発信パルス周
期を得る周期検出回路と、この基準再発信パルス
周期とあらかじめ定めた再発信パルス起動周期と
から基準再発信パルス数を得る基準再発信パルス
数演算回路と、この基準再発信パルス数にあらか
じめ設定した係数を乗じた値を設定値とし、前記
バツフアレジスタの内容を測定値としてPI演算
回路でPI演算を行い、前記バツフアレジスタの
内容が前記基準再発信パルス数に係数を乗じた値
になるように再発信パルス周期を制御する手段
と、この再発信パルス周期が設定され、前記バツ
フアレジスタの内容および前記基準再発信パルス
数とから再発信パルス数が設定されて再発信パル
スを出力する再発信パルス出力回路とを有した再
発信パルス発生装置。1. An input counter that counts input pulses, a retransmission pulse number calculation circuit that calculates the number of retransmission pulses by reading the count value of this input counter every measurement cycle and multiplying it by a scale constant, and this retransmission pulse number calculation circuit. A buffer register that adds the output, and a period detection method that reads the count value of the input counter every measurement period, calculates the input pulse period, and obtains the reference retransmission pulse period by multiplying this input pulse period by the reciprocal of the scale constant. circuit, a reference retransmission pulse number calculation circuit that obtains a reference retransmission pulse number from this reference retransmission pulse period and a predetermined retransmission pulse starting period, and a reference retransmission pulse number calculation circuit that calculates a reference retransmission pulse number by a preset coefficient. A PI calculation is performed in the PI calculation circuit using the value as the set value and the content of the buffer register as the measurement value, and retransmission is performed so that the content of the buffer register becomes the value obtained by multiplying the reference retransmission pulse number by a coefficient. means for controlling a pulse period; and a retransmission pulse output for outputting retransmission pulses with the retransmission pulse period set and a retransmission pulse number set from the contents of the buffer register and the reference retransmission pulse number. A retransmission pulse generator having a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17066382A JPS5961227A (en) | 1982-09-29 | 1982-09-29 | Device for generating recall pulse |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17066382A JPS5961227A (en) | 1982-09-29 | 1982-09-29 | Device for generating recall pulse |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5961227A JPS5961227A (en) | 1984-04-07 |
| JPS64854B2 true JPS64854B2 (en) | 1989-01-09 |
Family
ID=15909061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17066382A Granted JPS5961227A (en) | 1982-09-29 | 1982-09-29 | Device for generating recall pulse |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961227A (en) |
-
1982
- 1982-09-29 JP JP17066382A patent/JPS5961227A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5961227A (en) | 1984-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4716535A (en) | Speed detection apparatus | |
| JPS64854B2 (en) | ||
| JP2002071435A (en) | Measuring equipment | |
| US5431056A (en) | Method for depth compensation of amplitudes of echo-signals in an ultrasonic measuring device which uses the pulse-echo-technique | |
| JP3271323B2 (en) | Time measurement circuit | |
| JP3126219B2 (en) | Frequency measurement device | |
| JP2869524B2 (en) | SQUID type magnetic force measuring device | |
| JP3213796B2 (en) | Servo motor controller | |
| JPH0750001B2 (en) | String vibration type force measuring device | |
| JPS6319831B2 (en) | ||
| JP3419341B2 (en) | Flow measurement device | |
| JPS60147653A (en) | Speed detector | |
| JP2902233B2 (en) | Flow compensation device | |
| JP2827446B2 (en) | Motor speed detection method | |
| JPS6087523A (en) | Recalling pulse generator | |
| JPS6311662Y2 (en) | ||
| JPS60201278A (en) | Digital counting rate meter | |
| RU2105341C1 (en) | Optimal regulator | |
| JPS61226803A (en) | Process control device | |
| WO1990012456A1 (en) | Frequency multiplier circuitry and method | |
| SU836532A1 (en) | Device for control of batch-weighing scale | |
| SU911454A1 (en) | Time interval measuring device | |
| JPH0243201B2 (en) | ||
| JPS63313014A (en) | Reoutput pulse generating device | |
| JPH0133053B2 (en) |