JPS649590B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a device for detecting the median value of received electric field strength used for evaluating line quality in land mobile communications.

(Prior Art) It is well known that in land mobile communications, the received field strength of received radio waves is subject to fading due to the movement of the mobile station, and fluctuates drastically over several tens of dB. To evaluate the received electric field strength in an environment where such faging exists, it is common practice to use a statistical median value determined from the envelope of the received wave. Conventionally, a device for detecting this statistical median value (hereinafter referred to as the median value) uses a comparator to compare the estimated value of the median value at the present moment with the envelope level of the received wave detected after that point. , the magnitude and frequency ratio are smoothed and calculated by an integrator, the amount of error from the state with a frequency of 50% is detected, and the negative feedback type follow-up circuit moves the estimated value in the direction of reducing the error. Most of them are structured in this way. However, in a detection circuit with such a configuration, the feedback circuit including the integration has a fixed time constant, so it is not possible to accurately follow the receiving input that fluctuates rapidly, and the The drawback was that the value could not be given as defined.

Note that the following documents exist as conventional techniques.

Reference 1: Matsumoto, Adachi; Digital received electric field median detection circuit in mobile communications. Proceedings of the 1981 National Conference of the Institute of Electronics and Communication Engineers No.2157p8-200 Reference 2...Kobayashi, Nakata; Digital processing type reception level detection circuit. Proceedings of the 1985 National Conference of the Institute of Electronics and Communication Engineers No. 2463 p10-163 The following document also states that when the received wave envelope fluctuates over several tens of dB, it is first logarithmically compressed and then sampled at a constant period. The effective number of samples and sampling frequency are shown when statistically estimating the average power or voltage expressed in decibels from the samples obtained.

Reference 3: Adachi, Yoshida; Effective number of samples and sampling frequency in statistical estimation of average received power under Rayleaf aging. Journal of the Institute of Electronics and Communication Engineers '81/6vol.J64-B, No.6pp.556-557 Reference 4... Adachi; Statistical estimation of the median received voltage in Rayleaf aging. Journal of the Institute of Electronics and Communication Engineers '81/4vol.J64-B, No.4pp.336-337 (Objective of the Invention) The present invention has been made to eliminate the drawbacks of the conventional device. The objective is to be able to estimate the statistical median value as defined from the frequency distribution of the envelope of the received wave within the range, and also to be able to follow fluctuations in the median value by shifting the interval from time to time.

(Configuration of the Invention) FIG. 1 is a block diagram showing an example of the configuration of a received electric field median value detection device embodying the present invention. Symbol 1 in this figure is an A/D (analog-digital) converter, and its input L is the envelope output of the received wave or analog level information of its logarithmically compressed value.
The A/D converter 1 converts the input L into digital level information _LD0 for each pulse of the sampling clock SCL supplied from outside the device. 2 is a shift register which sequentially inputs LD ₀ at the timing of SCL and stores n samples (an appropriate value of n will be explained later). Its output LD _o is the level information after n samples delay. Reference numeral 3 denotes a timing generation circuit that generates various timing pulses necessary for a series of control sequences for median value detection calculations for each pulse of the sampling clock SCL. 4 is
RAM (random access memory) stores the frequency distribution of level information required for median detection calculations. 5 is an address switching circuit that switches the address A of the RAM 4. 6 is an address scanning circuit, RAM
4. Scan all addresses in one cycle. The address switching circuit 5 outputs LD ₀ , LD _o and the address scanning output AS of the address scanning circuit 6 according to the gate switching signals G _p , G _o , G _s outputted from the timing circuit 3, respectively.
is switched and output as address A of RAM4. The address scanning circuit 6 is activated by the gate switching signal _Gs from the timing circuit 3, and performs address scanning of the RAM 4 at the timing of the address scanning clock ACL also from the circuit 3. 7 is an increment circuit which has the function of adding +1 to the content D read from the RAM 4 and storing it at the original address, and is activated by the signal G _p from the timing circuit 3. 8 is a decrement circuit having a function of subtracting by -1 in contrast to 7, and is activated by the signal Gn. Reference numeral 9 denotes an integrating circuit which, when the address scanning circuit 6 scans all the addresses in the RAM 4, integrates all the contents in synchronization with this and generates a cumulative frequency pattern of digital values in its integrated output SUM. A comparator 10 compares the absolute values of digital data. One of these inputs is SUM
The other one is the cumulative frequency constant M that gives the median value.
It is. And the output DET of comparator 10 is SUM
It becomes H level when the condition M is satisfied. 11 and 12 are registers that store and output input data;
stores and holds the contents of the output AS of the address scanning circuit 6 at the time when the output DET of the comparator 10 rises from L level to H level, and further outputs the memory holding output.
The register 12 stores and outputs ASm in synchronization with the sampling clock SCL of the A/D converter 1. This output LDm becomes the median value detection output of the level distribution of the latest n samples.

(Operation of the Invention) The operation of the apparatus having the configuration shown in FIG. 1 will be explained below with reference to FIGS. 2 and 3. However, for convenience of explanation, the number n of samples of level information for detecting the voltage median value and the number of level divisions are both set to 11 for simplification.

Figure 2 is an example of the memory contents of RAM4, where the horizontal axis is address A, and the vertical axis is the data content D of each address.
The values for each are taken and expressed in a bar graph. The number in parentheses is the value of D. Here, the values 0 to 10 (11 levels) of address A correspond to the divisions ₀ to 10 of the value of level information output LD 0 of A/D converter 1, and A = RAM address = level information.
The data value D of each address indicates the number of times the corresponding level information was obtained. With this kind of response
The RAM 4 has a function of storing the frequency distribution for each level information value.

Every time a new LD ₀ is obtained at the start of reception, the increment circuit 7 uses LD ₀ as an address to increment the data value (=frequency) of the corresponding address.
If you increase this and continue this for n (= 11) samples, the level frequency distribution for the initial n samples becomes
Obtained in RAM4. If the frequency distribution at this point is as shown by the thick solid line in Figure 2, when a new LD ₀ is obtained in the next sample, the new set of n samples will be n from the new LD ₀ to just before LDn.
It becomes a set of level information for RAM4 to LDn.
will be thrown away. Therefore, it is necessary to update the frequency distribution to correspond to the new n samples.

For example, if LD ₀ = 2 and LDn = 6, the frequency of level 2 will be increased by +1 [(1) → (2) as shown in Figure 2], and the frequency of level 6 will be decreased by 1 [( 4)→
(3)], it is clear that new samples are added and old samples are deleted, and a new frequency distribution of n samples is obtained. In FIG. 2, this change in frequency distribution is shown by a dashed line with diagonal lines.

Based on the creation of the initial value of the frequency distribution and its update procedure as described above, and by applying the example in Figure 2, A/D
Figure 3 shows a time chart of an example of an operation in which the frequency distribution is updated in response to a new set of n samples for each sample of the level information output from the converter 1, and the median value is detected from this. .

In FIG. 3, the horizontal axis indicates the passage of time, and symbols SCL to LDm at the left end indicate each signal shown in FIG. 1. Of these, from SCL to ACL and
DET is the binary signal explained in FIG. 1, and its binary values H (signal present) and L (signal absent) are displayed at the right end of FIG. Also A (address), ASm
(sample output of register 11) and LDm (sample output of register 12) represent the contents by writing numerical values in large and small rectangular parts. D (RAM4
data content) and SUM (integration output of integration circuit 9)
The format is the same as in Figure 2 except that the horizontal axis represents the passage of time.

Now, the sampling clock at the top of Figure 3
A new level information sample _LD0 is obtained from the A/D converter 1 by one pulse of SCL, and at the same time, a gate switching signal is generated from the timing generation circuit 3.
Go rises to "H", and the address A of the RAM 4 becomes LD ₀ (=2) by the address switching circuit 5.
Therefore, the address LD ₀ (=2) in the RAM 4 is accessed, and the contents D (1) are added by +1 by the increment circuit 7 and changed to (2). “H” in this Go
The level time length T _G may be the minimum length necessary to execute a set of operations of reading data from one address of the RAM 4 and adding +1 and storing it. Next, instead of Go, the gate switching signal Gn becomes “H” for the same time length T _G.
level, RAM4 address LDn (=6)
is accessed, and its contents D (4) are subtracted by -1 by the decrement circuit 8 and changed to (3). The above shows the contents explained in FIG. 2 on the time axis. When the above operation, that is, creation of a new frequency distribution, is completed, the gate switching signal Gs rises to "H", and the address of the RAM 4 is scanned from 0 to 10 by the address scanning output AS of the address scanning circuit 6. Each of these address specifications is performed in synchronization with the address scanning clock ACL, and since the address information corresponds to the level information,
Each frequency corresponding to level 0 to level 10 is sequentially read out from the data D of RAM4 to the integration circuit,
Accumulated at ACL timing. Therefore, the integrated output SUM becomes a cumulative frequency distribution pattern developed on the time axis as shown in the figure. Here, the period T _A of the ACL may be the minimum length required to execute a set of operations of reading data from one address of the RAM 4 and integrating the data. Now, the median of the frequency distribution for the number of samples n (n is an odd number) is the cumulative distribution of (n
+1)/2, the other constant input M of the comparator 10 is set as M=(n+1)/
If 2=6 is set, A (or
AS) (5 in the example in Figure 3) is the median value.
Register 11 stores this at the rising point of DET as shown in Figure 3, and its output ASm value is updated from the previous median value (6 in the example in Figure 2) to the new median value (5 above). be done. This is register 12
When the next sampling clock SCL pulse arrives, it is outputted to the outside as the median detection output LDm.

Next, we will address the various performance issues that arise when the device according to the present invention described above is put to practical use in detecting the median received field strength in general land mobile communications, such as the dynamic range of level information, sampling period, number of samples, etc. Examine from the standpoint of gender and suitability.

It is generally accepted that fading in land mobile radio communications is so-called Rayleaf aging in which the envelope level distribution of the received signal follows the Rayleigh distribution law. First, the dynamic range of the envelope level (maximum change range of level)
For, logarithmically compressed value (decibel, dB)
When handled with 1 μV, it is approximately -30 to +80 dBμV (dBμV is 20 times the logarithm value with 1 μV as the standard), or 110 dB, although it depends on the performance of the receiver. Assuming that the measurement accuracy is within ±1 dB and the measurement is performed in 1 dB increments, the number of level divisions of level information will be approximately 110. This is within the range of 0 to 255 that can be expressed as a binary number of 1 byte = 8 bits, and can be realized by using an 8-bit A/D converter.

Next, the sample period required for statistical estimation of the median value
Regarding Ts (seconds), according to the above-mentioned document 3, the maximum Doppler frequency _D (Hz) of Rayleaf aging
It is known that if 1/T _s 2.61 _D ...(1) is satisfied, a median value with an effective standard deviation can be obtained. (1/T _s = s = sampling frequency).

Regarding the number of samples n, it is clear that the standard deviation of the median value decreases as n increases. According to the above-mentioned document 4, the number n of samples required to obtain a standard deviation of 1 dB is expressed by the following formula. Become.

n39...(2) In general, the maximum Doppler frequency _D of fading is the radio frequency (Hz) and the speed of the moving object v (m/m/
sec), and the speed of light c = 3 x 10 ⁸ (m/sec), then _D = v/c...(3), which is 800MHz used for land mobile radio.
In the zone, assuming v=100Km/h, from equation (3), _D 74 (Hz) ...(4) Substituting the condition of (4) into (1), Ts5×10 ^-3 (seconds) ...(5) . Therefore, the timing length T=nTs required to obtain one median value is T=n· _Ts ≈0.195 (seconds) (6) from (2) and (5). From the above numerical examples, the time length required for each operation shown in FIG. 3 is as follows.

Go, Gn H level time length T _G is memory RAM
Assuming that the time required to read and store 4 is twice the time T _A based on memory read, then from Figure 3, T _s 2T _G + (number of level divisions)・T _A = (4 + 110)・T _A 114T _A ...(7) Therefore, from both equations (5) and (7), T _A T _s /1145×10 ^-3 /11444 (μs) ...(8). Considering that the read and store speeds of general RAM are several μs or less, this T _A is a sufficiently achievable speed.

Furthermore, since the number of stages of the shift register 2 shown in FIG. 1 is made equal to the number of samples n, it is sufficient that it is 39 or more according to equation (2) and can be easily realized.

Furthermore, given the above calculation speed and storage capacity, it is also possible to replace all of the functional configuration of FIG. 1 except for the A/D converter 1 with software functions by a microcomputer, and in this case, provides versatility in that parameters such as the number of samples can be set arbitrarily.

(Effects of the Invention) Each time the received electric field is sampled, the median value detection device of the present invention accurately calculates the frequency distribution and cumulative frequency distribution of the received level, which is a total of a predetermined number of samples in the past, and Since the value is calculated and output, it is possible to eliminate the delay effect due to the integration time constant in the median value detection operation in the conventional method using the negative feedback type value tracking circuit, that is, the interference effect between a plurality of samples. Also, since it is possible to give a sample with the median value as defined from samples with any number of level values within the range required for the application,
The compatibility is high in terms of the correspondence evaluation between the theoretical values and the measured values.

Furthermore, many parts of the circuit configuration can be converted into software, which has the advantage of being suitable for downsizing, high reliability, and cost reduction of devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a device implementing the present invention, FIG. 2 is a diagram showing an example of the storage contents of the RAM in FIG. 1, and FIG. 3 is a diagram showing an example of the storage contents of the RAM in FIG. This is a time chart of an operation example of the median value detection used. 1...A/D converter, 2...Shift register,
3...timing generation circuit, 4...RAM (random access memory), 5...address switching circuit,
6... Address scanning circuit, 7... Increment circuit, 8... Decrement circuit, 9... Integration circuit, 10... Comparator, 11, 12... Register,
L...Analog level information, LDo, LDn...Digital level information, SCL...Sampling clock, A...RAM address, D...RAM data content, Go, Gn, _Gs ...Gate switching signal,
ACL...address scan clock, AS...address scan output, SUM...accumulation output, M...cumulative degree value that gives the median value, DET...comparator output,
ASm...Memory retention output, LDm...Median detection output.

Claims (1)

[Claims] 1. An A/D converter that samples the envelope of the received wave or its logarithmically compressed value using a sampling clock with a constant sampling period, converts it into digital numerical level information, and outputs the level information for n samples. (n is the number of samples required depending on the standard deviation of the desired median value) A shift register for storing, a random access memory (RAM) for storing the frequency distribution of the level information, and various timings synchronized with the sampling clock. A timing generation circuit that generates pulses, an address switching circuit that switches addresses in RAM, and an address scanning circuit that scans all addresses in RAM.
A RAM corresponding to level information from the A/D converter for each pulse of the sampling clock.
an increment circuit that specifies the address of 1 through the address switching circuit and increases the level information, that is, the frequency of the new level by one, and then switches the address corresponding to the level information n samples before by the shift register output. a decrement circuit which specifies the level information through the circuit and reduces by one the frequency of the old level to be discarded; and both the increment and decrement circuits.
After constantly updating the frequency distribution of the level information stored in the RAM in accordance with the latest n samples, the address scanning circuit hits the entire level information range.
An integration circuit that scans and specifies all the addresses in RAM and integrates the content when reading out the contents one after another, and an accumulation circuit that calculates the median value whose cumulative frequency distribution is determined by the number of samples n. A comparator that detects the first point in time that is equal to or greater than the frequency, a storage circuit such as a register that stores the address value, that is, the level information value, at the point of detection of the output, and a storage circuit such as a register that stores the stored contents at the next sampling clock pulse. 1. An apparatus for detecting a median value of a received electric field, comprising: a circuit for holding and outputting a median value detection output in synchronization with the received electric field.