JPH0113655B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic circuit for removing chattering of a contact switch from a switch signal passed through the contact switch. Since the signal from the contact switch includes chattering, it is necessary to remove this chattering portion from the signal in order to incorporate it into various devices. A conventional circuit for this purpose is shown in FIG. This circuit is
It consists of a counter 11 and a flip-flop 12 whose output is input. When an input signal IN containing chattering arrives, the counter 11 counts the clocks, and after the time period during which chattering generally occurs at the head of the signal has elapsed, The flip-flop 12 is configured to be inverted. Furthermore, if there is a short break in the input signal at the tail end of the input signal, the output is immediately cut off. According to this circuit, when there is chattering at the beginning or end of the input signal, it can be effectively removed from the signal, but if there is chattering during the middle duration of the input signal, the output
There is a drawback that OUT is interrupted. That is, as shown in the waveform diagram in Fig. 2,
The head chatter Ch ₁ and tail chatter Ch ₃ of the input signal IN do not appear on the output OUT, but the mid-chattering Ch ₂ does not appear on the output OUT.
It appears as a break in OUT. Generally, when the contact switch is a manually operated button, intermediate chattering Ch ₂ may occur, and in this case, this conventional circuit will misidentify it as two signals. The present invention improves on this, and aims to provide a circuit that can eliminate chattering even when it occurs during the intermediate duration of an input signal. The present invention has two flip-flops, the first flip-flop removes the leading and trailing chatter of the input signal, and the second flip-flop holds the output for a certain period of time after the input signal stops. The device is characterized in that it is configured so that even if the input signal is interrupted for a certain period of time or less while the input signal is being operated, this does not affect the output. This will be explained in detail with reference to the drawings. FIG. 3 is a circuit diagram of an embodiment of the present invention. An input signal IN is connected to the data input of the flip-flop 21, and a clock signal CL is connected to the clock input thereof. The input signal IN is connected to one input of the gate circuit 22. The output of this gate circuit 22 and the flip-flop 21
The output of gate circuit 23 is led to the input of gate circuit 23, the output of which is connected to the data input of flip-flop 24. Further, the clock signal CL is applied to the clock input of the flip-flop 24, and the output of the flip-flop 24 is provided to the clock input of the flip-flop 24.
2 and one input of the gate circuit 25. The input signal IN is applied to the other input of this gate circuit 25, and its output is connected to the reset input of the flip-flop 21. The operation of this circuit will be explained using the operational waveform diagram shown in FIG. In Figure 4, IN is an input signal with chatter via a contact switch, CL is a clock signal, Q is the output of flip-flop 21,
OUT is the output of this circuit. When a chattering input signal IN is applied, the flip-flop 21 is inverted at the first fall of the clock signal CL after the chattering ceases. As a result, at the next fall of the clock signal CL, the flip-flop 24 is inverted and output.
OUT rises. If chattering Ch ₂ occurs in the input signal IN on the way, flip-flop 2
1 is immediately inverted, its output Q is interrupted, and it is inverted again at the next fall of the clock signal CL. However, since the output OUT of the flip-flop 24 is fed back through the gate circuits 22 and 23, even if the output Q of the flip-flop 21 is interrupted, it will not be inverted until the next fall of the clock signal CL. Therefore, if the disconnection time due to chattering Ch ² is less than one period of the clock signal CL, this effect will not appear on the output OUT. Chattering Ch ₃ occurs at the tail end of the input signal, and when the time for which this occurs has elapsed and the time corresponding to one cycle of the clock signal has elapsed, the flip-flop 24 is restored. The period of the clock signal CL depends on the situation where chattering occurs in the input signal, its duration, and the output
It is best to determine it appropriately depending on the response situation of the circuit where OUT is used. Truth tables for gate circuit 22 or 23, 25 and flip-flop 21 are shown in Tables 1 to 3. In Table 3, the "top" of the clock input CL represents a rising edge, and the "bottom" thereof represents a falling edge. As described above, according to the present invention, an excellent circuit can be obtained that can eliminate not only the head and tail chattering included in the input signal but also the chattering that occurs in the middle of the input signal. By implementing the present invention, one output signal can be reliably obtained by one contact operation, and there is an excellent effect that malfunctions are significantly reduced.

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【table】 [Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional example. FIG. 2 is an operating waveform diagram of a conventional circuit. FIG. 3 is a circuit diagram of an embodiment of the present invention. FIG. 4 is an operational waveform diagram of the circuit according to the embodiment of the present invention.

Claims (1)

[Claims] 1. A first flip-flop 21 which takes an input signal as a data input and a clock signal given from the outside as a clock input, an AND gate circuit 22 which takes the above input signal as one input, and an output of this AND gate circuit and the above flip-flop. A first OR gate circuit 23 whose input is the output of
The output of the OR gate circuit is used as data input, the above clock signal is used as clock input, and the output is used as above.
A second flip-flop 24 serves as the other input of the AND gate circuit 22, and a second flip-flop receives the output of the second flip-flop and the above input signal and supplies its output to the reset input of the first flip-flop. 1. A chattering removal circuit comprising an OR gate circuit 25, and using the output of the second flip-flop as a signal from which chattering has been removed.