JPH0113794B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic exchanger having a functionally distributed configuration.

Conventionally, when configuring the control system of an electronic exchange, it is often configured using a single processor, and the connection processing for both basic and high-end services is performed by the same processor. The drawback was that it was impossible to perform both basic and high-end services.

The present invention aims to eliminate the above-mentioned conventional drawbacks, and the present invention will be explained below by way of an embodiment with reference to the drawings. In FIG. 1, 1 is a switch, 2 is an interprocessor communication bus,
3 is a switch control processor, 4 is an upper connection processor, 10 is a subscriber system lower connection processor, 11 is a telephone, 12 is a subscriber circuit, 13 is a call state memory access inhibit flag, 14
is a subscriber call state memory; 15 is a timer circuit; 20
21 is a line, 22 is a trunk circuit, 23 is a call state memory access inhibit flag, 24 is a trunk call state memory, 25 is a timer circuit, and 30 is a lower connection for the operator system. The processor 31 is a handling console.

Switch 1 via processor communication bus 2,
A communication bus between the subscriber circuit 12, the trunk circuit 22, and the console 31 is formed. Further, the processor 3 that controls the switch 1 controls the switch 1 through the inter-processor communication bus 2 in response to commands from the lower-level connected processors 10, 20, 30 or the higher-level connected processor 4. Call status information (data) for individual subscribers, trunks, and consoles 31 is held in call status memory 14 for subscribers, call status memory 24 for trunks, and call status memory 34 for consoles, respectively. There is. On the other hand, access inhibit flags 13, 23, and 33 are provided in one-to-one correspondence to each call state memory.

Next, the operation of this embodiment will be explained.

Here, services (tasks) that occur frequently but require relatively simple processing are defined as basic services.
Furthermore, if we call a service (work) that requires complex processing, although it is infrequent, a high-level service, then in a basic service, the lower-level connection processor 10,
20 and 30 perform processing while referring to and updating their own call state memory according to the occurring event. In this state, access inhibit flags 13, 23, and 3 corresponding to call state memories 10, 20, and 30 are set.
3 can be accessed by the lower processors 10, 20, and 30 (see FIG. 2).

However, when the lower-level connected processors 10, 20, and 30 detect the need for high-level services, they request the higher-level processor 4 for the service through the interprocessor communication bus 2. When a service is requested to the upper processor, the lower processors 10, 20, 30 disable access to the access inhibit flags 13, 23, 33 of the related call state memories 14, 24, 34, and at the same time set the timer circuit 1 to monitor for a certain period of time.
Start from 5, 25, 35. After a certain period of time has elapsed, the timer circuits 15, 25, and 35 detect a timeout, and if the access is disabled, the access is returned to the enabled state.

On the other hand, while the lower processors 10, 20, and 30 are not accessible due to the access inhibit flags 13, 23, and 33, the lower processors 10, 20, and 30 write 1 to the corresponding call state memory.
Access to 4, 24, and 34 is prohibited. The upper-layer connected processor 4 requested for service reads the call state memory 14, 24, 34 in the lower-layer connected processors 10, 20, 30 via the inter-processor communication bus 2, if necessary, and 20, 30 and the switch control processor 3 to write the updated contents into the call state memory 14, 24, 34. Upper connection processor 4 uses call state memory 14, 24, 3
The access inhibit flags 13, 23, and 33 are prohibited from being accessed by the lower-level connected processors 10, 20, and 30 from when 4 is read until the writing is completed. Further, time monitoring is performed by the timer circuit 15 from the time when access is prohibited, and if writing is not performed from the upper-level connected processor 4, the access prohibition is canceled when the timer circuits 15, 25, and 35 time out.

According to the above configuration, the following effects can be obtained.

It becomes possible to separate basic connections to lower-level connected processors, making it more resistant to failures and improving the reliability of basic functions.

Portions that require data memory and other process processing time can be distributed to lower processors in proportion to the scale of the system, such as the number of subscriber circuits and the number of trunk circuits. It can be easily expanded by increasing the number of units.

Note that it is also possible to easily enhance the functionality by adding an optional trunk system or the like to the above configuration. Furthermore, in the above configuration, it is also possible to provide a plurality of higher-level processors or to have a multiple hierarchical configuration.

As explained above, according to the present invention, basic services are processed by a lower processor, and when a high-class service is required, access to the lower processor is prohibited for a certain period of time, and the upper processor performs the high-class service. Therefore, even if the upper processor goes down, the memory of the lower processor can be accessed for a certain period of time, allowing basic services to continue, and functional distribution improves reliability and increases flexibility for expansion. has advantages.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a functionally distributed electronic exchange according to an embodiment of the present invention, and FIG. 2 is a diagram showing the structure of a call state memory for explaining its operation. 2...Inter-processor communication bus, 3...Switch control processor, 4...Upper connection processor,
10...Lower connection processor for subscriber system, 11
. . . Telephone, 12 . . . Subscriber circuit, 13 . . . Access inhibit flag for call state memory, 1
4... Call status memory for subscriber, 15... Timer circuit, 20... Lower connection processor for trunk system, 21... Office line, 22... Trunk circuit, 23
...lower connection processor for call state memory, 24
. . . Call status memory for trans, 25 . . . Timer circuit, 30 . . . Lower connection processor for operator system, 3
1... Console, 33... Access inhibit flag for call state memory, 34... Call state memory for console, 35... Timer circuit.

Claims (1)

[Claims] 1. A plurality of lower-level connection processors, each of which is provided with a call state memory for holding a call connection state in response to a plurality of call connection requests, a common bus line connecting the lower-level connection processors, and each of the lower-level connection processors. An upper connection processor that rewrites or controls the contents of the call state memory with the connection processor, and a processor provided for each of the lower connection processors and for controlling access from each of the lower connection processors. A flag circuit and a timer circuit provided for each of the lower-level connected processors and controlling the access prohibition time are provided, and the work that can be processed by each of the lower-level connected processors is processed by the lower-level connected processor alone,
A function-distributed electronic switching system in which work requiring the involvement of a higher-level processor is processed under the control of the higher-level processor by prohibiting access from the lower-level processor for a certain period of time set by the timer.