JPH0115141B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring the minority carrier trap level at the interface of a MOS type diode.

The phenomenon in which carriers in MOS diodes, Schottky junction diodes, PN junction diodes, etc. are captured by voltage application and gradually return to their original state due to thermal release after the voltage is cut off indicates changes in the depletion layer. Changes in the depletion layer are measured as transient phenomena in high-frequency capacitance. The parameters related to the thermal release of the carrier are determined by spectroscopically extracting the transient response at each temperature as a difference signal between two sets of weighted signals as a function of temperature, and calculating various physical quantities of the semiconductor by calculating the obtained signals. Ru. This method uses DLTS (Deep Level Transient
Spectroscopy) is becoming standardized as a method.

The DLTS method is excellent in that it can measure not only deep levels of semiconductors but also interface levels with high sensitivity and in a non-destructive manner. Moreover, with this method,
It has many advantages, such as being able to measure two or more trap levels separately, and also being able to discriminate between a minority carrier trap level or a majority carrier trap level by applying bias voltages in order or inversely.

However, with conventional methods, both the minority carrier trap level and the majority carrier trap level can be measured by using capacitance changes of PN junction or Schottky junction diodes.
A diode with a MOS structure had the disadvantage that only the majority carrier trap level could be measured.

In recent years, due to the demand for high-density LSI, crystal defects in the substrate itself and defects generated by high-density processing have a profound effect on deep levels and interface levels, and are one of the causes of defective or deteriorating semiconductor characteristics. I'm getting used to it. In particular, measuring this type of level in compound semiconductors is important for research and development, quality improvement, and yield improvement. Therefore, measurement of not only the majority carrier trap level but also the minority carrier trap level is becoming important. For example, the characteristics of a transistor are determined by the behavior of minority carriers relative to majority carriers.

The purpose of the present invention is to easily and efficiently measure the minority carrier trap level of a MOS diode.
The object of the present invention is to provide a method for measuring the minority carrier trap level at the interface of a MOS type diode.

The method for measuring the minority carrier trap level at the interface of a MOS diode according to the present invention involves applying a light pulse having an energy greater than the forbidden band width to the MOS diode while the temperature of the MOS diode to be measured is being varied. A wave is applied at each temperature at the same time as a bias pulse voltage, and the energy level of the minority carrier is increased by the energy of the optical pulse wave to invert the surface level, and the heat of the minority carrier is increased after the application of the optical pulse wave is stopped. The change in the depletion layer based on target emission is determined for each temperature as a transient change in high-frequency capacitance, and the obtained high-frequency capacitance transient change signal for each temperature is multiplied by a weighting signal to obtain a deep impurity level signal. It is characterized by measuring the minority carrier trap level at the interface of a MOS diode.

Hereinafter, specific examples of the present invention will be described in detail with reference to the drawings. Figure 1 shows an MOS that implements the method of the present invention.
This figure shows a specific example of a device for measuring the minority carrier trap level at the interface of a type diode. In the figure, 1 is a laser beam generator, 2 is a chopper mechanism that cuts off the laser beam to form an optical pulse wave,
3 is an optical pulse wave generation section consisting of a laser beam generator 1 and a chopper mechanism 2; 4 is an optical pulse wave generation section 3;
A part of the optical pulse wave emitted from the is transmitted, and a part is
A semi-transparent reflector for reflecting in a 90 degree direction, 5 a cryostat for temperature sweeping, and 6 a MOS type diode for measurement that is disposed inside the cryostat 5 and is irradiated with an optical pulse wave through the semi-transparent reflector 4. , 7 is a signal control/processing device including a central processing unit (CPU),
8 photoelectrically converts the optical pulse wave reflected by the semi-transparent reflector 4 to create a synchronization signal, which is used for signal control and
This is a photodetector that feeds the processing device 7. 9 is a heater for controlling the temperature inside the cryostat 5 under the control of the signal control/processing device 7; 10 is a heating feeder connecting the signal control/processing device 7 and the heater 9; and 11 is a heater for controlling the temperature inside the cryostat 5. Temperature sensor for detection, 12 is temperature sensor 1
This is a temperature signal line that transmits a temperature signal from 1 to the signal control/processing device 7. 13 is a high frequency capacitance meter that measures the high frequency capacitance of the measurement MOS type diode 6; 14 is a signal control device for the output of the high frequency capacitance meter 13;
A capacitance output line 15 for feeding to the processing device 7 is for measuring the bias pulse voltage from the signal control/processing device 7 via the high frequency capacitance meter 13 in accordance with the synchronization signal.
This is a bias pulse supply line given to the MOS type diode 6. 16 is a recorder such as an X-Y recorder or an X-Y plotter for recording the output signal output from the signal control/processing device 7; 17 is an external host computer connection bus provided in the signal control/processing device 7; be.

Next, a specific example of a method for measuring the minority carrier trap level at the interface of a MOS type diode using such an apparatus will be explained with reference to FIG. 1 and FIGS. 2A to 2D. The signal control/processing device 7 sets the temperature sweep time, controls the heater 9 in the cryostat 5 through the heating feeder 10, varies the temperature in the cryostat 5, and detects the temperature of the core by a temperature sensor 11. Detected by temperature signal line 1
2 to the signal control/processing device 7 and stored in this device 7. With the temperature of the MOS type diode 6 being varied in this way, the optical pulse wave generator 3 outputs an optical pulse wave at each temperature as shown in FIG. Through
The gate electrode side of the MOS type diode 6 is irradiated.
This optical pulse wave is set in advance so that, when irradiated onto the MOS diode 6, it has energy greater than the width of the forbidden band within the MOS diode 6. A part of the optical pulse wave emitted from the optical pulse wave generator 3 is reflected by the semi-transparent reflection plate 4 and enters the photodetector 8, where a synchronization signal is generated and sent to the signal control/processing device 7. Given. When a synchronization signal is given, this signal control/processing device 7 outputs a bias pulse voltage as shown in FIG. Then, it is applied between both electrodes of the MOS type diode 6. The energy of the optical pulse wave increases the energy level of the minority carriers in the MOS diode 6, and the surface level is inverted. The rising portion indicated by 18 in FIG. 2C shows a state in which the carrier is trapped. When the irradiation of the optical pulse wave is stopped, the minority carriers are thermally released in the MOS diode 6 as shown in 19 in Fig. 2C.
This occurs as shown in the section. Changes in the depletion layer based on thermal release of minority carriers in the MOS diode 6 are measured as transient changes in the high-frequency capacitance at each temperature using the high-frequency capacitance meter 13, and are sent to the signal control/processing device 7 via the capacitance output line 14. give. In the signal control/processing device 7, the high frequency capacitance transient change signal for each temperature given from the high frequency capacitance meter 13 is multiplied by a weighted signal consisting of two sets of rectangular waves as shown in FIG. 2D. In this case, the weighting signal has a peak value of zero during the time width Td from the stop of application of the optical pulse wave to the rise of the first weighting signal, and the peak value is zero when the first weighting signal and the second weighting signal are applied. The peak values of the first and second weighting signals within the time width Tw are +1 and -1. Through these processes, a DLTS signal V ₀ as expressed by the following equation is obtained.

V ₀ /ΔC=-1/Tw/τ・exp(-Td/τ) {1-exp
(−Tw/2τ)} ² …(1) Also, τ=1/e _o =1/ν _o σ _o N _C・expE _C −E _T /kT …(2) Here, ΔC is C in Figure 2 The amount of transient capacitance change shown in
Tw and Td are the time widths of each part of the weighted signal shown in Figure 2D, τ is the time constant of the transient capacitance characteristic, e _o is the electron emission rate, σ _o is the electron capture cross section, and N _C is the conduction band Effective level density, E _C is the conduction band level, E _T is the desired impurity level, ν _o is the average thermal velocity of electrons, T is the absolute temperature of the sample, and k is the Boltzmann constant.

Furthermore, by multiplying by ν _o →ν _p , σ _o →σ _p , N _C →N _V , E _C →E _V , the level of holes relative to the valence band can also be measured. Here, ν _p is the average thermal velocity of the hole, and σ _p
is the trapping cross section of the hole, N _V is the effective level density of the filled band, and E _V is the level of the filled band.

From the above two equations, ν _o , N _C , E _{C ,} etc. are constant depending on the semiconductor, so the linear relationship (Areus plot) obtained by setting l _o τ on the vertical axis and 1000/T on the horizontal axis ) to obtain σ _o and E _C.

Figure 3 shows the minority carriers measured when the MOS diode 6 is irradiated with light (a minority carrier DLTS signal is obtained) and when it is measured without light irradiation (a majority carrier DLTS signal is obtained).
DLTS signal 20 and multiple carrier DLTS signal 21
This is an example of finding the following. From these signals, the interface state density N _SS can be obtained using the following formula.

N _SS =±εC _OX N _S V _O /C _O ³ kT/[Td/T _W・l _o {Td/T _W (T
d/T _W+1 )/(Td/T _W+1/2 ) ² } +l _o (Td/T _W+1 /Td/T _W+1/2 )]...(3) Here, ε is The dielectric constant of Si, N _S is the dopant concentration, C _O is the capacitance per unit area in steady state,
C _OX is the capacitance of the oxide film per unit area, k is the Boltzmann constant, T is the absolute temperature, V _O is the DLTS signal, Td,
T _W is the time width of the weighting signal. As shown in Figure 2D, when measuring the minority carrier trap level, the MOS capacitance shows a decreasing transient response, so
As in the case of a PN junction, the DLTS signal is positive. On the other hand, in the measurement of the majority carrier trap level, a transient response occurs in which the capacitance increases, so the DLTS signal becomes negative. The positive and negative signs in equation (3) correspond to the measurement of the minority carrier trap level and majority carrier trap level, respectively.

_FIG . 4 shows the result calculated by the signal control/processing device 7 by substituting the values of the multiple carrier trap DLTS signal 20 and the multiple carrier trap signal 21 in FIG. 22 shows the minority carrier interface state density vs. temperature characteristic, and 23 shows the results drawn with the recorder 16.
shows the majority carrier interface state versus temperature characteristics. According to this example, it can be seen that the value of the majority carrier interface state density is about one order of magnitude smaller at around room temperature than the value of the minority carrier interface state.

As described above, it becomes possible to calculate the energy distribution over the entire forbidden band of the interface state density. Fifth
The figure shows an example of this interface state density distribution characteristic. Here, _EV is the valence band level. Thereby, the interface level density distribution of electrons and holes can be easily and accurately drawn.

As the weighting signals, it is of course possible to use not only two sets of rectangular wave signals, but also two sets of pulse signals, two sets of exponential function signals, or the like.

As explained above, according to the present invention, energy is given to a MOS type diode by an optical pulse wave,
Since the energy level of the minority carriers is increased to invert the surface level, the minority carrier trap level at the interface of the diode can be easily and accurately measured. Therefore, by combining it with the conventional method of using pulsed voltage,
Interface states across the entire forbidden band can be measured. In particular, the method of the present invention is superior to the admittance method in terms of detection sensitivity and in that measurements are not affected by variations in interfacial potential.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of an apparatus for implementing the measurement method according to the present invention, Fig. 2 A to D are waveform diagrams of various parts explaining the method of the present invention, and Fig. 3 is a DLTS
FIG. 4 is a signal versus temperature characteristic diagram, FIG. 4 is a minority carrier interface state density versus temperature characteristic diagram, and FIG. 5 is an energy distribution diagram of the interface state density. 3... Optical pulse wave generator, 4... Semi-transparent reflector, 5...
Cryostat for temperature sweep, 6...MOS type diode, 7...signal control/processing device, 8...photodetector, 13...high frequency capacitance meter.

Claims (1)

[Claims] 1. While the temperature of the MOS diode to be measured is being varied, an optical pulse wave having an energy greater than the bandgap width is applied to the MOS diode at each temperature simultaneously with a bias pulse voltage to generate the optical pulse. The energy level of the minority carriers is increased by the energy of the wave to invert the surface level, and the change in the depletion layer based on the thermal release of the minority carriers after the application of the optical pulse wave is stopped is expressed as a transient change in the high-frequency capacitance at each temperature. The high-frequency capacitance transient change signal obtained for each temperature is multiplied by a weighting signal to obtain a deep impurity level signal.
A method for measuring the minority carrier trap level at the interface of a MOS diode.