JPH0622259B2 - Interfacial electrical conductivity evaluation method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a deep impurity semiconductor near the interface of a heterojunction in a semiconductor device or the interface between an insulating film and a semiconductor, which adversely affects electrical conduction. The present invention relates to an interfacial electric conduction evaluation method suitable for detecting a level (defect level).

Conventional technology and problems Conventionally, for example, an interface effect semiconductor device has been known as a semiconductor device utilizing a current flowing at the interface of a heterojunction or a current flowing at the interface between an insulating film and a semiconductor.

In such a semiconductor device, the quality of the interfacial electrical conduction greatly affects the characteristics, and the interfacial electrical conduction is related to the interface or a deep impurity level near the interface.

Therefore, it is necessary to obtain the correlation between the interface electric conduction and the interface or a deep impurity level near the interface, in order to obtain a semiconductor device having good characteristics, but there has been no method so far.

An object of the present invention is to make it possible to directly determine the correlation between the interface electric conduction and the deep impurity level at the interface or in the vicinity of the interface by using an actual field effect semiconductor device.

According to the present invention, as described above, the presence or absence of a deep impurity level (defect level) and its position can be detected by measuring the drain-source current flowing at the interface of the heterojunction. .

Generally, the drain-source current I is expressed by the following equation. That is, I = q · n · μ · E (1) q: Elementary charge (constant) n: Interface electron concentration μ: Electron mobility E: Electric field (S.M.S. By "Physics"
of Semiconductor Device
s 1969 John Wiley and So
ns, Inc.).

In the present invention, it is possible to measure Δn and Δμ, which are changes of n and μ derived by expanding the formula (1),
From the measurement result, it is possible to know the defect level, that is, whether the trap exists at the interface, in the film, or both.

The principle of the present invention will be described with reference to FIGS.

FIG. 1 is a band model diagram of a field effect semiconductor device utilizing a current flowing at the interface of a heterojunction.

In the figure, MG is a metal gate electrode, 1 is GaAlAs
N ⁺ type semiconductor layer as a layer, 2 as a semiconductor layer as a GaAs layer, FL as a Fermi level, SL as an interface level, and SE as an interface charge.

The figure (a) shows the case of a steady state where a normal bias voltage is applied, and the interface state SL is not filled with electrons.

FIG. 6B shows a case where a pulse bias is applied to the metal gate electrode MG in addition to the normal bias voltage so that the charge state of the interface becomes more in the accumulation (inversion) mode. SL is filled with electrons.

FIG. 7C shows the case where the state in which the pulse bias is applied is returned to the normal bias voltage application state described with reference to FIG. 7A. In this state, the state described with reference to FIG. The charges accumulated in the interface state SL will be released.

Due to this charge discharge, the amount of accumulated (inverted) charge existing at the interface changes, and therefore the current between the drain and the source also changes.

As previously shown as the equation (1), the drain-source current I is expressed by I = q · n · μ · E, and in the present invention, the variations Δn and μ of n derived from this formula are expressed. Of the drain-source current I is defined as ΔI, I + ΔI = q (n + Δn) (μ + Δμ) E (2) Formula (1) Substituting into the left side of (2), qnμE + ΔI = qnμE + q (n + Δn) (μ + Δμ) E, and ΔI = q (Δn · μ + Δμ · n + Δn · Δμ) E, and further Δn / n << 1, Δμ / μ << 1 If, then ΔI = q (Δn · μ + Δμ · n) E.

To obtain the change ΔI of the current I, as described above, after applying the pulse bias, sampling is performed at predetermined times t1 and t2, and the difference between the currents between the times t1 and t2 is measured by the temperature change. It is obtained as a function of.

Thus, in order to obtain the function as a function of temperature, the field effect semiconductor device as the sample is placed in a container that can be heated by a heater, and the temperature of the field effect semiconductor device is changed while being detected by, for example, a thermocouple, It is necessary to feed a temperature-related signal, for example, to one input of the XY recorder.

FIG. 2 illustrates the case where the above-described operation is performed. FIG. 2A shows the gate bias voltage, and FIG.
FIG. 4 is a diagram showing a drain-source current.

In FIG, _{V R} is the gate bias value, _{V F} is the pulse bias value, t is time, PB1 and PB2 are pulse
Bias, t1 and t2 indicate sampling times, respectively. As can be seen from the figure, the pulse bias PB1 or PB2 is applied, and the drain / source currents after the pulse bias PB1 or PB2 fall are changed as shown if there is a defect level. If there is no defect level, the drain / source current does not change and is flat. Needless to say, the temperature scanning is performed between the sampling times t1 and t2.

Embodiment of the Invention FIG. 3 is a block diagram showing an example of an apparatus for carrying out the present invention.

In the figure, 11 is a bias voltage generator, 12 is a pulse bias voltage generator, 13 is an amplifier, 14 is a boxcar averager, 15 is an XY recorder, TT is a thermocouple, and Q is a sample transistor. , S is a source, D is a drain, G is a gate, and R is a resistance.

In this embodiment, a constant voltage is applied between the source S and the drain D, and a voltage is applied to the gate G so that the interface is in the inversion or accumulation mode, that is, the pulse / bias voltage generator 1
Apply pulse bias from 2. After the pulse bias falls, the transient response of the current between the drain D and the source S is sampled by the boxcar averager 14, and the difference is obtained from the currents at the times t1 and t2. The current difference between times t1 and t2 is recorded as a function of temperature on the XY recorder 15 while changing the temperature of the transistor Q, which is a sample.

FIG. 4 is a diagram showing data obtained by evaluating the correlation between the interfacial electric conduction and the defect level according to the embodiment.

In the figure, the temperature T is plotted on the horizontal axis and i (t1) -i (t
The spectrum obtained by changing the position of the gate for sampling the signal of 2), that is, t1 / t2 is shown. Note that PB indicates the condition of the pulse bias used when obtaining this data.

From the gate position dependence of the peak current shown in this data, the defect causing the peak current is 0.36 from the conduction band.
It was found to be in the energy position of [eV].

Further, if such data is obtained, it is possible to easily determine where the defect level exists, and it is possible to greatly contribute to the improvement of the characteristics of the semiconductor device. That is, when the defect level (interface trap) exists only at the interface,
As shown in FIG. 4, the peak appears on the positive side in the data when the current value between the source and the drain is measured as a function of temperature, but the defect level (in the film) 4), the peak appears on the negative side as seen in FIG. 4, and when the interface trap and the trap in the film are mixed, the peak appears on the positive side and the negative side. Since it appears in both, the judgment is extremely easy.

By the way, in order to shift the charge state of the deep impurity level, that is, the defect level from the steady state, light can be irradiated to fill the electrons in addition to the method of applying the pulse bias to the gate of the transistor. It is desirable to use monochromatic light such as laser light as the irradiation light at that time.

FIG. 5 is a block diagram showing an example of an apparatus for carrying out the method of irradiating light, and the same parts as those described with reference to FIG. 3 are designated by the same symbols.

This device is different from the device shown in FIG. 3 in that it is provided with a laser light generator 16, an optical chopper 17, a half mirror 18, a photo cell 19, and a bias voltage generator 20.

In this device, a bias voltage generator 20 applies a constant bias voltage to the gate of the transistor Q, the light from the laser light generator 16 is pulsed by an optical chopper 17, and this is passed through a half mirror 18. Transistor Q
To irradiate. Further, a part of the light reflected by the half mirror 18 is photoelectrically converted in the photo cell 19, and the pulse obtained thereby is converted into the boxcar averager 1.
4 is used as a trigger signal. After the light pulse is incident on the transistor Q, the operation of the device shown in FIG. 3 is almost the same. That is, the transient response of the drain-source current is measured and recorded after the irradiation of the light pulse is completed.

EFFECTS OF THE INVENTION According to the present invention, the correlation between the interface electric conduction and the deep impurity level at the interface or in the vicinity of the interface can be detected spectrally and spectroscopically using an actual field effect semiconductor device. It is possible to easily obtain the basic data for obtaining the interface. Further, since it is possible to easily determine whether the defect level exists only at the interface, only in the film, or both, it is possible to accurately identify the points to be improved in the semiconductor device. Therefore, it has a great contribution to the improvement of the characteristics.

[Brief description of drawings]

1 and 2 are band model diagrams for explaining the principle of the present invention and diagrams showing gate-bias voltage and drain-source current, and FIG. 3 is an example of an apparatus for carrying out the present invention. FIG. 4 is a block diagram for explaining, FIG. 4 is a diagram showing the data obtained by the apparatus of FIG. 3, and FIG. 5 is a block diagram showing another example of the apparatus for carrying out the present invention. In the figure, MG is a metal gate electrode, 1 is GaAlAs
N ⁺ type semiconductor layer which is a layer, 2 is a semiconductor layer which is a GaAs layer, FL is a Fermi level, SL is an interface level, SE is an interface charge, t1 and t2 are sampling times, 11 is a bias voltage generator, 12 is a pulse bias voltage generator,
13 is an amplifier, 14 is a boxcar averager, 1
5 is an XY recorder, TT is a thermocouple, Q is a transistor, S is a source, D is a drain, G is a gate, and R is a resistor.

Claims (1)

[Claims] 1. An electric or optical pulse is applied to a gate of a field effect semiconductor device utilizing electric conduction at an interface such as a heterojunction interface, an interface between an insulator and a semiconductor, and a predetermined time after the end of the pulse. An interfacial electric conduction evaluation method characterized by measuring the transient response of the drain-source current of the device while changing the temperature of the field effect semiconductor device and examining the presence or absence of a defect level.