JPH0117249B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically, when forming an element pattern by etching, the edge of the pattern is tapered and a material such as an electrode material is vapor-deposited thereon. The present invention relates to a method for manufacturing a semiconductor device that enables good coverage and control of pattern size at the same time.

Conventionally, in the process of manufacturing semiconductor devices, element patterns are created by generating a resist pattern using a negative or positive resist, and then etching an insulating film according to this pattern using a wet or dry etching method. However, with this method, the edge walls of the pattern tend to have a shape that is nearly perpendicular to the film surface, resulting in poor coverage of vapor deposition materials such as aluminum and aluminum copper at the pattern edges. There was a problem.

For example, to explain the method of forming electrodes according to the conventional method, as shown in FIG.
A resist film 12 is formed on a substrate 11 such as SiO ₂ by a conventional method (see Fig. 1A), and then the SiO ₂ substrate is etched according to this electrode resist pattern to form the state shown in Fig. 1B. When the resist film 12 is further removed and an electrode material 13 (for example, aluminum, aluminum copper) is deposited, the state shown in FIG. 1C is obtained. However, this method
Because the edge wall surface of the etched portion of the SiO ₂ substrate 11 is etched with a steep slope,
Poor coverage is more likely to occur. Since such poor coverage causes migration of aluminum due to long-term circuit operation, a method of manufacturing a semiconductor device that eliminates this problem has been desired.

Therefore, the present inventors have conducted intensive research in order to eliminate the problems of such conventional semiconductor device manufacturing methods and to develop a semiconductor device manufacturing method that does not cause poor coverage of electrode materials, etc. However,
By ashing the resist using a plasma asher during the etching process, the inventors succeeded in achieving this objective, leading to the present invention.

According to the present invention, the steps include: forming a vapor phase grown oxide film on a silicon semiconductor substrate having thermal oxide films of different thicknesses formed on the surface; forming a resist pattern on the substrate; and forming a resist pattern on the substrate. Wet-etching the vapor-grown oxide film using the pattern as a mask; Ashing a part of the resist film using a plasma assher to move the edges of the resist pattern; and Ashing and moving the edges. Using the resist pattern as a mask, the thermal oxide film is wet-etched on the area where the thermal oxide film has been formed to a large thickness so that it remains, and a part of the resist film is ashed using plasma assher. The thermal oxide film on the area where the thermal oxide film was formed with a thick film thickness remains and is reduced to a thin film thickness using the resist pattern with the edges ashed and moved as a mask. A step of wet etching the thermal oxide film so as to remove the thermal oxide film on the formed region; and a step of ashing a part of the resist film using a plasma assher to carbonize and transfer the edges of the resist pattern. A step of wet-etching the thermal oxide film remaining on the region where the thick thermal oxide film has been formed using the resist pattern with the thickened edge as a mask to open an electrode window, and removing the resist film. Provided is a method for manufacturing a semiconductor device, comprising the steps of: forming an electrode material film on a substrate.

In a preferred embodiment of the present invention, a bulk electrode is formed using a self-alignment method, in which a collector electrode is formed in a region where a thermal oxide film is formed with a thick film thickness, and a base electrode is formed in a region where a thermal oxide film is formed with a thin film thickness. Form an electrode window.

The outline of the method of the present invention will be explained in comparison with the conventional method described above with reference to FIG. _2. For example, as shown in FIG. After etching the SiO ₂ substrate 14 halfway according to this resist pattern, the etching is temporarily interrupted (see the dotted line "B" in FIG. 2) and the resist film 15 is ashed by a plasma assher. (The dotted line in Figure 2B is removed) and etched again to remove the remaining SiO ₂
is removed (state shown in FIG. 2C), and finally an electrode material 16 such as aluminum is deposited to obtain the state shown in FIG. 2D. As described above, according to the method of the present invention, the resist film 15 is ashed by the plasma assher during the etching process, so as to make it clear that SiO ₂ Membrane 1
The edge portions of the four patterns are processed into a tapered shape, so that a vapor deposited film with good coverage of the electrode material 16 can be obtained as shown in FIG. 2D.

According to the present invention, the edges of the resist pattern are ashed and moved during etching by utilizing the controllability and isotropic progress of resist ashing by plasma assher, thereby removing electrode materials, etc. The coverage of the vapor deposition material can be improved, and the shape of the pattern wall surface can be controlled arbitrarily by appropriately selecting the timing, amount of ashing, and, in some cases, the number of times of resist ashing by plasma assher. It has the advantage of being able to Note that since the contact area with the electrode material is determined by the initial etching, the contact area does not change due to the resist ashing process using the plasma asher, and a predetermined pattern can be formed with high precision.

In order to explain the method of the present invention in more detail, an example in which the method of the present invention is applied to manufacturing a bulk electrode window of a self-aligned bipolar IC will be shown below with reference to FIGS.

As shown in FIG. 3A, a silicon single crystal substrate 2
For example, a thermal oxide film 22 (SiO ₂ ) of about 1000 Å is formed on
is formed, and then a vapor phase growth oxide film 23 of, for example, approximately 4000 Å is grown thereon. In FIG. 3A, section "C" indicates the base region, and section "D" indicates the collector contact region.

Next, as shown in FIG. 3B, a negative resist pattern 24 (about 7000 Å thick), for example, a bulk electrode is formed on the insulating film 23. In the figure, the "E" section indicates the base electrode section, and the "F" section indicates the collector electrode section (although in reality, the distance between the base electrode section and the collector electrode section is long).

Then, the vapor-phase grown oxide film 23 and the thermal oxide film 22 are etched according to this resist pattern 24. In the method of the present invention, for example, first, only the vapor-phase grown oxide film 23 is etched, and then the thermal oxide film 22 is etched.
is left in the state shown in Figure 3 (c). In this etching operation, the insulating film 23 can be etched isotropically by performing wet etching using a buffer solution of hydrofluoric acid and ammonium fluoride, so that the desired etching can be performed. In this way, an oxide film 22 of about 1000 Å remains on the base electrode portion “E” and a thermal oxide film 22 of about 1800 Å remains on the collector electrode portion “F”.

After etching the vapor-grown oxide film 23, the etching operation is temporarily interrupted and a part of the resist film 24 (dotted line in FIG. 3D) is etched using a plasma assher.
Ash to a thickness of about 1500Å. Such plasma ashing can be performed by a general plasma etching technique conventionally used for resist removal, etc., for example, by using oxygen gas in a plasma device equipped with a barrel-shaped chamber (8" x 18"). ,Degree of vacuum
This can be carried out by generating plasma at 1.0 atm and an output of 150 W for 5 to 6 minutes.

Next, as shown in FIG. 3E, the thermal oxide film 22 (1000 Å) of the base electrode portion "E" is wet-etched using a buffer solution of hydrofluoric acid and ammonium fluoride, and the thermal oxide film 22 of this portion is etched. The thickness of is set to 0 Å. At this time, a part of the thermal oxide film 22 of the collector electrode part "F" remains, and the vapor-phase grown oxide film 23 has a faster etching rate than the thermal oxide film 22, and normally, while the thermal oxide film 22 is etched by 1000 Å, about It is etched by 1400 Å (see the dotted line in Figure 3).

As shown in FIG. 3E, after the thermal oxide film 22 of the base electrode section "E" has been etched, etching is interrupted again and a part of the resist film 24 (the third (See the dotted line in the figure) Approximately 1500Å is incinerated. Thereafter, as shown in Figure 3, approximately 800 Å of the thermal oxide film 22 remaining on the collector electrode "F" portion is etched using, for example, a buffer solution of hydrofluoric acid and ammonium fluoride, and the thickness of this film is reduced. to 0 Å. Next, by over-etching the thermal oxide film by about 500 Å, the thermal oxide film 22 is etched to a total of about 1300 Å, and the vapor-grown oxide film 23 is etched to a total of about 1800 Å, resulting in a state as shown in Figure 3. . In addition, in FIG. 3, the dotted line portion indicates the portion etched by this operation.

Finally, the electrode window opening process is completed by removing the resist film 24 under appropriate plasma assher conditions, resulting in the state shown in Fig. 3 H, and the base electrode "E"
And the opening of the collector electrode "F" is completed. Incidentally, the distance between the base electrode and the collector electrode in the "G" section of FIG. 3H is actually long.

As shown in FIG. 4A, according to the conventional method, after forming a negative resist pattern, a vapor phase grown oxide film
3' and the thermal oxide film 22' are continuously etched, for example, the pattern edge wall surface 25 of the base electrode portion has a sharp shape, and in such a shape, the coverage 26 of the electrode material such as aluminum becomes extremely poor. Moreover, in the conventional method, in order to prevent shape deterioration, only the Si of the base electrode is exposed, and the remaining oxide film on the collector electrode must be opened again in a separate process using another mask. Note that "H" indicates a resist pattern edge.

In contrast, according to the present invention, as described above, it is possible to obtain the tapered pattern edge wall surface 27 as shown in FIG. Since Si can be exposed up to the top of the electrode, compared to the conventional method, there is no need to use another mask to open the collector electrode window, so one step can be omitted.

[Brief explanation of drawings]

FIGS. 1A, 1B, and 1C are explanatory diagrams for schematically explaining a conventional method of manufacturing a semiconductor device. FIGS. 2A, 2B, 2C and 2D are explanatory diagrams for schematically explaining a method of manufacturing a semiconductor device according to the present invention. Figures 3A, B, C, D, H, H, G, and C are explanatory cross-sectional views showing the state when providing a bulk electrode window of a self-aligned bipolar IC according to the present invention. . FIG. 4A is an explanatory diagram schematically showing the state of a pattern edge wall surface with a window opened according to the conventional method and the vapor deposited film when aluminum is vapor deposited thereon. FIG. 4B is an explanatory diagram schematically showing the state of the pattern edge wall surface opened in accordance with the method of the present invention and the vapor deposited film when aluminum is vapor deposited thereon. 11, 14... Substrate, 12, 15... Resist film, 13, 16... Electrode material, 21... Silicon single crystal substrate, 22, 22'... Thermal oxide film, 23,
23'...Vapour-phase growth oxide film, 24...Resist pattern, 25, 27...Pattern edge wall surface, 2
6, 28...Aluminum vapor deposited film, E...Base electrode part, F...Collector electrode part.

Claims (1)

[Claims] 1. A step of forming a vapor phase grown oxide film on a silicon semiconductor substrate having thermal oxide films of different thicknesses formed on the surface thereof, a step of forming a resist pattern on the substrate, and a step of forming a resist pattern on the substrate. a step of wet etching the vapor-grown oxide film using the resist pattern as a mask; a step of ashing a part of the resist film using a plasma assher to move the edges of the resist pattern; and ashing and moving the edges. Using the resist pattern as a mask, the thermal oxide film is removed so that the thermal oxide film on the areas where the thermal oxide film is formed with a thick film remains, and the thermal oxide film on the areas where the film is formed with a thin film thickness is removed. A process of wet etching a part of the resist film using a plasma assher to ash and move the edges of the resist pattern, and a process of forming a thick thermal oxide film using the resist pattern with the edges ashed as a mask. The present invention is characterized by comprising the following steps: wet etching the thermal oxide film remaining on the thickly formed region to open an electrode window; removing the resist film; and forming an electrode material film on the substrate. A method for manufacturing a semiconductor device. 2. Forming a bulk electrode window using a self-alignment method in which a collector electrode is formed in a region where a thick thermal oxide film is formed and a base electrode is formed in a region where a thin thermal oxide film is formed. A method for manufacturing a semiconductor device according to claim 1, characterized in that: