JPH0117288B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform equalizer that equalizes signal waveforms.

FIG. 1 shows a waveform equalizer developed by the inventor of the present invention that can shift the cosine group delay characteristic by a desired amount in the horizontal direction on the frequency axis. In the figure, 1 is an input terminal, 2 is a branching circuit that branches the signal input to this input terminal 1 and outputs it, and 3 is a 90° phase shifter that rotates the phase of the signal branched by the branching circuit 2 by 90°. 4a to 4d are delay circuits that delay the input signal by a predetermined time T (seconds) and output the delayed signal;
5 is an inverter that inverts the phase of the delayed signal and outputs it; 6a is an adder that adds the output of the branch circuit 2 and the output of the inverter 5; 6b is the output of the 90° phase shifter 3 and the delay circuit 4d 7a and 7b are amplitude adjustment circuits that adjust the respective output amplitudes of the adders 6a and 6b; 6c;
is an adder that adds the outputs of both amplitude adjustment circuits 7a and 7b and the output of the delay circuit 4a, and 8 is its output terminal.

Note that the circuits 4a, 4b, 5, and 6a allow
A first delay circuit network 10a that creates a main signal obtained by delaying one of the outputs of the first branch circuit 2 by a time T, and an added echo signal obtained by adding the above output and an inverted signal obtained by delaying this by 2T. The circuits 4c, 4d, and 6b constitute a second delay circuit network 10b that creates an added echo signal from the output of the phase shifter 3.

Next, the operation will be explained. However, since any signal waveform can be expressed as a linear sum of extremely thin pulses, we will treat these extremely thin pulses as input signals below.

The signal input to the input terminal 1 is divided into two by the branch circuit 2, and one is sent through the 90° phase shifter 3.
Each signal has a predetermined delay time T and is input to delay circuits 4c and 4d that do not cause signal attenuation. The other output of the branch circuit 2 is a direct delay circuit 4a,
4b.

Therefore, the signal input to the adder 6a is:
A signal with a delay time of zero, and a signal with a delay time of 2T whose phase is inverted by the inverter 5.
After the two signals are added, the amplitude adjustment circuit 7a
The amplitude is adjusted by , and becomes one input signal of the adder 6c. Similarly, the input signals of the adder 6b include a signal with a delay time of zero and a signal with a delay time of 2T, and after the two signals are added, the amplitude is adjusted by the amplitude adjustment circuit 7b, and the signal is input to the adder 6c. No. 1
This results in two input signals. Furthermore, in addition to the above input signals to the adder 6c, there is also a signal delayed by a time T by passing only through the delay circuit 4a, and this signal is directly input to the adder 6c without amplitude adjustment. Ru. Hereinafter, this signal will be referred to as a main signal, and the signal that has passed through the amplitude adjustment circuits 7a and 7b will be referred to as an echo signal. The signals added by the adder 6c are output from the output terminal 8.

Now, the amplitude of the main signal is normalized by 1, and the amplitude values (hereinafter referred to as tap coefficients) adjusted by the amplitude adjustment circuits 7a and 7b are defined as kcos θ ₀ and ksin θ ₀ , respectively. However, k and θ ₀ are constants, k is the amplitude ratio of the echo signal and the main signal, and θ ₀ is the group delay or amplitude characteristic of this waveform equalizer on the frequency axis in the horizontal direction with the cosine characteristic as the reference. This is the amount by which it can be shifted.

At this time, the transfer function of the entire equalizer F ₁ (ω) (ω=
2πf) is F ₁ (ω)=1−j2ksin(ωT−θ ₀ ) (1), and when k≪1, the amplitude and group delay characteristics G ₁
(ω) and τ ₁ (ω) are respectively becomes.

The characteristics at this time are shown in Figures 2a and b. As can be seen from this figure, while the amplitude characteristic in figure a remains unchanged, only the cosine-shaped group delay characteristic indicated by the broken line in figure b is shifted by an arbitrary frequency θ ₀ /T in the horizontal direction, that is, in the frequency direction. This equalizer can perform group delay equalization.

FIG. 3 shows the time domain waveform at this time. In the figure, a is the output signal of the amplitude adjustment circuit 7a, b is the main signal, and c is the output signal of the amplitude adjustment circuit 7b. The signals a and b are in phase, and the signal c is the same as both the signals a and b. It has a phase difference of 90°.

The equalizer in Figure 1 is configured as described above, so if the waveform distortion is small, the tap coefficient of the equalizer can be small, and even if delay equalization is performed, amplitude distortion will not occur. If the waveform distortion is large, the approximation on the right side of equation (2) no longer holds true, so when delay equalization is performed, amplitude distortion occurs, the independence of amplitude and group delay is not maintained, and the convergence during adjustment is impaired. It had the drawback of being bad.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and a signal after delay equalization by a delay equalization section is input to an amplitude distortion correction section,
In addition, by establishing a certain relationship between the tap coefficient of the amplitude distortion correction section and the tap coefficient of the delay equalization section, the independence of amplitude and group delay can be completely ensured even when the group delay distortion of the waveform to be equalized is large. The purpose is to provide a waveform equalizer that can maintain

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows a waveform equalizer according to an embodiment of the present invention. In the figure, 10 is a delay equalizer having exactly the same configuration as a conventional waveform equalizer, and 20 is a delay equalizer 10. It is an added amplitude distortion correction section, and the circuit elements 1b, 2b, 3b, 4 of the amplitude distortion correction section 20 are
e~4h, 5b, 6d~6f, 7c, 7d, 8b
are almost the same as the corresponding circuit elements in the delay equalizer 10. However, this amplitude distortion correction section 20
In this case, the inverter 5b is installed on the side of the echo signal whose phase has been rotated by the 90° phase shifter 3b, and the delay times of the delay circuits 4e to 4h are each set to 2T.

Note that the circuits 4e, 4f, and 6d generate a main signal obtained by delaying one of the outputs of the second branch circuit 2b by a time of 2T, and an added echo signal obtained by adding the above output and a signal delayed by 4T. The circuits 4g, 4h, 5b, and 6e constitute a fourth delay circuit network 20b to create an added echo signal from the output of the phase shifter 3b. are doing.

Next, the operation of the waveform equalizer configured as described above will be explained with reference to FIGS. 4 and 5.

Assuming that the amplitude and group delay characteristics at the output of the delay equalizer 10 are G ₂ (ω) and τ ₂ (ω), respectively, these are (2 ) is exactly the same as the formula, becomes. As can be seen from equation (3), the amplitude distortion is −cos2
It can be seen that it takes the form (ωT−θ ₀ ).

Next, the signal from the delay equalization section 10 inputted to the input terminal 1b of the amplitude distortion correction section 20 is sent to the branch circuit 2b.
One of them is input to the 90° phase shifter 3b and then added to the delay circuits 4g and 4h which have a delay time of 2T and do not cause signal attenuation, and the other has a delay time of 2T directly. Delay circuits 4e, 4f with
is applied to Therefore, the signals input to the adder 6d are a signal with a delay time of zero and a signal with a delay time of 4T. After these two signals are added, the output amplitude is adjusted by the amplitude adjustment circuit 7c.
It is adjusted so that acos2θ ₀ , and becomes one of the input signals of the adder 6f. Similarly, the signal input to the adder 6e is a signal with zero delay time that has passed through the 90° phase shifter 3b, and a signal that has a delay time of 4T and is input to the inverter 5b.
After these two signals are added, the amplitude adjustment circuit 7d adjusts the output amplitude to be asin2θ ₀ , and becomes one of the inputs of the adder 6f. Furthermore, adder 6f
As an input signal, there is a signal having a delay time 2T that has passed only through the delay circuit 4e, and is directly inputted to the adder 6f with a normalized amplitude of 1 without amplitude adjustment.

Therefore, the transfer function of the amplitude distortion correction section 20 is F ₃
(ω), then F ₃ (ω) = 1 + 2 a cos2 (ωT - θ ₀ ) (4), and the amplitude and group delay characteristics G ₃ (ω) and τ ₃ (ω) are respectively G ₃ (ω) = 20log ₁₀ [1+2acos2(ωT−θ ₀ )] τ ₃ (ω)=O(dB) (seconds) (5).

That is, it can be seen that the characteristics of the amplitude distortion correction section 20 are that the group delay characteristic is flat and only the amplitude characteristic changes in a cosine shape.

Therefore, when correcting amplitude distortion by cascading the delay equalization section and the amplitude distortion correction section shown in Fig. 4, it is necessary to compare the amplitude characteristics of equations (3) and (5). It can be seen that the amplitude distortion is minimized when a=k ² /2.

At this time, the amplitude characteristic Gt(ω) of the entire Figure 4 is Gt(ω)≒10log ₁₀ [1+2k ² +k ⁴ cos2(ωT−θ ₀ )・
{1−3cos2(ωT−θ ₀ )}](dB)(6), and the amplitude distortion term becomes a higher order term of ^k4 or higher,
Amplitude distortion becomes extremely small.

FIG. 5 shows various frequency characteristics of the circuit shown in FIG. 4 when a=k ² /2. That is, Figure a shows the group delay characteristic of the delay equalizer 10, Figure b shows the amplitude distortion generated in the delay equalizer 10, Figure c shows the amplitude characteristic in the amplitude distortion corrector 20, and Figure d shows the above delay. The overall amplitude characteristics when the equalization section 10 and the amplitude distortion correction section 20 are connected in cascade are shown.

However, in the figure, the broken line indicates the case where the deviation in the frequency axis direction is zero (ie, θ ₀ =0), and the solid line indicates the general case (θ ₀ ≠0).

In the above embodiment, a case has been described in which one echo signal before and after the main signal is used as the delay equalization section and the amplitude distortion correction section, but the present invention is not limited to only this case. Equalization can also be performed using a plurality of echo signals before and after the main signal, and in this case, it is possible to perform more complex equalization of group delay characteristics while correcting amplitude distortion.

Further, although the above-described embodiment circuit has the amplitude adjustment circuit and the inverter configured separately, these can also be configured with a gain adjustment circuit having a polarity inversion function. Further, as the delay circuit, a delay line with taps, a shift register, a cable, etc. can also be used.

Furthermore, the number of echo signals does not necessarily need to be the same before and after the main signal, nor does it need to be the same number in the delay equalization section and the amplitude distortion correction section.

As described above, according to the present invention, the delay equalization section and the amplitude distortion correction section that corrects the amplitude distortion generated by the delay equalization section are connected in cascade, and the tap coefficients of each of them have a certain relationship. Since the structure is configured to have a large group delay distortion without amplitude distortion, it is possible to equalize distortion with a large group delay, and since the independence of the amplitude and group delay is maintained, adjustment is facilitated.

[Brief explanation of drawings]

Figure 1 is a block diagram of a waveform equalizer developed by the inventor of the present invention, Figure 2 is a frequency characteristic diagram of the waveform equalizer of Figure 1, and Figure 3 is a diagram of the waveform equalizer of Figure 1. 4 is a block configuration diagram of a waveform equalizer according to an embodiment of the present invention, and FIG. 5 is a diagram of various frequency characteristics of a waveform equalizer according to an embodiment of the present invention. Figure a is the group delay characteristic diagram of the delay equalization section, Figure b
is an amplitude distortion characteristic diagram of the delay equalization section, FIG. c is an amplitude characteristic diagram of the amplitude distortion correction section, and FIG. d is a total amplitude characteristic diagram. 10... Delay equalization section, 20... Amplitude distortion correction section, 2...
1st branch circuit, 3... 90° phase shifter (first phase shifter), 4a to 4d... delay circuit, 5... inverter,
6a, 6b...Adder, 10a, 10b...First and second delay circuit networks, 7a, 7b...First and second amplitude adjustment circuits, 6c...Adder (first addition circuit), 2
b...Second branch circuit, 3b...90° phase shifter (second phase shifter), 4e to 4h...Delay circuit, 5b...Inverter, 6d, 6e...Adder, 20a, 20b...Third, third 4 delay circuit networks, 7c, 7d...third, fourth
amplitude adjustment circuit, 6f...adder (first addition circuit). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A first branch circuit that branches an input signal; one output of this branch circuit is delayed by a predetermined time T to create a main signal, and the output of one of the branch circuits and this main signal are The first step is to create an echo signal by adding the inverted signal of the signal delayed by 2T.
a delay network, a first phase shifting the other output of the branch circuit by 90°;
A second delay circuit that creates an echo signal by adding the output of this phase shifter and a signal delayed by a time of 2T, and the amplitude ratio of the echo signal and the main signal is expressed as k, cosine When the amount by which the group delay characteristics of this waveform equalizer is shifted in the horizontal direction on the frequency axis based on the waveform characteristics as a reference is θ ₀ ,
To the echo signal output of the first and second delay circuit networks above.
First and second amplitude adjustment circuits that adjust the amplitude with weights of kcosθ ₀ and ksinθ ₀ , and a first addition that adds the outputs of both amplitude adjustment circuits and the main signal output of the first delay circuit network. a delay equalization section including a circuit; a second branch circuit that takes the output of the delay equalization section as an input signal and branches the input signal; one output of this branch circuit is delayed by a predetermined time of 2T to produce a main signal; and a third delay network that creates an echo signal by adding the output of one of the branch circuits and a signal delayed by a time of 4T, and a third delay circuit that shifts the phase of the other output of the branch circuit by 90°. 2
a phase shifter, a fourth delay circuit network that creates an echo signal by adding the output of this phase shifter and an inverted signal of a signal delayed by time 4T, and the third and fourth delay circuit networks described above. third and fourth amplitude adjustment circuits that adjust the amplitude by adding weights of (k ² /2) cos2θ ₀ and (k ² /2) sin2θ ₀ to the echo signal output of and an amplitude distortion correction section equipped with a second addition circuit that adds the main signal output of the delay circuit network No. 3, and the amplitude distortion correction section that is provided with a second addition circuit that adds the main signal output of the delay circuit network No. 3. . A waveform equalizer, characterized in that the amplitude distortion correction unit performs correction with the amplitude distortion correction section having a flat group delay and a cosine-shaped amplitude characteristic.