JPH0118465B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a central processing unit in a multiprocessor system in which a plurality of central processing units share a main memory and operate in parallel. .

(Prior Art) Each central processing unit in a multiprocessor system that shares a main memory has its own operating system, and in order to be able to operate independently, a hardware fixed area on the main memory is used. Each must be held independently. Conventionally,
When a program running on each central processing unit accesses its respective hardware fixed area, the same logical address is accessed no matter what central processing unit is operating. Therefore, in order to ensure that the accessed hardware area is a hardware fixed area on the main memory fixed to the central processing unit, a real address is converted to an absolute address by a prefix conversion mechanism. This prefix conversion mechanism is a hardware mechanism that maps a hardware fixed area to an area unique to each processor.

On the other hand, some computers with virtual memory control have an address translation buffer (TLB) in the address translation mechanism to speed up address translation from virtual addresses (logical addresses) to real addresses.
Even in a conventional multiprocessor system using a virtual memory control method, the address translation buffer (TLB) converts a virtual address into a real address, and then a prefix conversion mechanism converts the real address into an absolute address.

(Problem to be Solved by the Invention) As mentioned above, each time a virtual address is translated into a real address using an address translation buffer (TLB),
Next, the conventional method of converting a real address into an absolute address using a prefix conversion mechanism had a problem in that it required more time for address conversion than a single processor system.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a central processing unit that reduces address conversion time in a multiprocessor system using virtual memory control.

[Structure of the invention]

(Means and effects for solving the problem) In order to achieve the above object, the central processing unit of the present invention has a conversion pair for directly converting a virtual address into an absolute address in the address conversion buffer of the address conversion mechanism. This shortens the time required to convert addresses from virtual addresses to absolute addresses.

(Embodiment) FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, 1 is a main storage device, 2 is a central processing unit, and 3 is a bus to which a plurality of central processing units and main storage devices are connected.

The main storage device 1 has a segment table 11 and a page table 12 for converting virtual addresses into real addresses. The central processing unit 2 includes a data buffer register 21 that stores data sent from the main memory 1 via the bus 3, a prefix conversion mechanism 22 that has a prefix register and calculates an absolute address from a real address, and an address conversion mechanism. Address translation mechanism 2 that obtains a real address from a virtual address as a buffer (TLB) owner
3. Select one of the outputs from the virtual address register 24 that holds virtual addresses, the control section 25 of the central processing unit 2, the prefix conversion mechanism 22, or the output from the address conversion mechanism 23 and output it onto the bus 3. It has a data selector 26.

Next, the operation of this embodiment will be explained with reference to FIG. 1 and FIGS. 2 and 3 which are operational flowcharts.

When the virtual address is sent from the buffer register 21 etc. to the control unit 25, the control unit 25 sends the virtual address to the virtual address register 24.
The virtual address register 24 holds the virtual address sent from the control unit 25 and then sends the virtual address to the address translation mechanism 23 and prefix translation mechanism 22. (Step S1) Depending on the address, it is determined whether the virtual address needs to be converted into a real address or whether the virtual address should be used as a real address. Control unit 25
determines whether to operate the address translation mechanism 23 or the prefix translation mechanism 22 from the received virtual address, and based on the judgment result, either the address translation mechanism 23 or the prefix translation mechanism 22 is operated. Make one work. The control unit 25 also controls the address translation mechanism 2.
It also controls the data selector 26 which controls whether the output from the prefix conversion mechanism 22 is output onto the bus 3 or the output from the prefix conversion mechanism 22 is output onto the bus 3 (step S2). Address conversion from virtual address to real address When necessary, the control unit 25 operates the address translation mechanism 23. The address translation mechanism 23 starts operating in response to an instruction from the control unit 25, and inputs the virtual address sent from the virtual address register 24. The address translation mechanism 23 checks whether a translation pair exists in the address translation buffer (TLB) for translating the sent virtual address into a real address. (Step S3) When a translation pair for converting a virtual address to a real address does not exist in the address translation buffer (TLB), the address translation mechanism 23 sends the virtual address as is to the data selector 26. When the data selector 26 needs to convert a virtual address into a real address, it is instructed by the control unit 25 to output the output from the address conversion mechanism 23 onto the bus 3; Outputs the sent virtual address onto bus 3. The virtual address output on the bus 3 is taken into the main memory 1 and converted from the virtual address to a real address using the segment table 11 and page table 12. (Step S4)
The converted real address is sent to the address conversion mechanism 23 via the bus 3, data buffer register 21, and control section 25. The address translation mechanism 23 sends this translated real address to the prefix translation mechanism 22. (Step S5) Whether or not a real address needs to be converted to an absolute address is determined depending on the address. The prefix conversion mechanism 22 determines from the real address whether or not to prefix convert the real address. (Step S6) When the prefix conversion mechanism 22 determines that prefix conversion is necessary for this real address, it performs prefix conversion from the real address to an absolute address using a prefix register, etc., and converts this absolute address into an address. It is returned to the mechanism 23. (Step S7) If the prefix conversion mechanism 22 determines that there is no need to perform prefix conversion on the real address, the prefix conversion mechanism 22 returns the sent real address to the address conversion mechanism 23 as is. (Step S8) Address conversion mechanism 23 Prefix conversion mechanism 2
When an absolute address is sent from 2, a translation pair is created to directly translate the virtual address to an absolute address, and the translation pair is stored in the address translation buffer (TLB). (Step S9) Also, the address conversion mechanism 23 is connected to the prefix conversion mechanism 22.
If a real address is sent from , create a translation pair to convert the virtual address to a real address,
The translation pair is stored in an address translation buffer (TLB). Thereafter, these translation pairs are used for virtual address to real address translation and virtual address to absolute address translation. (Step S
10) When a translation pair exists in the address translation buffer (TLB) to translate a virtual address to a real address,
The address translation mechanism 23 uses the translation pair to translate the sent virtual address into a real address.
The address conversion mechanism 23 sends the converted real address to the prefix conversion mechanism 22 (step S11). Thereafter, the prefix conversion mechanism 22 performs the operations of step S6 and step S7 or step S6 and step S8 described above, and also performs address conversion. The mechanism 23 performs the operation of step S8 or step S9 described above.

When there is no need to convert a virtual address to a real address, the control unit 25 uses the prefix conversion mechanism 22
make it work. The prefix conversion mechanism 22 starts operating according to instructions from the control unit 25 and inputs the virtual address sent from the virtual address register 24. The prefix conversion mechanism 22 directly replaces this virtual address with a real address, and determines whether or not it is necessary to convert this real address into an absolute address. (Step S12) When it is determined that it is necessary to convert the real address to an absolute address, the prefix conversion mechanism 22 uses a prefix register or the like to convert the real address to an absolute address. The converted absolute address is sent to the data selector 26. (Step S13) When determining that there is no need to convert the real address to an absolute address, the prefix conversion mechanism 22 sends the real address as is to the data selector 26. When operating the prefix conversion mechanism 22, the control unit 25 instructs the data selector 26 to output the output from the prefix conversion mechanism 22 onto the bus 3. The data selector 26 outputs the real address output from the prefix conversion mechanism 22 onto the bus 3 in accordance with instructions from the control section 25, and the real address is given to the main storage device 1.
(Step S14) From now on, when converting a virtual address for which a conversion pair to an absolute address is stored in the address translation buffer (TLB), the address translation mechanism 23
performs address translation using a translation pair stored in its address translation buffer (TLB) for directly obtaining an absolute address from a virtual address.

〔Effect of the invention〕

According to the present invention, since a translation pair for directly obtaining an absolute address from a virtual address is stored in an address translation buffer (TLB), this translation pair can be used when converting a virtual address to an absolute address. , it is possible to shorten the time required for address translation to directly obtain an absolute address from a virtual address.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and FIGS. 2 and 3 are operational flowcharts. 1...Main storage device, 2...Central processing unit, 22
... prefix conversion mechanism, 23 ... address conversion mechanism, 25 ... control unit, 26 ... data selector.

Claims (1)

[Scope of Claims] 1. A central processing unit in a multiprocessor system sharing a main memory using a virtual memory control method, which converts a virtual address to a real address and further converts the obtained real address to an absolute address. Address translation has an address translation buffer that stores translation pairs that directly obtain an absolute address from a virtual address when translation is required, and performs translation from a virtual address to a real address and from a virtual address to an absolute address. a prefix translation mechanism that directly translates a virtual address to an absolute address as needed when translation from a virtual address to a real address is not required; and an output of the address translation mechanism or the prefix translation mechanism. A central processing unit comprising: a data selector that selectively outputs data to the main storage device.