JPH0118520B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a memory access timing circuit for determining timing when a read/write memory (hereinafter abbreviated as RAM) is accessed as a register.

Prior Art and Problems In order to access a memory, various signals are required to determine the timing of its operation. Such signals are typically created using shift registers or the like to generate outputs with a fixed order and timing.

On the other hand, memory and registers serving as input/output circuits have different access timings, and therefore, in order to access RAM as a register, a timing circuit is required.

FIG. 1 shows the configuration of a conventional RAM access timing circuit for accessing RAM as a register. In the figure, 1 is an external bus, 2
is RAM, 3 is a bus timing circuit, 4 is an address bus, _5-1 and _5-2 are latch circuits, 6
is a driver receiver, 7 is a memory timing circuit, and 8 is an internal bus. In the bus timing circuit 3, 31 is an address matching circuit, 32 is a gate circuit, 33 is an OR circuit, 34 is a shift register, and 35, 36, and 37 are gate circuits.

In FIG. 1, when the external bus 1 writes data to the RAM 2 as a register, the central control unit (hereinafter abbreviated as CPU), not shown, turns on the write instruction signal *WT to the bus timing circuit 3. At the same time, a predetermined address is output via the address bus 4. address bus 4
The address given from address match circuit 31
When the address matches the preset address, the address match circuit 31 generates an output and opens the gate circuit 32. As a result, the write instruction signal *WT is sent to the shift register 34 via the OR circuit 33.
The shift register 34 is set in response to the clock signal CK. This results in output Q
1 is turned on and applied to the gate circuit 35.
A write instruction signal *WT is applied to the other input of the gate circuit 35, so that the signal CK1 is generated from the gate circuit 35, and the latch circuit 5
_-1 is added to the CK terminal. When the latch circuit _5-1 is applied with the signal CK1, the driver receiver 6
The data on the external bus 1 is latched via the external bus 1. on the other hand,
Shift register 34 outputs signal MEMREQ to memory timing circuit 7. The memory timing circuit 7 thereby sends various timing signals necessary for the operation of the RAM 2 to the RAM 2.
occurs and gives a memory write cycle to RAM. RAM2 is thereby connected to internal bus 8.
However, the latch circuit outputs the latched data to the internal bus 8 by applying the output of the gate circuit 35 to the output control terminal OC, and therefore the latch circuit 5 _- The data latched to ₁ is written to RAM2 in accordance with the memory write cycle. shift register 34
generates output Q3 at the time when writing to RAM2 is completed. The gate circuit 36 is opened by the signal MEMREQ, and an acknowledgment signal *ACK indicating the completion of the operation is thereby sent back to the CPU. Furthermore, the shift register 34 is reset and output Q1
is turned off, and therefore the latch circuit _5-1 stops operating.

Next, the data written to RAM2 is transferred to external bus 1.
When reading, the CPU sends the read instruction signal *RD
is turned on, and a predetermined address is output to the address bus 4. When the addresses match in the address match circuit 31, an output is generated from the gate circuit 32, the shift register 34 is set, the output Q2 is turned on, and the signal MEMREQ is output. The memory timing circuit 7 thereby provides a timing signal to the RAM 2 to provide a memory read cycle to the RAM. Therefore, the data written in RAM 2 is read out and output to internal bus 8. At the same time, the signal CK2 is output from the memory timing circuit, and the data on the internal bus 8 is latched in the latch circuit _5-2 , so that the data is held even after the memory read cycle is completed. On the other hand, an output is generated from the gate circuit 37 due to the generation of the output Q2, and is applied to the output control terminal OC of the latch circuit _5-2 , so that the data latched in the latch circuit _5-2 is read out. The signal is then output to the external bus 1 via the driver receiver 6. The shift register 34 generates an output Q3 at the time when the data output to the external bus 1 is completed, and an acknowledgment signal *ACK is sent back to the CPU via the gate circuit 36. The output Q2 is turned off and the latch circuit _5-2 stops operating.

In other words, in response to an access request from the CPU, the memory timing circuit 7 is activated by the memory access signal (MEMREQ) of the bus timing circuit 3.
is activated, but the memory timing circuit 7 is terminated independently of the bus timing circuit 3. Therefore, latch circuits _5-1 and _5-2 are provided between the driver receiver 6 and the RAM 2, and the memory timing circuit 7 is activated. Therefore, it is necessary to correct the timing of the bus timing circuit 3.

In this way, in order to access RAM as a register, conventional memory access timing circuits require a latch circuit and a latch circuit to adjust the timing of data input/output on the external bus and the timing of write and read cycles in RAM. This requires a circuit for control, making the circuit configuration unavoidably complicated.

Purpose of the Invention The present invention aims to solve the problems of the prior art, and its purpose is to provide a memory access timing circuit that does not require a latch circuit when accessing RAM as a register. It is in.

Embodiment of the Invention FIG. 2 shows the configuration of an embodiment of the memory access timing circuit of the present invention. In this figure, the same parts as in FIG. 1 are designated by the same numbers, and 9 is a flip-flop (FF).

In FIG. 2, when external bus 1 writes data to RAM 2 as a register,
The CPU turns on the write instruction signal *WT and outputs a predetermined address via the address bus 4. When the addresses match in the address match circuit 31, an output is generated from the gate circuit 32 and the shift register 34 is set in response to the clock CK. This allows the shift register 34
A signal MEMREQ is generated from the memory timing circuit 7 and applied to the memory timing circuit 7. The memory timing circuit 7 thereby generates various timing signals necessary for the operation of the RAM 2 and provides a memory write cycle. When RAM2 is given a timing signal, it passes through driver receiver 6 to internal bus 8.
Write the data of external bus 1 that is being output to.
On the other hand, the signal MEMSEL is output by the same operation as in the case of data reading, which will be described later, and furthermore, the signal T is output at the write end time.
FF9 is set and the memory write cycle is made to wait without being completed by the signal PAUSE. At the same time, the signal MEMACK is output, and the confirmation signal *ACK indicating the completion of the operation is sent through the gate circuit 36.
Sent back to the CPU. The CPU knows that *ACK has been returned, and sends the instruction signal *WT address bus.
OFF, thereby MEMREQ, MEMSEL
It will be turned off. By turning MEMSEL FF, FF9 becomes reset state, and signal PAUSE becomes
It is turned OFF and the memory write cycle ends.

Next, the data written to RAM2 is transferred to external bus 1.
When reading, the CPU sends the read instruction signal *RD
is turned on, and a predetermined address is output to the address bus 4. When the addresses match in the address matching circuit 31, the gate circuit 32
An output is generated from , the shift register 34 is set, and a signal MEMREQ is output. The memory timing circuit 7 thereby outputs a timing signal to the RAM 2, and therefore the data written from the RAM 2 is read out and output to the internal bus 8, and then output to the external bus 1 via the driver receiver 6. .

On the other hand, due to the address match in the address match circuit 31, the signal MEMSEL is output and the FF9
0 reset is released and the memory timing circuit 7 outputs the signal T at the time when the reading of data in the RAM 2 is completed.
is set and the signal PAUSE is output, causing the memory read cycle to wait without completing. At the same time, the signal MEMACK is output, and the confirmation signal *ACK indicating the completion of the operation is passed through the gate circuit 36.
is sent back to the CPU. As in the case of data writing described above, the CPU turns off the signal *RD and the address bus by returning *ACK, which turns off MEMREQ and MEMSEL, and therefore
FF9 is in the reset state and the signal PAUSE is
It is turned OFF and the memory read cycle ends.

That is, in the present invention, in the case of a memory access request from the CPU, the end of the memory timing circuit 7 is extended by the PAUSE signal when the bus is accessed, thereby eliminating the need to latch the data bus.

As described above, the memory access timing circuit of the present invention uses a latch circuit and a latch circuit to adjust the timing of data input/output on the external bus and the timing of writing and reading in the RAM in order to access the RAM as a register. There is no need for a circuit for this purpose, and the circuit configuration is simplified.

Effects of the Invention As explained above, according to the memory access timing circuit of the present invention, a timing signal for writing data on an external bus is generated to the memory in response to a write instruction signal, and a timing signal for writing data on an external bus is generated in response to a read instruction signal. A means for generating a timing signal for reading data from the memory onto an external bus is provided, and a confirmation signal indicating completion of writing or reading data in the memory and a halt to the memory access cycle are provided in accordance with the timing signal of the means. Since a means for outputting a signal is provided, the access timing of the memory can be made dependent on the external timing when the memory is accessed from the outside as a register. Therefore, a latch circuit and its control circuit for adjusting the data input/output timing on the external bus and the write/read timing in the memory are not required, and the circuit configuration is simplified.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional memory access timing circuit, and FIG. 2 is a diagram showing the configuration of an embodiment of the memory access timing circuit of the present invention. 1... External bus, 2... Read/write memory (RAM), 3... Bus timing circuit, 4... Address bus, 5 _-1 , 5 _-2 ... Latch circuit, 6...
Driver receiver, 7... Memory timing circuit, 8... Internal bus, 9... Flip-flop (FF), 31... Address matching circuit, 32... Gate circuit, 33... OR circuit, 34... Shift register, 35 , 36, 37... gate circuit.

Claims (1)

[Claims] 1. Timing for writing data on the external bus in response to a write instruction signal in a memory access timing circuit that determines the timing of writing and reading data when writing and reading data between an external bus and memory as a register. means for generating a signal to the memory and a timing signal for reading data in the memory to an external bus in response to a read instruction signal; 1. A memory access timing circuit comprising means for outputting a confirmation signal indicating completion of writing or reading and a signal halting a memory access cycle.