JPS6112294B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test pattern generator that can generate more effective test patterns for functional testing of a device under test.

FIG. 1 shows an example of the basic configuration of a pattern generating section of a conventional test pattern generator for functional tests. This operation is performed by setting the initial value (operand) of the test pattern to be generated in the pattern register 11, the arithmetic number for the pattern register 11 to the constant register 12, and setting the pattern to the arithmetic logic circuit 13 before the test is executed. Arithmetic and logic functions to be executed are respectively set by control signals passed through a terminal 14 from a control section (not shown) that controls the generation section. The test pattern is generated by performing arithmetic and logical operations on the contents of the pattern register 11 and the contents of the constant register 12 according to the set function of the arithmetic logic circuit 13, and the test pattern is generated through the terminal 15. It is applied to the test device as, for example, write information, and is also used as expected value information as necessary. At the same time, the arithmetic and logic results are entered into the pattern register 11 and become the contents of the pattern register 11 in the next test pattern period, that is, in the test cycle.

Most conventional test pattern generators generate test patterns using the configuration and operation described above. Such conventional test pattern generators are limited to relatively simple test pattern generation sequences, that is, test pattern sequences that can be expressed using arithmetic and logic, and are limited to complex test pattern sequences, such as interference performed in large-capacity memory. The generation of discontinuous (complex) test pattern sequences used in effectiveness tests, etc. is called a dummy cycle, which hinders test effectiveness, and the original test pattern sequence may contain unnecessary test pattern information. There was a problem. In other words, in order to implement a complex test pattern sequence, it is necessary to change the contents of the constant register 12 and the calculations and logic to be executed by the arithmetic logic circuit 13 midway through, and the test cycle is wasted for the changes. , the test cycle becomes a so-called dummy cycle in which no test pattern occurs. When this dummy cycle occurs, the state of the signal within the device under test changes during this time, and it may not be possible to perform a correct test.

The present invention makes it possible to generate complex test pattern sequences without generating dummy cycles, which was a drawback of conventional devices of this type, and its purpose is to improve the degree of freedom in test pattern generation.

According to the present invention, test pattern information is generated from the basic pattern generation section through logic processing, for example, through processing similar to conventional processing, and the generated test pattern information is controlled by an inversion control signal in an inversion control circuit to be tested. Supply to the device. The pattern memory is read during the test, and the read information is supplied to the inversion control circuit as the inversion control signal.
By pre-storing complex information in the pattern memory, complex test pattern sequences can be generated.

FIG. 2 shows data pattern information written to the memory circuit and its data pattern sequence when the device under test is a memory circuit.
In the figure, the memory size is shown reduced to a small size of 8×8 for convenience of explanation. Figure A is an example of a relatively simple test pattern that can be generated with a conventional test pattern generator, Figure B is an example of a relatively discontinuous test pattern, and Figure C is a certain area, in this example Y address 5. Examples of test patterns in which a simple test pattern changes to a discontinuous test pattern are shown below.

FIG. 3 shows one embodiment of a test pattern generator according to the present invention. The present invention comprises a basic pattern generating section 16, a pattern memory 17, and an inversion control circuit 18 that reads the output of the basic pattern generating section 16 and performs a signal inversion operation based on the read output of the pattern memory 17. The pattern memory 17 has a memory capacity equal to or larger than that of the device under test, and is accessed using address information from a dedicated address signal generation circuit or address information applied to the memory under test as an address signal. The basic pattern generating section 16 generates test patterns through logical processing.

The operation of FIG. 3 will be explained by taking as an example a case where the basic pattern generating section 16 has the same configuration as the conventional test pattern generator shown in FIG. 1. Before executing the test, each part of the basic pattern generating section 16 is set, and test information to be applied to the pattern under test is written in the pattern memory 17 in correspondence with the test pattern sequence or the address signal applied to the device under test. This writing is performed by applying an address signal from the terminal 19 and write information from the terminal 21 to the memory 17, respectively. For example, if the pattern memory 17 is accessed by an address signal applied to the device under test and it is desired to generate a test pattern as shown in FIG. Write each data information to the position.

Basic pattern generation section 1 when a test pattern is generated
6, the pattern memory 17 is accessed at the same time, and the inversion control circuit 18 inverts the test information from the basic pattern generation section 16 based on the information obtained thereby. The information thus obtained is used as a test data pattern for the device under test. For example, the second
If the pattern shown in FIG. 2B is written in the pattern memory 17 and "0" is always generated from the basic pattern generating section 16, the test pattern sequence shown in FIG. 2B is obtained at the terminal 15. When the basic pattern generator 16 generates a combination of "1" and "0", a very complex pattern is obtained at the terminal 15.

In the configuration shown in FIG. 4 showing another embodiment of the present invention, the basic pattern generating section 16 does not generate test patterns by calculation and logic as shown in FIG. The X address and Y address in the address signal are supplied from terminals 22 and 23 to the comparison circuit 24, respectively, and these are compared, or the logic between the X address, Y address and the contents of the constant register 25 provided exclusively for A comparison may be made and the result may be used as test pattern information. The timing of the comparison is terminal 2.
This is done by applying a control signal from the control unit through 6. In this invention, essentially the basic pattern generating section 1
It does not depend on the configuration of 6. Although this embodiment differs in the operation of the basic pattern generating section 16, other operations are completely the same as in the embodiment shown in FIG.

An embodiment in which the invention is further multifunctional will be described below. FIG. 2C shows a test pattern that is often used when conducting detailed tests of large-capacity memories, and is an example of a test pattern that is relatively continuous up to a certain characteristic region and then changes to a discontinuous test pattern sequence. When generating such a test pattern, according to the configuration and operation shown in FIG. 3 or 4, all of the generated test patterns depend on the information in the pattern memory 17, so Even in areas where it is not desired to depend on pattern memory information, it is necessary to write a certain amount of information.

On the other hand, in the embodiment shown in FIG. 5, the information from the pattern memory 17 is invalidated when a relatively simple test pattern occurs in one test pattern sequence, and the information is stored from the pattern memory 17 only when a complex test pattern occurs. Enable information. A gate circuit is connected between the output side of the pattern memory 17 and the inversion control circuit 18 to enable or disable the data from the pattern memory 17.
7 is inserted, and the gate signal for the gate circuit 27 is generated by applying a signal generated in real time during the test pattern sequence from the control section that controls the entire test pattern generator through the terminal 28. However, it is not necessarily limited to that.

According to this method, inverted data is written in advance only in the area in the pattern memory 17 where a complex test pattern is to be generated, and no settings are made in other areas, so data is written to the pattern memory 17. can be simplified.

As explained above, due to the structure of the test patterns generated by conventional test pattern generators, it is difficult to generate discontinuous test pattern sequences such as those used for interference effect testing of large-capacity memories, and there are also problems that dummy cycles are included. It was hot.

In contrast, the test pattern generator of the present invention transfers pattern information generated by a conventional test pattern generator characterized by continuous test pattern generation to a pattern memory 17 capable of discontinuous information generation. Generates test patterns by modifying them with output information. It is possible to generate a wide range of test patterns from simple to complex without the need for dummy cycles, and this is achieved with a relatively simple configuration. It has the advantage of being possible.
Generally, a plurality of bits are output in parallel from the basic pattern generating section 16, but these bits are outputted in parallel to the pattern memory 17.
Inverting or non-inverting control can be performed at the same time using the 1-bit output.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a conventional test pattern generator, and Fig. 2 shows various types of test patterns and test pattern sequences written into the memory circuit assuming a memory circuit as the device under test. FIG. 3 is a block diagram showing one embodiment of the test pattern generator according to the present invention, and FIGS. 4 and 5 are block diagrams showing other embodiments of the test pattern generator according to the present invention. It is. 11: pattern register, 12: constant register, 13: arithmetic logic circuit, 15: test pattern output terminal, 16: basic pattern generation section, 17: pattern memory, 18: inversion control section, 19: address signal input terminal, 21: Write information input terminal, 2
2: X address input terminal, 23: Y address input terminal, 24: comparison circuit, 27: gate circuit.

Claims (1)

[Claims] 1. A basic pattern generation section that generates test pattern information through logical processing, and an inversion control circuit that performs an inversion operation on the information generated by the basic pattern generation section and uses the output information as test pattern information for the device under test. A test pattern generator for testing, comprising a pattern memory having a capacity equal to or larger than that of the device under test, which is read during test execution and sends the read information as inversion control information to the inversion control circuit.