JPH0118611B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wireless communication device, and more particularly to a wireless communication device provided with a memory for storing frequency data for transmission and reception.

As shown in FIG. 1, some conventional wireless communication devices are equipped with a memory 10 for storing frequency data related to transmission frequencies and reception frequencies. To write to the memory 10, the address of the memory 10 is designated by rotating the address designation dial 12 provided on the operation panel 11. In addition, the frequency adjustment dial 14
The frequency data being adjusted is displayed on the display 34. When the desired frequency data is displayed, the write button 13 is pressed. A mark is displayed on the display 34 to indicate that the write operation has been completed. This display will disappear after about 1 second. To read and use the frequency data written in the memory 10, the memory mode button 17 is pressed. When the memory mode button 17 is pressed, the frequency data stored in the data area of the address corresponding to the rotational position of the address designation dial 12 is read out from the data bus 10a, and the child side data of the mode selection data bus switch 19 is read out. via bus 19b parent data bus 19c
The signals are output in parallel to the programmable counter 9 of the PLL circuit 4. When the operation mode is receive mode
A desired signal corresponding to the local signal output from the terminal 4a of the PLL circuit 4 to the local side of the mixer 3 is selected via the antenna 1, the RF unit 2, and the mixer 3. If you want to change control from memory mode to dial mode, press dial mode button 18.
is pressed to restore the mode selection data bus switch 19 and close the child side data bus 19a and the parent side data bus 19c. In this case, the frequency data is determined by the count value of the frequency division ratio setting circuit 20 formed by a pulse integration counter. Division ratio setting circuit 20
The count value is variable according to the addition and subtraction pulses output from the up button 15 and down button 16 or the rotation angle of the frequency adjustment dial 14. In an actual circuit, the variable range is below MHz, and the upper range is determined by the band selection means. Additionally, a range switching button and the like are provided for changing the variable range per revolution of the frequency adjustment dial. The frequency data generated by the frequency division ratio setting circuit 20, including the upper and lower digits, can be directly set using numeric buttons (not shown), or can be read from the memory 10 by operating the read button _K1 to read the data bus 20a. It can also be set via If the function of the mode selection data bus switch 19 is used for transmission/reception switching, cross-crossing operation can be performed. Also,
A clear ear function (variable receiving frequency during operation, returns to initial value when restored), etc. are provided. In the figure, reference numeral 5 is a reference signal oscillator, 6 is a phase comparator, 7 is a low-pass filter, and 8 is a voltage controlled oscillator.

In the conventional wireless communication device described above, the frequency data written in the memory 10, the frequency data read out, the frequency data output from the frequency division ratio setting circuit 20, and the setting information (addition/subtraction) input to the frequency division ratio setting circuit 20, The logical structure involved in data exchange between pulses, band information, frequency data formed by numeric buttons, etc. is not clear. Therefore, the operability is poor, various operating members and related circuits are required, the space factor of the operating panel 11 is reduced, and the number of parts is increased.

The present invention has been made in view of the above points, and an object of the present invention is to provide a wireless communication device that improves operability by streamlining the association between a memory that stores frequency data and frequency data generated by frequency adjustment operations. shall be.

The present invention is provided with a plurality of frequency division ratio setting means. Data exchange between each frequency division ratio setting means and the memory is determined by a memory address designation operation and a frequency adjustment operation. Normally, each frequency division ratio setting means performs a write operation with a data area of a designated address. The structure is such that the read operation is performed on the frequency division ratio setting means that has undergone the frequency adjustment operation for the first time immediately after the address designation operation.

An embodiment of the wireless communication device according to the present invention will be described below with reference to FIG.

Components that are the same in FIG. 2 and FIG. 1 are designated by the same reference numerals, so their explanation will be omitted.

In FIG. 2, 20a is an A-side frequency division ratio setting circuit, and 20b is a B-side frequency division ratio setting circuit. A-side frequency division ratio setting circuit 20a and B-side frequency division ratio setting circuit 20b
The active side is designated by the active side designation switch 31 which operates in response to the operation of the active side designation button 29.
Set frequency division ratio (hereinafter referred to as frequency data)
is output to the slave data buses 32a and 32b of the transmission/reception data bus switch 32, regardless of whether it is active or inactive. It is also displayed on the display 34 at the same time. A-side frequency division ratio setting circuit 20 becomes active
The a or B side frequency division ratio setting circuit 20b is capable of addition/subtraction pulse counting, write operation, and read operation.

12 is an address designation dial. The address designation dial 12 is formed of a rotary type switch and has slave contacts M ₁ to _{M o} and a master contact 12a.
Any one of M ₁ to _{M o} contacts the parent contact 12a to generate address data. The parent contact 12a undergoes a momentary disconnection process between adjacent slave contacts _M1 to _M0 during the addressing operation, and outputs a momentary disconnection pulse generated during this instantaneous disconnection process to the instantaneous disconnection pulse detector 27.

The addressing operation detection circuit is composed of an instantaneous pulse detector 27 for detecting pulse edges and a flip-flop circuit 28. When the address designation dial 12 is operated, the address designation dial 12
An instantaneous interruption pulse occurs at the parent contact 12a. The instantaneous interruption pulse detector 27 operates upon receiving the instantaneous interruption pulse and sets the flip-flop circuit 28.

The active side counting operation detection means is composed of an addition/subtraction pulse switch 30 operated by the active side designation button 29, an A side pulse edge detector 21a, and a B side pulse edge detector 21b. frequency adjustment dial 14,
The addition/subtraction pulses sent out from the addition/subtraction pulse generation means such as the up button 15 and the down button 16 are switched by the addition/subtraction pulse switch 30 to the A-side pulse edge detector 21a or the B-side pulse edge detector 21b.
Output to.

When the A-side pulse edge detector 21a operates while the flip-flop circuit 28 is set, the A-side readout control circuit 22a is controlled. Under control, the address data in the address register 26 is stored in the A address register 25a via the closed normally open contacts of the A address switch 24a. At the same time, a read control signal is output to the RD terminal of the memory 10, so the A address register 25
The frequency data stored in the data area of the address data stored in a is transferred to the data bus 10.
The signal is read out to the active A-side frequency division ratio setting circuit 20a via the signal a. At the end of the read operation, the flip-flop circuit 27 is reset. When the flip-flop circuit 27 is reset, the control signal output from the A-side pulse edge detector 21a to the A-side write control circuit 23a via the X'-X connection is valid and the A-side write control circuit 2
3a performs write control on the memory 10.

The B-side frequency division ratio setting circuit 20b includes a B-side pulse edge detector 21b, a B-side readout control circuit 22b, and a B-side pulse edge detector 21b.
An address switch 24b, a B side write control circuit 23b, and a B address register 25b are provided.
The operation sequence is similar to that on the side.

Here, frequency data is stored in address 1 of memory 18.
50.420.0MHz, 2nd address 50.540.0MHz, 3rd address
Assume that 145.540.0MHz is stored. When the address data of the A address register 25a is 1 and the address data of the B address register 25b is 2, the frequency data of the A side frequency division ratio setting circuit 20a is
50.420.0MHz, and the frequency data of the B side frequency division ratio setting circuit 20b is 50.540.0MHz. A side, B
Both sides can be finely adjusted, and the fine adjustment results are immediately written to the data area of each address.

Rotate the address designation dial 12 and select the child contact _M2
When , the address data in the address register 26 becomes 2. Operate the active side designation button 29 to select A.
Make the side active. When the frequency adjustment dial 14 is operated, the address data in the A address register 25a becomes 2, the frequency data becomes 50.540.0 MHz, and the frequency data at address 2 is controlled by the A side. Specify the child contact _M1 with the address designation dial 12 and
The frequency data at address 1, where side is active, is controlled by side B. In other words, the frequency data on the data buses 32a and 32b are reversed. If you specify address 3 and control it on the A side, the frequency data of address 3 will be displayed.
Since 145.540.0MHz is read out, you can immediately transmit and receive without having to specify the band.

The variable range per revolution of the frequency adjustment diamond 14 is in the lower digits (kHz in fine tuning, usually several
10kHz), the frequency data stored at the mechanical position of the frequency adjustment dial 14 not only cannot be changed in the lower digits, but also the frequency data in the memory 10 will be rewritten. As a countermeasure for this, when reading out the frequency adjustment dial 14,
It is preferable to provide a circuit that switches the variable range per rotation to fine inch operation. Note that in order to obtain a variable range below MHz, the MHz button formed by the bounce button is used together with the frequency adjustment dial 14, so that the upper digits are not affected.

If a write-inhibit button is provided and the circuit is configured so that the read operation is performed again when the write-inhibit button is restored, the clearer operation (fine adjustment of the reception frequency is possible, and the frequency data before the fine adjustment becomes the same after restoration) is facilitated.

When two frequency adjustment diamonds 14 are provided, the active side designation button 29 may be omitted.

A wireless communication device according to the present invention includes first and second frequency division ratio setting means for counting addition/subtraction pulses, addressing means for specifying a memory address, and addressing operation detection means for detecting an addressing operation. The first one that identifies the start of the counting operation and becomes active.
or the active side counting operation detecting means for identifying the second frequency division ratio setting means, and the first one which becomes active from the data area of the designated address according to the operation of the active side counting operation detecting means and the address designation detecting means. or reading means for reading the frequency data into the second frequency division ratio setting means, and writing means for writing the frequency data from the activated first or second frequency division ratio setting means into the data area of the designated address; Since it has a configuration equipped with this, it has the feature that the two frequency data stored in the memory can always be generated in an adjustable state. Therefore, the transmitting and receiving frequencies can be adjusted freely and the operability can be improved.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional wireless communication device, Figure 2 is a block diagram of a conventional wireless communication device.
The figure is a block diagram showing an embodiment of a wireless communication device according to the present invention. In the figure, 1 is the antenna, 2 is the antenna
RF unit, 3 is a mixer, 4 is a PLL circuit, 5 is a reference signal oscillator, 6 is a phase comparator, 7 is a low-pass filter, 8 is a voltage controlled oscillator, 9 is a programmable counter, 10 is a memory, 11 is an operation panel, 12 is an address designation dial, 13 is a write button, 14 is a frequency adjustment dial, 15 is a hot button, 16 is a down button, 17 is a memory mode button, 1
8 is a dial mode button, 19 is a data bus switch for mode selection, 20 is a frequency division ratio setting circuit, 20a is an A side frequency division ratio setting circuit, 20b is a B side frequency division ratio setting circuit, 21a is an A side pulse edge detection 21b is a B-side pulse edge detector, 22a is an A-side readout control circuit, 22b is a B-side readout control circuit, 23
a is an A side write control circuit, 23b is a B side write control circuit, 24a is an A address switch, 24
b is a B address switch, 25a is an A address register, 25b is a B address register, 26 is an address register, 27 is an instantaneous interruption pulse detector, 28
is a flip-flop circuit, 29 is an active side designation button,
30 is an addition/subtraction pulse detector, 31 is an active side designation switch, 32 is a data bus switch for transmission and reception, and 33
34 is a display, and _K1 is a readout button.

Claims (1)

[Claims] 1 A PLL circuit including a programmable counter whose frequency division ratio is determined by the frequency data input from the data bus, a memory for storing the frequency data, and a pulse integration counter for outputting the frequency data. A frequency ratio setting means,
A radio communication device comprising frequency adjustment means for sending addition/subtraction pulses to the frequency division ratio setting means to generate the frequency data, and first and second frequency division ratio setting means for counting the addition/subtraction pulses. and address designating means for designating the address of the memory, address designation operation detection means for detecting the address designation operation, and the first or second frequency division ratio setting that becomes active upon identifying the start of the counting operation. an active side counting operation detection means for identifying the means, and a first or second said one that becomes active from a data area at a designated address in accordance with the operation of said active side counting operation detection means and said address designation operation detection means. It comprises a reading means for reading frequency data to the frequency division ratio setting means, and a writing means for writing the frequency data from the active first or second frequency division ratio setting means to a data area of a designated address. , a wireless communication device configured to transmit and receive frequency data generated by first and second frequency division ratio setting means.