JPH0118630B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a shift register using a charge-coupled device (hereinafter abbreviated as CCD) and a method for driving the shift register. Since the concept of CCD was announced in 1970, rapid development has progressed against the background of conventional advanced integrated circuit technology, and in recent years various applications such as solid-state imaging devices, analog delay lines, filters, and digital memories have been carried out. It became like that. In particular, CCD solid-state image sensors have features such as low power consumption, small size and light weight, and no afterimage.
Better S/N than MOS type solid-state image sensor,
It has the advantage of being highly integrated.
Furthermore, an interline type high-sensitivity two-dimensional solid-state image sensor has been developed in which the photoelectric conversion region is formed by a P-N junction, and the vertical and horizontal registers for reading out the photoelectrically converted signal charges are composed of CCD shift registers. has been done. This solid-state image sensor has the features of both a conventional MOS type solid-state image sensor and a CCD solid-state image sensor, and has the advantage of high photoelectric sensitivity and good S/N ratio. However, conventional devices have the disadvantage that the amount of charge that can be transferred by the shift register is small, and when the amount of light incident on the PN junction increases and the signal charge increases, the shift register overflows. In fact, in a practical interline solid-state imaging device that uses a P-N junction as a photodetector and CCD registers as vertical and horizontal shift registers, the number of photodetectors in the horizontal direction must be at least 400. In addition, in the horizontal direction, there are 400 channel stopper P-N junctions, transfer gates, and CCD shift registers in this order.
Therefore, the width of a vertical register with a light-receiving area of 12.8H x 9.6Vmm ² for a 1″ bidicon compatible device is approximately 15 μm at the widest.
Also, in the vertical direction, at least the number of effective scanning lines of the TV, that is, approximately 500 elements are required, so one transfer stage of the shift register (one transfer stage per PN junction) is required. Even if the length of is long
It becomes 20μm. As is well known, in a two-phase drive CCD register, each transfer stage requires two regions, an accumulation region and a barrier region, and charge is stored only in the accumulation region, but at this time, the electron potential of the accumulation region is Since the constraint that the potential of the barrier region is always greater than the potential of the barrier region is necessary for highly efficient charge transfer, the amount of transferable charge stored in the storage region of the shift register becomes very small. In addition, in practical CCD interline imaging devices, in order to reduce resolution degradation due to non-transfer of charges, embedded channel CCDs are used in vertical and horizontal registers, which have a lower non-transfer efficiency although the amount of charge that can be transferred is smaller than that of surface channel CCDs. must be used. In addition, the four-phase drive mode, which has a large amount of charge transfer, is undesirable due to the need for ease of driving the device and ease of processing wiring and contacts during device manufacturing, and the amount of charge that can be transferred is generally smaller than that of the four-phase drive mode2. There is no need to use phase drive mode. When a conventional buried channel device is used in two-phase drive mode, the charge is transferred to Si-SiO ₂ during charge transfer.
Because the charge is transferred without interfering with the surface, the Si
Although the transfer efficiency is much better than the surface channel mode that transfers while interfering with the -SiO ₂ interface, the surface channel mode necessary to increase the amount of transferred charge never appears. For this reason, the amount of charge that can be transferred in the vertical register of the conventional structure is extremely small. However, in general, in CCD imaging devices, the noise of the output amplifier is small, so even with the vertical registers subject to the above conditions, an S/N of about 60 dB can be easily obtained when the maximum amount of charge is transferred. If the amount of charge sent from the PN junction to the shift register increases further, not only will the S/N ratio not improve any further, but the shift register will overflow, causing a so-called blooming phenomenon. An object of the present invention is to provide a shift register capable of transferring a large amount of charge that does not easily cause blooming even when a large amount of charge is transferred from a P-N junction to the shift register, and a method for driving the same. . According to the present invention, the charge transfer electrodes in each group include a first charge transfer electrode group connected to the first drive pulse phase and a second charge transfer electrode group connected to the second drive pulse phase. In a two-phase drive charge transfer device having a charge accumulation region and a barrier region arranged every other transfer electrode under each transfer electrode, the barrier region is arranged from the substrate side to the substrate, a layer having a conductivity type opposite to that of the substrate,
It has a laminated structure in the order of a layer having the same conductivity type as the substrate, an insulating film, and a transfer electrode, and the potential at the boundary between the insulating film and the layer having the same conductivity type as the substrate is of a conductivity type opposite to that of the substrate. There is obtained a shift register characterized in that the potential is smaller than the maximum potential in the layer having the transfer electrode, and both of the potentials are smaller than the potential obtained by subtracting the flat band voltage from the voltage applied to the transfer electrode. Further, according to the present invention, in the shift register, the potential of the storage region during charge storage is changed between the potential of the storage region when there is no charge and the maximum potential of a layer having a conductivity type opposite to that of the substrate in the barrier region. A shift register driving method characterized by the following is obtained. According to the present invention, a shift register is obtained that does not have the conventional drawback that the shift register easily overflows. Hereinafter, the present invention will be explained in detail using the drawings. Figure 1 shows the conventional method using the interline method.
FIG. 2 is a top view of a light receiving section and a vertical register section of a CCD two-dimensional imaging device. In this specification, a case will be described in which a P substrate is used as the semiconductor substrate, but it goes without saying that the contents can also be applied to a case in which an N substrate is used. First, 101 is a SiO ₂ layer with a thickness of 5,000 to 10,000 Å formed on a silicon substrate, and is called a field oxide film that prevents the formation of channels. Normally, channel stop diffusion occurs under the field oxide film, and although it has the same conductivity type as the substrate, it has a higher impurity concentration than the substrate. On the silicon substrate are an N ⁺ region 102, an N region 104,
An N ⁻ region 105 is formed. The N ⁺ region forms a P-N ⁺ junction with the substrate and functions as a diode for photoelectric conversion, and the N region 104 and the N ^- region 1
05 serves as the storage area and barrier area of the vertical CCD register 108. N ⁺ area, N area,
A SiO ₂ layer (not shown) with a thickness of 1000 to 3000 Å is provided on the N ⁻ region, and a transfer gate electrode 103 and a transfer electrode 109 are further provided thereon.
The transfer gate electrode acts as a control gate when sending the charge stored in the P-N ⁺ junction to the shift register 108, and the transfer electrode 109 controls charge transfer within the shift register 108. These transfer electrodes are connected for each horizontal line, and vertical transfer pulses Φ ₁ , 106 and Φ ₂ 107 are supplied every other line. Next, the operation of this device will be briefly explained in order to clarify the effects of the present invention. First, electrons generated by the incident light are stored in the N ⁺ region. The number of electrons generated is proportional to the intensity of the incident light. In the first field Φ ₁ 10
When the transfer gate electrode 103 is turned ON with Φ 6 ON and Φ ₂ OFF, light is applied to this storage region from the N ⁺ region facing the storage region of the transfer electrode to which the Φ ₁ pulse is applied. The generated electrons are transferred. Next, transfer gate electrode 10
If you turn off 3, turn Φ ₁ off, and turn Φ ₂ on, electrons will flow from the storage region under the transfer electrode connected to Φ ₁ to the storage region under the transfer electrode connected to Φ ₂ below. Move. In this way, Φ ₁ and Φ ₂ are turned ON and OFF.
Each time it is reversed, the charge moves downward one step at a time. The charge that has thus reached the bottom stage of the shift register is then sent to the horizontal CCD register (not shown) when the ON and OFF states of Φ ₁ and Φ ₂ are reversed.
It is read out from this register as a video signal.
In the next field, electrons are taken out to the vertical register from the N ⁺ region facing the storage region under the transfer electrode connected to Φ ₂ and read out as a video signal by the same means as described above. By sequentially repeating these two fields, an interlaced video signal can be obtained. Now, when light is incident on one P-N ⁺ junction, when the transfer gate 103 is turned on, charges corresponding to the storage area of the vertical register 108 are injected, but the amount of charge that can be transferred to the vertical register is It is determined by the concentration of the silicon substrate, the concentration of the N region, the thickness of the oxide film (not shown) mentioned above, and the voltage applied when the transfer electrode is turned ON and OFF. Vertical register overflows. Figure 2 shows the potential distribution in the depth direction of the storage region and barrier region of the conventional two-phase drive and embedded channel shift register shown in Figure 1 as a function of the amount of signal charge present in the storage region. It is something. In this figure, 201 is a SiO ₂ layer (not shown) in FIG. 1, 202 is an N region or N ^- region in FIG. 1, 203 is a P-type silicon substrate, 204 is a P-N junction boundary, V _G
−V _FB is the voltage effectively applied to the transfer electrode when Φ ₁ or Φ ₂ is in the ON state. In this figure, the same numbers as in FIG. 1 are the same parts and have the same functions. This also applies to the following figures.
S ₁ , S ₂ , and S ₃ are respectively in the state where the signal charge in the accumulation region is 0, the state where it has increased slightly, and the state where it has increased further and the signal charge is
The figure shows a state where the electron potential has become equal to V _G −V _FB , just as interference with the SiO ₂ surface is about to begin. If the amount of electrons increases further, the electrons will start to interfere with the surface, so the amount of charge in the S ₃ state will be the maximum amount of charge that can be transferred by the buried channel.
Therefore, in a charge transfer device with a conventional structure, in order to enable the transfer of this amount of charge, the potential shape of the barrier region becomes the maximum value V _G - V _FB at the Si-SiO ₂ interface, as shown in B, and the substrate It gets smaller as you go in that direction. In this case, the maximum amount of charge that can be transferred is qsNo(Xj−Xn), where S is the area of the storage region, as can be seen from the figure.
becomes. However, q is the unit charge No is the donor density, Xj
is the junction depth, and Xn (<Xj) is the depth from the junction surface to the position where the charge exists. FIG. 3 shows the potential distribution in the depth direction of the storage region and barrier region of the two-phase drive, embedded channel shift register with a large amount of transferable charge according to the present invention. In the device of the present invention, the accumulation region has the same impurity profile as in FIG. 2, and the potential profiles S ₁ and S ₃ are the same as S ₁ and S ₃ in FIG.
It is made the same as However, the potential of the barrier region of the device according to the invention has a shape shown at 305, unlike in the case of FIG. In addition, the impurity profile of the barrier region is also as follows from the substrate side: P substrate 203, N region 301, P region 302.
This is different from the case in Figure 2. Assuming that the impurity concentration in each region is constant, the electric field in each region is expressed as shown in FIG. Here, the direction of the electric field was positive from SiO ₂ to the substrate. In FIG. 4, X ₁ to X ₅ all indicate distances measured from the Si-SiO ₂ interface 304, where X ₁ is the maximum potential point in the P layer 302, and X ₂ is the maximum potential point in the P layer 302.
2 and the N layer 301, X ₃ is the potential minimum point in the N layer 301, X ₄ is the boundary between the N layer 301 and the P substrate 203, and X ₅ is the position where depletion of the P substrate 203 starts. . It is obvious at first glance that the potential shown in FIG. 3 can be obtained by integrating the electric field shown in FIG. From this, it can be seen that there actually exists an impurity profile that provides the potential shown by 305. Therefore, the potential 303 of the barrier region is
As shown in the figure, it has a value V ₁ smaller than V _G −V _FB at the Si-SiO ₂ interface 304, becomes minimum at X ₁ in the P layer 302, and inflects at the boundary X ₂ between the P layer 302 and the N layer 301. It has a maximum value V ₂ smaller than V _G −V _FB and larger than V ₁ at X ₃ in the N layer 301, and has an inflection point at the boundary X ₄ between the N layer 301 and the P substrate 203,
The size can be further reduced toward the P substrate 203. When charge flows into the storage region of this shift register, it first starts to accumulate from the maximum potential point of potential profile _S1 in Fig. 3, and when the amount of charge increases and the electron potential reaches V _G −V _FB , the surface and start interfering. As more charges flow in, the charges accumulated in the P and N layers hardly increase, and most of the charges are accumulated at the Si-SiO ₂ interface, and the electron potential reaches V ₂ at point X ₃ in Figure 3. increase to. If the number of electrons increases further, it will overflow from point _X3 to the next transfer stage. The amount of charge at the point when the electron potential becomes V _G −V _FB and it just starts to interfere with the surface is expressed as qN _D (Xj−Xn)S, and the electron potential becomes V ₂ . The amount of charge at that time is approximately given by pN _D (Xj−Xn)S +Co{V ₂ −(V _G −V _FB )}. Here, Co is the oxide film capacitance of the storage region. By thus changing the potential profile of the barrier region from the conventional structure, it was possible to increase the amount of transferable charge by the second term compared to the case of a pure buried channel. Next, some points to be noted in realizing such a potential distribution of the barrier region will be described. First, the potential V ₁ of the Si-SiO ₂ interface 304 is set to V _G −
In order to make V _FB smaller than FB, the total amount of donor and acceptor ions included from point _X5 to _X1 becomes zero, and the acceptor ions existing from _X1 to the Si- _SiO2 interface are concentrated in The impurity distribution must be such that it creates a positive electric field. Also, the potential V ₂ at the maximum potential point X ₃ in the N layer is V _G
In order to be smaller than −V _FB , it is necessary to create an impurity distribution such that the increase in potential due to donors and acceptors existing between X ₅ and X ₃ is less than V _G −V _FB . Another important point is that even if the amount of transferred charge is small, in order to prevent the charge from interfering with the surface when it crosses the barrier during transfer, it is necessary to set V ₁ < _{V 2} . Potential rise up to SiO ₂ x ₁
It is necessary to create an impurity distribution such that the potential rise is greater than that from X3 to _X3 . Generally, an impurity distribution having such a desired potential distribution is formed in the P substrate 203, the N region 301, the P layer 302, and the SiO ₂ layer 2.
It can be obtained by solving the one-dimensional Poisson's equation by giving the substrate voltage and the transfer electrode voltage for the region including 01. Next, the operational characteristics of the shift register with a potential barrier according to the present invention are determined by referring to the potential distribution obtained by solving Poisson's equation, and determining the transfer electrode voltage in the buried mode and the maximum transfer charge amount in the surface mode. Let's clarify this further by examining the relationship between them. Figure 5a shows how the shape of the potential barrier, which has the characteristics shown in Figure 3, changes depending on the effective transfer electrode voltage (V _G - V _FG ), and the effective transfer The electrode voltage is V _A → V _B →
As V _C → V _D increases, the potential at the Si-SiO ₂ interface increases accordingly, V _1A → V _1B → V _1C → V _1D , and the voltage at the maximum potential point in the N region also increases to V _2A.
→V _2B →V _2C →V _2D .
FIG. 5b shows the dependence of the potential shape of the storage region on the effective electrode voltage using the same vertical and horizontal axes as in FIG. 5a. From this figure, it is obvious that when V _G −V _FB increases as V _A → V _B → V _C → V _D , the potential at which the charge starts to interfere with the surface increases as shown in the figure, V _A → V _B → V _C → V _D increases, and the depth from the surface where the signal charge exists when it starts to interfere with the surface is X _A →X _B →X _C →
It can be seen that X _D becomes smaller and the maximum potential of the storage region also becomes larger. Using these figures, the amount of charge that can be transferred for each value of V _G −V _FB is determined as follows. Here, X _A , X _B , X _C , and X _D are each V _G −V _FB
indicates the maximum depth at which signal charges exist when V _A , V _B , V _C , and V _D are present.

[Table] This table shows that as the transfer electrode voltage increases, the amount of charge transferred in buried mode decreases, and when the transfer electrode voltage increases to a certain value, surface mode transfer begins and the amount of transferable charge gradually increases. I understand that. In general, transfer in surface mode is given by (electrode voltage - maximum potential in the N layer in the barrier region) x oxide film capacitance, and if the value in parentheses is 2 to 3 volts, it is the amount of charge transferred in normal buried mode. Become more. Therefore, increasing V _G −V _FB has a great effect in increasing the amount of transferred charge by allowing the buried mode and surface mode to coexist when good transfer efficiency is not necessarily required. Figure 6 shows the relationship between the effective transfer electrode voltage (V _G −V _FB ) and the potential distribution of the barrier region in the P region 302.
The impurity concentration of is shown as a parameter a,
V _G −V _FB increases in the order of b and c. In addition, 1, 2, and 3 in the figure are when the concentration of the P region is the highest,
The middle case indicates the lowest case. From this diagram
When V _G −V _FB is low, transfer is performed in complete buried mode in 1, 2, and 3, and the surface mode never appears, but when V _G −V _FB is intermediate, transfer in 1 is in surface mode. In 2, it became possible to transfer the surface mode, but in 3, it became a complete buried mode, and when V _G −V _FB is high, 1, 2,
All three now allow surface mode transfer.
It can also be seen that the higher the concentration of the P region, the lower the maximum potential in the N layer (that is, the difference between V _G −V _FB and this maximum potential becomes larger). Putting these together, the higher the concentration of the P region, the lower the transfer electrode voltage allows for surface channel transfer, and the amount of charge that can be transferred in both surface mode and buried mode at the same transfer electrode voltage. It can be seen that the amount increases. Therefore, it is generally advantageous to have a higher concentration in the P region. Fig _. 7 shows _{experimentally} what was described in Figs. This figure shows the relationship between the amount of transferred charge and the amount of charge transferred by the buried channel.
This figure shows that as V _G −V _FB increases, the transferable amount in the buried mode decreases, but the surface mode increases, so the transferable charge amount increases as a whole.
The higher the concentration of the P region, the larger the amount of charge that can be transferred in both the buried surface mode, and the higher the concentration of the P region, the more surface mode transfer becomes possible at a lower V _G −V _FB . Recognize. These correspond well to what has been explained in connection with FIGS. 5 and 6. Therefore, from this figure, we can explain the potential shape of the barrier region with reference to Figure 3 and increase the concentration of the P region within the range that satisfies the requirements and lower the maximum potential in the N region as much as possible to reduce the amount of transferred charge. The best thing can be learned from the points. When the shift register according to the present invention is used as the vertical register shown in Fig. 1, the amount of transferred charge can be greatly increased compared to the case of only the conventional buried mode, so that vertical shift can be performed even in the case of strong incident light. The register saturation phenomenon has become less likely to occur, and blooming has been greatly alleviated. In addition, normal imaging devices require high resolution, that is, high transfer efficiency, for incident light until a predetermined S/N is obtained, but the resolution deteriorates somewhat for incident light that is stronger than that. Therefore, in an imaging device using the resistor of the present invention, the embedded channel mode is used up to the amount of charge necessary to obtain the predetermined S/N, and the embedded channel mode is used for the amount of charge beyond that. The surface channel mode is also allowed and the increase in the total amount of charge can be measured.

[Brief explanation of drawings]

Fig. 1 is a top view of an interline type CCD imaging device, Fig. 2 is a potential distribution in the depth direction of the storage region and barrier region of the shift register used in this device, and Fig. 3 is a diagram showing the potential distribution in the depth direction of the storage region and barrier region of the shift register used in this device.
The structure and potential distribution of the storage area and barrier area of the CCD resistor, Figure 4 shows the electric field distribution of the barrier area of the resistor shown in Figure 3, and Figure 5 shows the electric field distribution of the barrier area of the resistor shown in Figure 3.
FIG. 6 shows the dependence of the potential distribution of the barrier region of the resistor shown in FIG. 3 on the impurity distribution and the transfer electrode voltage. Figure 7 shows V _G
FIG. 3 is a diagram showing the relationship between −V _FB and signal charge amount. 101 is a field oxide film, 102 is an N ⁺ region,
103 is a transfer gate, 104 is a storage region, 105 is a barrier region, 106 and 107 are clock pulses, 108 is a shift register, 109 is a transfer electrode, 201 is a gate oxide film, 202 is an N region or N ^- region, 203 is a P region Substrate, 204 is a P-N junction, 301 is an N region, 302 is a P region,
303 is the N region, 304 is the Si-SiO ₂ interface, 30
5 is barrier potential.

Claims (1)

[Claims] 1. A first charge transfer electrode group connected to the first drive pulse phase and a second charge transfer electrode group connected to the second drive pulse phase, and charge transfer of each group. In a two-phase drive charge transfer device in which electrodes are arranged every other time and a charge accumulation region and a barrier region are provided under each transfer electrode, the barrier region is arranged from the substrate side to the substrate, a layer having a conductivity type opposite to that of the substrate, and the substrate. has a laminated structure in the order of a layer having the same conductivity type, an insulating film, and a transfer electrode, and the potential at the boundary between the insulating film and the layer having the same conductivity type as the substrate has a conductivity type opposite to that of the substrate. 1. A shift register characterized in that the shift register is configured such that the potential is smaller than the maximum potential of the layers including the transfer electrode, and both of the potentials are smaller than the potential obtained by subtracting the flat band voltage from the voltage applied to the transfer electrode. 2 A first charge transfer electrode group connected to the first drive pulse phase and a second charge transfer electrode group connected to the second drive pulse phase, and the charge transfer electrodes in each group are arranged every other In a two-phase drive charge transfer device, which has a charge accumulation region and a barrier region under each transfer electrode, the barrier region is formed from the substrate side, a layer having a conductivity type opposite to that of the substrate, and a layer having the same conductivity type as the substrate. has a laminated structure in the order of a layer, an insulating film, and a transfer electrode, and the potential at the boundary between the insulating film and the layer having the same conductivity type as the substrate is the highest among the layers having the opposite conductivity type to the substrate. A method of driving a shift register configured to have a potential smaller than the potential, and also smaller than the potential obtained by subtracting the flat band voltage from the voltage applied to the transfer electrode, in which the potential of the storage region during charge accumulation is equal to the potential when the storage region has no charge. 1. A method for driving a shift register, comprising changing the potential between a potential and a maximum potential of a layer having a conductivity type opposite to that of a substrate in a barrier region.