JPH0119305B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample number conversion circuit, and more particularly to a circuit that converts the number of samples of an image signal or the like.

In digital processing of image signals and audio signals, the signals are represented as a set of sample values. Since not only audio signals but also image signals are processed as electrical signals whose amplitude changes over time due to scanning, the sample values form a time series, and the time interval between samples is usually constant. .

If the interval between samples is sufficiently small relative to the speed of change of the signal, the series obtained by converting the number of samples by sample thinning or interpolation will have the same number of sample values. This is a good approximation of the series. Let the sequence S _I of M samples be the sequence S ^- _O of N samples
Suppose you convert it to Here, M and N are positive integers. If M>N, the result of the transformation is approximately equal to a sample sequence obtained by coarsely sampling the same signal.
If the sample time intervals before and after conversion are made equal, the signal will be temporally compressed after conversion. In the case of image signals, this is equivalent to reducing the image. Conversely, if M<N, the conversion result will be close to a sample sequence obtained by sampling the signal more densely, and if the sampling intervals before and after conversion are the same, it will be possible to time-expand the signal and enlarge the image. Become.

In circuits that digitally perform sample number conversion as described above, the relationship between numerical values M and N has conventionally been limited to relatively simple ones.

FIG. 1a is a block diagram showing a conventional example of the configuration of a sample number conversion circuit when M>N. The sample value series _S1 before conversion is stored in the memory 11, and the address counter 12 receives the address count up signal.
It is counted up by the clock as SF,
Sample values DT are obtained sequentially. The same clock is sent to the frequency division counter 13 as the frequency division count up signal CK.
The count value of the frequency division counter 13 is also provided as one input of the comparison circuit 14. Comparison circuit 1
The other input of 4 is a binary signal indicating the division ratio.
When DR is being applied and the count value of the frequency division counter 13 matches the signal DK, the comparison circuit 14 outputs a matching pulse. This pulse is given to the reset terminal of the frequency division counter 13 and resets the frequency division counter 13.
repeats counting with a period equal to the numerical value DR.

The coincidence pulse is also output as a re-sampling pulse SM, indicating that the output value DT of the memory 11 at the time when this pulse is output is to be the sample value after conversion. Therefore, the output value of the memory 11 only at the time when the resampling pulse SM is output is the converted sample value sequence S ^- _O. For example, using this resampling pulse SM, the output value of memory 11 is transferred to another output memory (or shift register).
It will be easily understood that if the sample value sequence S - _O after transformation is written to , the converted sample value sequence S ^- O will be stored in its memory. FIG. 1b is a diagram showing an example of sample number conversion by the conversion circuit as described above, and shows a case where the frequency division ratio is 2. In the following, for simplicity, it is assumed that the sample value is a binary signal 0 or 1. In this example, M and N are 2 to 1
It forms a simple ratio of , and sample number conversion is equivalent to thinning out every other sample. In the circuit configuration as shown in FIG. 1, the ratio of M and N is generally equal to the frequency division ratio DR, and the conversion is usually performed by thinning out every DR-1 sample. When the ratio of M and N is not an integer, comparator circuit 1
It is possible to change the input signal DR to the resampling pulse SM every time the resampling pulse SM occurs, but this control is complicated.

FIG. 2a is a block diagram showing a conventional example of the configuration of a sample number conversion circuit when M<N. This second figure a
In this case, the functional operation of each part is the same as in the case of FIG. 1a, but the connections of signal lines are different. Frequency division count up signal applied to frequency division counter 23
The clock as CK is output as is as a resampling pulse SM, and the coincidence pulse output from the comparator circuit 24 resets the frequency division counter 23 and generates a count-up signal for the address counter 22.
This count-up signal SF is used as SF.
As a result, the address counter 22 is counted up. As a result, the resampling pulse SM with only the frequency division ratio of the signal DR input to the comparator circuit 24 is generated.
One count up pulse SF is generated per time.
Therefore, each sample value of the sample sequence S _I before conversion is output as a sample value of the sample sequence S ^- _O by a division ratio of DR, and the number of samples is multiplied by DR.

FIG. 2b shows an example of conversion when the frequency division ratio is 2, that is, M:N is 1:2. In the circuit configuration as shown in FIG. 2, it is normal that N is an integer multiple of M; otherwise, the input value DR to the comparator circuit 24 must be changed for each count-up pulse SF.
Control is complicated.

In order to be able to arbitrarily select the values of M and N in the conventional circuit configuration as described above, it is necessary to switch the circuit connections in FIGS. 1 and 2 according to the magnitudes of M and N.
The circuit configuration and its control become even more complex.

Therefore, the main object of the present invention is to provide a sample number conversion circuit that can arbitrarily set the values of M and N using a relatively simple single circuit.

To summarize the invention, in a circuit that converts a signal represented by a first sequence of M sample values S _I into a second sequence of N sample values S ^- _O , a binary signal representing a numerical value N is - The binary signal representing N is made negative, and the selection means selects either the binary signal of -N or the binary signal representing the numerical value M and supplies it to the adder circuit.
The adder circuit adds the selected signal and the numerical value stored in the temporary storage means and stores the result in the temporary storage means. Based on the contents stored in this temporary storage means, a read signal for reading out the next sample value signal in the first sample value series S _I stored in the first storage means is stored in the first storage means. The write signal for writing the next sample value signal in the second sample value series S ^- _O is generated and applied to the second storage means.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of a sample number conversion circuit according to the present invention. As shown in the figure, the number N
The binary signal representing
is converted into a binary signal and becomes one input of the selection circuit 32, and a binary signal representing the numerical value M is input to the other input. According to the output signal SG of the register 34, one of the binary signals is outputted from the selection circuit 32 and becomes one input B of the addition circuit 33. The adder circuit 33 performs binary addition of both the input signals A and B, and the sum is output and becomes the input to the register 34 . In register 34, the strobe pulse
The input value is transmitted to the output side by ST, and this becomes the A input of the adder circuit 33. The signal SG of the highest digit MSB of the binary signal output of the register 34 is a sign bit that is 0 when the output value is positive or zero and 1 when it is negative, and this signal SG is given to the selection circuit 32. , the binary signal -N is output from the selection circuit 32 when it is 0, and the binary signal M is output when it is 1. With the above-described configuration, the selection circuit 32 and the addition circuit 3
3. In the register 34, a change in input and output occurs immediately after the application of the strobe pulse ST.

The sequence control circuit 35 generates the strobe pulse ST, a pulse SF indicating a request for the next sample value of the sample value series S _I before conversion, and a pulse indicating addition of a sample value to the sample value series S ^- _O after conversion. This is a circuit that generates SM, and is a sequential circuit with a general configuration. The status register 61 updates the status of the sequential circuit by transmitting the input to the output side using the clock CK.
The output serves as the address input for the ROM62. The ROM 62 stores the output of the sequential circuit in each state and instructions regarding determination of the next state as a program, and outputs the output in accordance with the address input.
A part of the output of the ROM 62 is sent to the state determination logic circuit 63.
The next state to be taken, such as conditional branching, is determined by combining with external input. ROM
The other part of the output of 62 is input to an output logic circuit 64, which generates an output of the required pulses and levels, such as by conditionally gating the clock CK.
In addition to the output signal SG of the register 34, external inputs include instructions to start and end conversion (not shown), and outputs include, in addition to the three types of pulses mentioned above, a pulse CL for resetting the register 34, etc. There is. Pulse SF corresponds to the count pulse of the address counter in Figures 1 and 2, and pulse SM
corresponds to the resampling pulse.

The pulse SF is given to the address counter 41 to count up the address, and the address output of the address counter 41 causes the S _I memory 42 to be counted up.
address is specified. This S _I memory 42 stores the sample value series S _I before conversion. Further, the pulse SM is applied to the address counter 43 to count up the address, and the address of the S ^- _O memory 44 is designated by the address of the address counter 43 being output. This S ^- _p memory 44 stores the sample value sequence S ^- _O after conversion.

FIG. 4 shows a specific circuit example of the negative circuit 31 in FIG. 3, and includes an addition circuit 40 and negation circuits 41 to 44. In this example, the 4-digit 2
The base number N is also converted to a 4-digit binary number -N. Since one input value of the adder circuit 40 is N and the other input value is -1, the output value of the adder circuit 40 is N-1, and the values of all digits are logically inverted by the NOT circuits 41 to 44. Because -(N-1)
A binary signal representing -1=-N is obtained. The other building blocks of FIG. 3 can be easily implemented with corresponding logic integrated circuit elements.

FIG. 5 is a diagram showing an example of sample number conversion by the sample number conversion circuit as shown in FIG. 3. Particularly, FIG. FIG. 5b is a diagram showing the relationship between the sample value series S _I and S ^- _O before and after conversion.
This example shows a case where M is 7 and N is 4 (M>N).

Since the register 34 is reset before the conversion starts (step 0), the output value A of the register 34 is 0.
Therefore, the signal SG of the largest digit also becomes 0, so the selection circuit 32 selects -N and the numerical value of the output B becomes -4.
Therefore, the output of the adder circuit 33 also becomes a numerical value of -4. Since the signal SG is 0, in step 1, the pulse SF is output simultaneously with the strobe pulse ST. As a result, the first sample value 0 of the sample value series S _I before conversion is obtained. Furthermore, in step 1, the output value -4 of the adder circuit 33 in step 0 is transmitted to the output of the register 34, and the maximum digit signal SG
changes to 1. As a result, the selection circuit 32 selects the numerical value M and reaches the addition circuit 33, and the output value of the addition circuit becomes 7-4=3. In the next step 2, since the signal SG is 1, a resampling pulse SM is generated simultaneously with the strobe pulse ST. As a result, the first sample value obtained from the sample value series S _I becomes 1 of the sample value series S ^- _O after conversion.
Output as the th sample value. After the pulse is generated, the output value of the register 34 is 3, the signal SG is 0,
The output value of the selection circuit 32 is -4, and the addition circuit 3
The output value of 3 is -1. Therefore, in the next step 3, strobe pulse ST and pulse SF are generated simultaneously, and the second sample value 0 is obtained from the sample value series S _I before conversion. Similarly, at each step, pulse SF or resampling pulse is applied simultaneously with strobe pulse ST according to signal SG.
SM is generated. That is, if the output value A of the register 34 is positive or zero in the previous step, strobe pulse ST and pulse SF are generated in the next step, and the sum of A and -N is calculated. Pulse ST and resample pulse
SM is generated and the sum of A and M is calculated. In this way, the above process is repeated until the resampling pulse SM is generated N times, that is, until the number of samples of the converted sample value sequence S ^- _O reaches N.
As a result, as shown in Figure 5b, the sample value series S _I
4 sample values are selected and output from the 7 sample values of
A sample value sequence S ^- _O is formed.

Figure 6 is another example of sample number conversion using the sample number conversion circuit as shown in Figure 3, where M is 5 and N is 8 (M<N).
The case is shown below. In the same way as in Fig. 5, the sixth
Figure 6a shows changes in the main input and output signals of the conversion circuit for each strobe pulse ST, and Figure 6b shows the relationship between the sample value series S _I and S ^- _O before and after conversion. Similar to the circuit operation in FIG. 5, if the output value A of the register 34 is positive or zero in the previous step, strobe pulse ST and pulse SF are generated in the next step, and the sum of A and -N is If not, a strobe pulse ST and a resample pulse SM are generated to calculate the sum of A and M. Since N is larger than M at this time, steps for generating resampling pulses SM may occur successively. As a result, as shown in Figure 6b, the sample value series before conversion is
Some of the sample values in S _I are repeatedly output to form the converted sample value sequence S ^- _O. and,
The conversion ends when the number of samples after conversion reaches N.

In the previous example, the register 34 was reset before starting the sample number conversion, but
If a positive integer value less than or equal to M is preset in the register 34, different sample values are selected from the sample value series S _I to form the sample value series S' ^- _O.

FIG. 7 shows an example of such sample number conversion. Similarly to the case of FIG. 5, FIG. 7a shows changes in the main input and output signals of the conversion circuit for each strobe pulse ST, and Figure 7b shows the sample value series before and after conversion.
The relationship between S _I and S′ ^- _O is shown. M and N are the same numbers 7 and 4 as in the case of FIG.

At the start of conversion, when the register 34 is reset by the pulse CL and the strobe pulse ST is generated by temporarily setting the value of N to -6, the value 6 is stored in the register 34 via the selection circuit 32 and the addition circuit 33. Preset. If this is the initial state, M and N are set to 7 and 4, respectively, and the same sequence control as in the case of Fig. 5 is performed, each step becomes as shown in Fig. 7a, and as a result of sample number conversion, As shown in Figure 7b, the sample value sequence S' ^- _O after conversion is obtained from the sample value sequence S _I before conversion.
The converted sequence S' ^- _O is the converted system example S ^- _O in Figure 5b.
Although the number of samples is the same, the contents are different. This means that a sampled value sequence with a different sampling phase relative to the original signal has been obtained. In other words, by changing the numerical value preset in the register 34, the sampling phase can be selected.

As can be seen from the above explanation, in the sample number conversion circuit shown in Figure 3, the values of M and N can be arbitrarily selected, and the number of samples can be changed from M to M using the same sequence control method regardless of the relationship between the two. It is possible to convert to N. In the embodiment, in order to simplify the explanation, the values of M and N are small positive integers. Needless to say, this problem can be solved by increasing the number of digits in base number processing. In addition, in the example, the sample value is binary (0
However, even in the case of a multivalued signal consisting of a plurality of bits, similar sample number conversion is possible by processing the plurality of bits in parallel. Furthermore, by selecting a numerical value to be preset in the register 34, the sampling phase of the converted sample value series relative to the original signal can be selected.

As described above, according to the present invention, since the sample number conversion circuit is configured with a negative circuit, a selection circuit, an addition circuit, a register, and a sequence control circuit, the number of samples of the sample value series before and after conversion can be set arbitrarily. It is possible to realize a relatively simple circuit that can be selected as the desired one and convert the number of samples using a similar control method, and to obtain a useful means for processing such as time compression and expansion of signals or reduction and expansion of images. .

[Brief explanation of drawings]

1 and 2 show examples of conventional sample number conversion circuits, with FIG. 1 showing a case where the number of samples is decreased, and FIG. 2 showing a case where the number of samples is increased. FIG. 3 is a block diagram showing the configuration of a sample number conversion circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing a specific example of a negative conversion circuit. Figures 5 and 6
FIG. 7 and FIG. 7 are diagrams showing an example of sample number conversion by a sample number conversion circuit according to an embodiment of the present invention. In the figure, 31 is a negative circuit, 32 is a selection circuit, 33 is an addition circuit, 34 is a register, and 35 is a sequence control circuit.

Claims (1)

[Claims] 1. In a sample number conversion circuit that converts a signal represented by M first sample value series into N second sample value series, an input signal is transferred to the output side according to a write signal. temporary storage means for converting a binary signal representing a numerical value N into a binary signal representing a negative numerical value -N; Selection means for selecting and outputting at least one of an output signal and a binary signal representing the numerical value M; adding the signal selected by the selection means and the output code signal of the temporary storage means; addition means for supplying the temporary storage means as an input signal; first storage means for storing the first sample value series; second storage means for storing the second sample value series; generating a write signal to be applied to the storage means, and reading out the next sample value signal in the first sample value series from the first storage means in accordance with the output code signal of the temporary storage means; A sample number conversion circuit comprising sequence control means for generating a read signal and a write signal for writing a next sample value signal in the second sample value series into the second storage means.