JPS6132867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides compressed data that reduces the restoration processing time by providing a shift register with a ^2n- bit shift function for restoring image data from equal length run lengths of compressed data. This relates to a restoration circuit.

Conventionally, in one-dimensional or two-dimensional encoding methods, in order to convert equal-length run lengths obtained from compressed data (hereinafter simply referred to as equal-length run lengths) into actual image data, a corresponding black-and-white encoder is used as a restoration circuit. Since the bits were shifted one by one according to the mode, the shifting operation took time.

FIG. 1 shows an example of a conventional restoration circuit. first,
The equal length run length is stored in the RL latch circuit 14, and the RL counter 16 is cleared.
Next, specify the black and white mode of the run length using the flip-flop 10, fill the shift register 11 with “0” and “1” corresponding to black or white, and then input the image data. Restore. The next decoding scanning line memory 12 is a buffer that stores the restored contents of the shift register 11 for one line or more. The number of bits in the shift register 11 is set to be the same as the number of bits in one word of the decoding scanning line memory 12.

The shift number counter 13 counts the number of shifts in the shift register 11, and when the shift register 11 is full, the control pulse generation circuit 17
The control pulse generating circuit 17 decodes the contents of the shift register 11 and sends a control signal to the scanning line memory 12.
write to. When writing to the decoding scanning line memory 12 is completed, the shift number counter 13 is cleared. Then, the shift register 11 starts shifting again, and the shift number counter 13 repeats the procedure of counting the number of shifts. Also, RL counter 1
6 counts the number of bits of the run length restored by the shift register 11, and when this count matches the contents of the RL latch circuit 14, the restoration of one equal length run length is completed.

As explained above, the conventional restoration circuit has the disadvantage that it takes too much time to restore image data because it shifts one bit at a time.

An object of the present invention is to provide a compressed data restoration circuit that reduces the processing time for restoring image data from equal length run lengths of compressed data.

To achieve the above object, the compressed data restoration circuit of the present invention comprises a shift register for restoring and shifting band-compressed image data, and a decoding scan line memory for storing one or more lines of the contents of the shift register. In the data restoration circuit, a shift register capable of shifting every 2 ⁿ bits and a shift every 1 bit determined in advance is used, and when the bit length of the run length to be restored of image data is 2 ⁿ bits or more, the shift register is used. When the bit length of the run length is less than 2 ⁿ bits, the image data is shifted by 1 bit, and when ^the shift register is full of image data, it is controlled to be written to the decoding scanning line memory. It is characterized by comprising means.

The present invention will be described in detail below with reference to examples.

FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention.

In the same figure, flip-flop (FF) 10
stores whether the run length to be restored is white or black, and specifies the corresponding "0" or "1" to the shift register 21.

The shift register 21, as shown in a detailed circuit example in Fig. 3, serially inputs the output of the FF10 to the first stage shift register (SR) 21-1, and shifts it one bit at a time to each stage SR21-2 to SR21-4. function, and SR21 with 2 bits each with parallel input.
-2 to 21-4. This function uses a 1-bit shift signal 31 or a 2-bit shift signal 32 from the control pulse generation circuit 24, which will be described later.
selected by. Furthermore, these signals 31,
32 is synchronized with a predetermined clock through an AND circuit to create a shift clock, a shift operation is performed, and the output is sent to the decoding scanning line memory 12 as a 1-bit or 2-bit output.

Returning to FIG. 2, the shift number counting circuit 22 counts the number of shifts in the shift register 21, and the RL counting circuit 23 counts the number of bits of the restored run length. These counting circuits 22 and 23 have a flip-flop (FF) 22 which is the least significant digit (LSB).
-1, 23-1 and its upper digit counter 22-
It consists of 2, 23-2. With this configuration,
If a constant clock is input to the FFs 22-1, 23-1 and the counters 22-2, 23-2 at the same time, it will count one by one, and if the clock is input only to the counters 22-2, 23-2, it will count two each.
Further, it can be determined whether the value is an odd number or an even number depending on the contents of FF22-1 and FF23-1. The RL latch circuit 14 stores the equal length run length, and the comparison circuit 1
5 compares the contents with the RL counting circuit 23 and outputs a matching signal. The control pulse generation circuit 24 receives the outputs of the FF 22-1 and the counter 22-2 of the shift counting circuit 22, that is, 1 bit count or 2 bits.
The count value of the bit count and the match signal of the comparator circuit 15, that is, the end signal of the run length, are input, the 1-bit shift signal 31 and the 2-bit shift signal 32 are sent to the shift register 21, and the write signal is sent to the decoding scanning line memory 12. Send 33,
Performs necessary controls to restore image data.

The operation of the above-mentioned configuration will be explained below.

First, the run length is stored in the RL latch circuit 14, and the counter 23-2 and FF 23-1 are cleared. Next, the comparison circuit 15 compares the value of the contents of the RL latch circuit 14 excluding the LSB and the counter 23 -
Compare the values of 2.

If the value excluding the LSB of the RL latch circuit 14 and the value of the counter 23-2 do not match, the 2-bit shift signal 32 is output until these values match. This 2-bit signal is used to shift and fill the shift register 21 by 2 bits in accordance with the monochrome mode of the FF 10, and at the same time, the number of shifts of these 2 bits is counted by counters 22-2 and 23-2. At this time, shift register 2
1 restores the image data by shifting it two bits at a time using parallel input through the wiring shown in FIG. 3, and the counting circuits 22 and 23 count two bits at a time.

If the value of the shift number counting circuit 22 becomes one less than the number of bits of the shift register 21,
Next, the control pulse generating circuit 24 outputs a 1-bit shift signal 31. Using this 1-bit shift signal 31, the shift register 21 uses the serial input to shift and restore the image data by 1 bit.
Count 1 including 3-1. As a result, the value of the shift number counting circuit 22 matches the value of the shift register 21.

If the value of the shift number counting circuit 22 reaches the number of bits of the shift register 21, then the control pulse generation circuit 24 outputs a write signal 33 to the restored scanning line memory 12 to write the contents of the shift register 21. . Next, after writing is completed, counter 22-2 and
Clear FF22-1 and repeat the action from the beginning.

Then, when the value excluding the LSB of the RL latch circuit 14 and the value of the counter 23-2 match, the LSB of the RL latch circuit 14 and the value of FF23-1 are compared, and if both match, the run length is restored. finish. If they do not match, the control pulse generation circuit 24 outputs a 1-bit shift signal 31,
The shift register 21 is shifted by one bit, and the counting circuits 22 and 23 count the number of shifts by one. By this 1-bit shift, the above-mentioned values match, and the restoration of the run length is completed.

Compared to conventional restoration circuits, the embodiment of the present invention only separates the counting circuit into a flip-flop and a counter.

Usually, most images have a run length of 2 or more, so data restoration processing can be performed about twice as fast as conventional circuits. In the embodiment, the shift is made every 2 bits, but generally it can be set to 2 ⁿ bits.

Note that in this example, the equal length run length obtained by one-dimensional encoding or two-dimensional encoding is restored, but instead of this equal length run length, changes made to the pixels of the scanning line are used. It may also be restored using the address of the point.

As explained above, according to the present invention, the shift register for restoring image data from equal-length run lengths of compressed data is provided with a ^2n- bit and 1-bit shift function, thereby performing restoration processing. As mentioned above, the speed can be increased to about twice.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a conventional example, FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a detailed circuit example of the main part of the embodiment of FIG. is a flip-flop, 12 is a decoding scanning line memory, and 14 is a flip-flop.
RL latch circuit, 15 is a comparison circuit, 21 is a shift register, 22 is a shift number counting circuit, 23 is RL
22-1 and 23-1 are flip-flops, 22-2 and 23-2 are counters, and 24 is a control pulse generation circuit.

Claims (1)

[Claims] 1. In a compressed data restoration circuit that includes a shift register that restores and shifts band-compressed image data and a decoding scanning line memory that stores one or more lines of the contents of the shift register, a predetermined shift every 2 ⁿ bits is performed. When the bit length of the run length to be restored of the image data is 2 n bits or more, the shift register is shifted by 2 ⁿ bits, and the bit length of the run length is 2 ⁿ bits or more. Compressed data restoration characterized by comprising means for controlling to shift one bit at a time when the image data is ⁿ bits or less, and to write the image data to the decoding scanning line memory when the shift register is full. circuit.