JPH0119671B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for bus transmission in an information processing system.

There is bus transmission for transmitting and receiving information signals between multiple devices or circuit groups in an information processing system, and as shown in FIG.
RV2a are connected as a set, and multiple devices 1
Common transmission cable 3 between 0a to 0d
Send and receive signals via.

Therefore, when the DV1a of the device 10a operates to send a signal, RV2b to d operate in the other devices 10b to d excluding the own device 10a, and at the next timing, for example, the other RV2a except for the DV1b and RV2b operate. , c, and d operate and are connected by the same transmission cable 3, the drive circuit
Control is performed so that two or more DVa to d do not become active and interfere with each other at the same timing.

Further, the drive circuit DV1a in the devices 10a to 10d
The outputs of ~d are always accompanied by deviations and fluctuations in both the output voltage and timing. Other drive circuits DV1a~
Although d is constituted by a semiconductor element that performs a switching operation in accordance with a control signal, there is always a delay in the switching operation. For example, an output stop operation in switching of a semiconductor device has a falling time and a stop because the base size is finite in the structure of the semiconductor device, even though the accumulation time can be ignored due to non-saturation operation as is well known. A finite turn-off time is required from the time the semiconductor element receives control until the output of the semiconductor element is sufficiently terminated.

For this reason, when switching between transmitting and receiving operations in conventional bus transmission, both the driving operation and receiving operation (=driving operation from another) are stopped, and the transmission bus has a high impedance ( Control is performed to insert no-signal timing (HIZ). Although this method eliminates interference, it has the disadvantage that unnecessary timing for signal transmission increases, resulting in a longer transmission time.

The present invention provides a means to eliminate this drawback. For this reason, the present invention provides means for generating a clock that precedes a reference clock and a clock that lags behind a reference clock in a bus transmission drive circuit that transmits and receives signals by mutually switching between a driving operation and a receiving operation. When transferring from reception to driving by sending a signal by logical product, driving is delayed, when transferring from driving to receiving, driving is cut off first, and when driving continues, driving is continued. It is characterized by eliminating and reducing the non-signal timing that is HIZ that was conventionally transmitted, and shortening the transmission time of the information signal.

By sending a signal by ANDing with the delay clock, the drive is delayed when transitioning from reception to drive, the advance cutoff of the drive is performed when transition from drive to reception, and the pre-cutoff is performed when the drive is continuous. In the past, we were able to achieve continuous drive and send out signals.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of a driving circuit according to one embodiment of the present invention. 11 is a clock generation circuit, 1
2, 13, and 14 are latches, 15 is a control data register, 16 is a transmission data register, 17 is an output circuit with a gate, and AND is an AND circuit. Further, CLK _{0 to 3} and D _{0 to 4} indicate signals between each functional circuit, and correspond to the symbol names of the time chart in FIG. 3.

Although not shown in FIG. 2, the clock generation circuit 11, control data register 15, and transmission data register 16 operate according to control signals from the main control circuit. The clock generation circuit 11 is a reference clock.
CLK ₀ is sent to latch 14, a clock CLK ₁ that leads the reference clock is sent to latch 12, and a clock CLK ₂ that lags the reference clock is sent to latch 13. The control data register 15 latches pre-stored transmission and reception switching control data _D0 to the latch 12,
Send on 13th. For example, if the signal "1" is the transmission and the signal "0" is the reception, in FIG. 3, the clock is used as a unit for transmission, reception, transmission, transmission, and reception from _T1 . D ₀ is input to the enable terminals of latches 12 and 13, respectively, and is triggered each time by the trailing edge of previous CLK ₁ and CLK ₂ , so that latch 12 outputs D ₁
, the latch 13 outputs D ₂ respectively. Similarly, the signal from transmit data register 16 is output by latch ₁₄ as signal D3.

Here, the signals D ₁ and D ₂ are input to AND, and D ₁ and D ₂
The logical product D ₄ is output. D ₃ output from latch 14 is input to output circuit 17, but AND
Therefore, only the portion gated by D ₄ and logically ANDed with D ₄ is output by the output circuit 17 as a predetermined output pulse. The temporal representation of the output signal is
Matches D ₄ .

Since the signal output by this drive circuit has a no-signal portion that is at the required HIZ at both the leading and trailing edges of the output signal with respect to the reference clock, each DV
When applied to 1a to 1d, the no-signal timing that was conventionally inserted between the drive and reception timings when switching between transmission and reception operations becomes unnecessary, and there is no interference between transmission and reception switching. Furthermore, since the number of no-signal timings is reduced compared to the conventional method, transmission time is shortened and bus transmission efficiency is increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of bus transmission in a conventional system and an embodiment of the present invention, FIG. 2 is a block diagram of a drive circuit in an embodiment of the present invention, and FIG. 3 is a block diagram of a drive circuit in an embodiment of the present invention. This is an operation time chart.

Claims (1)

[Scope of Claims] 1. In a bus transmission drive circuit that transmits and receives data signals by mutually switching drive operation and reception operation using a control signal, means for generating a clock that precedes a reference clock and a clock that lags behind a reference clock; means for latching the control signal according to the preceding clock, the delayed clock, and the reference clock, respectively; an AND gate for outputting the AND of the control signal latched by the preceding clock and the delayed clock; and the reference. A bus driving circuit comprising: an output circuit that outputs the data signal latched by a clock only during a period when the AND gate output is obtained.