JPH0120752B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a display device using a display element such as a light emitting diode, and more particularly to a display device that connects small unit display devices to project television images on a large screen. It is something.

[Technical background of the invention and its problems]

A display device consisting of display elements such as light emitting diodes (LEDs) arranged in a matrix is
Compared to display devices using cathode ray tubes, it is advantageous in that it can be made smaller and thinner, can operate at lower voltages, and can also produce large screen areas exceeding 1 m x 1 m.

Conventionally, as a driving method for such a display device in which display elements are arranged in a matrix, a line sequential scanning method, which is a composite method that takes advantage of the advantages of both a dynamic method and a static method, has been mainly used. Simply put, this method converts the drive signal applied to the row lines of the display element array into a timetable, sequentially scans and drives the row lines, and synchronizes with this by applying a binary level of "1" or "0" to the column lines. This is to selectively switch image data.

However, with this line sequential scanning method, for example, the 64 x 64 pixel multicolor LED display device described in "Electronic Materials" February 1980 issue, pages 68 to 72,
“IEEE TRANSACTION ON ELECTRON
DEVICES” VOL・ED−26, No.68, AUGUST
As seen in the 96 x 64 pixel and 160 x 112 pixel television scanning matrix display devices described in 1979, pp. 1182-1186, as the screen size, or number of pixels, increases, so does the drive of this type of display device. Due to the limitations of the image data processing speed of external equipment, it is difficult to scan at a repetition rate that does not cause flickering to the human eye. Furthermore, the current that momentarily flows through the display element array is determined by the number of pixel data applied to the column lines, and a large current flows through the row lines that receive this data.
Miniaturization of this type of flat display device, IC
Features such as bondability with Furthermore, this is disadvantageous in terms of increasing display brightness.

Therefore, conventionally, when creating a large screen display device with an extremely large number of pixels, for example, "CONFERENCE RECORD OF 1978
BIENNIAL DISPLAY RESEACH
CONFERENCE” OCTOBER 24-26, 1978,
FLAT-PANEL DISPLAY listed in SID P20~21
A method has been considered in which a large number of small unit display devices each having a driving circuit on the back side of a substrate are connected together. The drive circuit attached to the above-mentioned unit display device is equipped with a number of memory elements corresponding to the number of pixels in the display element array of this unit display device, and independently controls the display element array in each unit display device. Since it can be driven, it is suitable for the response characteristics of the LED mentioned above, and can be easily integrated into an IC.

A large-scale display device in which a large screen is constructed by connecting such small-sized unit display devices can be schematically represented as shown in FIG. That is, 1 has a plurality of monolithic or hybrid structures constituting a given pixel on the substrate.
As a display section with LEDs arranged in a matrix
The LED array 2 is a module driver as a drive circuit that drives the LED array 1 using the line sequential scanning method.
A unit display device 3 is a unit display device 3 that integrates a module driver 2 with a display function. And this unit display device 3
A unit panel 4 is formed by arranging the units vertically and horizontally in a matrix to form a screen of a desired size.The unit driver 5 supplies various signals and power to the unit panel 4. - The display unit 6 is a combination of the panel 4 and the unit driver 5, which has one display function as a whole.

The inventors have already proposed a specific method for configuring the above-mentioned unit display device, especially the module driver therein (Japanese Patent Application No. 57-20113).
issue). This basic configuration uses an m×n stage static shift register for the number of pixels in each row and column direction of a display element array in a matrix arrangement as m and n as a storage circuit for image data, and the first m stages of the static shift register are The output drives the column lines of the display element array, and depending on the level of a binary select signal from the outside, it is possible to switch between inputting the image data to the shift register and circulating the shift register. On the other hand, scanning driving of the row lines of the display element array is performed based on the count of the clock signal.

By doing so, the circuit configuration of the module driver included in the unit display device can be simplified. The storage circuit for storing image data to be supplied to the display element array is mainly composed of shift registers, and pixel signals are taken in and read out only by switching the input of the shift register and shifting by a clock signal. This is because it can be done. Therefore, the power consumption of the module driver can be reduced, and
When this module driver is made into an IC, it is easy to incorporate it into the lower part of the substrate where the display element array is arranged.

Furthermore, when arranging such display devices as unit display devices in a matrix and configuring a large screen display device (display unit) as a unit panel,
The select signal line and clock signal line are arranged in the row and column directions of the unit panel, respectively.
By driving and controlling each unit display device as a whole in a manner similar to line sequential scanning using the supply pattern of select signals and clock signals supplied from the driver to these lines, the unit display device can be The ability to control the devices significantly reduces the number of wiring between the unit drivers and the individual unit display devices, and also makes the unit drivers simpler to configure. Therefore, it is possible to relatively easily realize an extremely large screen with several hundred unit display devices.

By the way, image data information sources for display devices with such large screen areas are generated from various terminal devices such as computers and TV signals, but scanning by a computer requires a huge amount of memory to secure the image data. Therefore, a television scanning system is advantageous because it can produce a large amount of information with a relatively simple circuit configuration. Normally, when giving a television image signal to a display device as a binary signal of "1" or "0", NTSC (National
In the Television System Committee system, image signals are processed using 525 horizontal synchronizing signals per frame and two vertical synchronizing signals per frame. In this case, image signal processing within the horizontal synchronization period can be solved by sampling at sampling intervals divided by the number of pixels in the horizontal direction of the display device, so the number of pixels in the horizontal direction of the display device is not particularly limited. However, the vertical pixel division is limited to 262.5 (525/2).

Therefore, for display devices in which the number of pixels in the vertical direction exceeds 262.5 horizontal scanning lines, it is necessary to scan multiple rows of pixels arranged in the horizontal direction at once, or to use the computer scanning method described above. This requires complex image processing, such as temporarily storing the image signal produced by the video circuit of a television receiver in memory, processing the data, and outputting it according to the number of pixels arranged vertically. This determines the effective pixel size for displaying television images on a display device using the above-mentioned display element array. In other words, the number of pixels in the vertical direction must be less than 262.5 of the number of horizontal scanning lines per field, the width-to-height ratio of a typical television screen is 4:3, and the effective image area is taken into account. It can be seen that the ideal maximum number of pixels is 320 horizontally and 240 vertically.

However, since a unit display device composed of a specific number of pixels operates independently, if such unit display devices are simply connected to form a display device with a large screen area, image display timing and brightness will be affected. It becomes difficult to match the balance etc. without any problems.

In other words, the image signal once stored in the shift register in the unit display device is circulated and output when the select signal commonly given to the unit display devices arranged horizontally (unit row) is not selected. ing. This display operation uses a clock signal that is commonly given to the vertically arranged unit display devices (unit row) to operate a counter synchronized with the movement of the shift register, so that a clock signal of m units is input n times. If the next vertical synchronizing signal appears and scanning of a new image signal begins before the image is detected, the internal counter will malfunction and a correct image cannot be produced. In addition, to prevent this, if the clock signal is stopped so that the horizontal synchronization signal is not output until the next vertical synchronization signal appears after completing n x N horizontal scans, the counter in the m x n unit display device During this period, the scanning line is stopped at the n-th scanning line, and the display operation is performed for a longer time than the other scanning lines, resulting in problems such as the brightness being different and good image quality not being obtained.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that can correctly display television images on a large-screen unit panel constructed by combining a large number of unit display devices each having a specific number of pixels.

[Summary of the invention]

A display device according to the present invention includes a display element array formed by connecting display elements with a specific number of pixels (m x n) in a matrix, and stages of the same number as the number of pixels (m x n) of this display element array, and receives a clock signal from an external source. A shift register that performs a shift operation by
receiving a select signal and image data from the outside, and inputting the image data to the shift register from the first stage when the select signal is at a first level;
a switching circuit that inputs the output of the last stage of the shift register to the first stage when the select signal is at a second level; and a switching circuit that amplifies the output of the first m stages of the shift register and supplies it to the column line of the display element array. means for sequentially selecting the row lines of the display element array every time m clock signals are input; and a brightness adjustment circuit for inhibiting selection of the row lines based on an external brightness adjustment signal. a unit panel formed by connecting unit display devices in N rows x M columns, each including a unit display device, and a unit panel that drives this unit panel to display a television image
Consists of a driver.

The unit driver includes means for binarizing valid image data within a horizontal synchronization period of the television image signal and commonly providing it to each unit display device of the unit panel, and a means for performing vertical and horizontal synchronization of the television image signal. Starting by applying signals simultaneously, the units
A clock signal generating means repeats the operation of sequentially outputting m clock signals to each column of the panel with a predetermined pause period every time a horizontal synchronizing signal arrives;
a select signal generating means for sequentially outputting a select signal to each row of the unit panel at the timing of a horizontal synchronization signal every time n clock signals are output; and common to each unit display device during the rest period of the clock signal. a brightness adjustment signal generating means for outputting a brightness adjustment signal; and a clock signal generating means for a period after all unit display devices of the unit panel are driven by the clock signal and the select signal until the arrival of the next vertical synchronization signal. and means for simultaneously stopping the output of the clock signal and superimposing a display blanking pulse on the output of the brightness adjustment signal generating means.

That is, according to the present invention, the effective image data within the period of the horizontal synchronizing signal given to the number of pixels (m×M) lined up horizontally on the unit panel is
It is sampled while switching times.

In this operation, first, when the vertical and horizontal synchronizing signals of the television image signal are simultaneously received, a select signal is applied to the first unit row, and the first row of n stages therein is selected. Further, with the next horizontal synchronizing signal, the scanning is switched to the second row and then to the third row, and n rows are scanned. When the scanning of n rows is completed, the horizontal synchronization signal switches the pixel columns, and at the same time the select signal for selecting the unit column is transferred to the second unit column, which is then sequentially switched to the pixel column.
Scan twice. Then, until the next vertical synchronization signal appears, the image data in the 262.5 horizontal synchronization signals are written to each unit display device.

In this case, the number of pixels in the vertical direction of the unit panel is n×N.
If you choose a positive value that does not exceed 262.5 lines, horizontal synchronization signals of 0.5 lines or more will become odd. Therefore, during the period from the completion of n x N horizontal scans until the appearance of the next vertical synchronizing signal, a blanking pulse is generated that stops the clock signal and at the same time inhibits the display operation, and each unit display of the unit panel It is applied to the brightness adjustment circuit of the device to drive and control it.

〔Effect of the invention〕

According to this invention, if the number of times to scan the product n×N of the number of vertical pixels of a unit display device n and the number of vertical unit columns N is a number that does not exceed the number of horizontal synchronization signals, an extremely simple image can be obtained. Television images can be created using processing circuits.

Further, even in a display unit in which a large number of unit display devices capable of displaying on their own are combined, a television image can be displayed without blurring the image or destroying the balance of brightness.

[Embodiments of the invention]

Figures 2 to 4 show the configuration of a unit display device and its time chart according to the present invention, and an LED array 1 as a display element array has m (row direction) x n (column direction) LEDs. They are arranged in a matrix and connected to each intersection of m row lines and n column lines. Here, m・n
The value of is, for example, m=n=16. LED array 1
are configured on one substrate, for example. A module driver 2 for driving the LED array 1 is provided at the bottom of this board. This module driver 2 is configured as follows.

That is, the module driver 2 receives a select signal S, serial image data D, clock signal C,
A reset signal R, a brightness modulation signal B, and an enable signal E are input from the outside. Among these signals, select signal S, serial image data D
is input to a switching circuit 10 obtained by a configuration including an AND gate 11, an inverter 12, an AND gate 13, an OR gate 14, and the like. In this switching circuit 10, the level of the select signal S is S="1"
When S=0, the image data D is input to the shift register 15 from the first stage, and when S="0", the output from the last stage of the shift register 15 is input to the first stage.

The shift register 15 is an m×n stage static shift register, in other words, m stages are divided into 1
One block consists of n blocks B ₁ to Bn. The first block of this shift register 15
B ₁ , that is, the outputs from the first stage to the mth stage, are applied to the row lines in the LED array 1 via a first drive circuit 18 consisting of m amplifiers that amplify the currents of these outputs.

On the other hand, the clock signal C is applied to the shift register 15 and is also input to the bit counter 21. Bit counter 21 and address
The counter 22 is set to an initial state by a reset signal R, and outputs a carry signal CA every time m=16 clock signals C are counted. It should be noted that the clock signal C has an idle period of about 10 to 100 times its period between the K.mth clock and the K.m+1th clock.
The address counter 22 uses this carry signal CA.
In response to this, address signals specifying column lines in the LED array 1 are sequentially output to the decoder 17.

A brightness adjustment circuit 30 composed of AND gates 31, 32 and an OR gate 33 is further provided within the unit display manufacturing unit, and a brightness adjustment circuit 30 is provided as an input signal for controlling the brightness adjustment operation based on the brightness adjustment signal B. An enable signal E is prepared. In this case, the brightness adjustment signal B is a pulse-like signal whose width can be modulated arbitrarily between the 1st and 15th cycles of the clock signal given during the rest period for every m=16 clock signals C. It will be done.

The time chart in Figure 4 shows the situation. This brightness adjustment signal B is input to the first AND gate 31. On the other hand, the bit counter 21 outputs a carry signal CA that becomes low level when all of its A, B, C, and D outputs are high level, and the second
It is input to AND gate 32 and address counter 22. Brightness adjustment signal B and carry signal CA
When the enable signal E is at a high level, the signals pass through AND gates 31 and 32 and are combined by an OR gate 33 to become a luminance enable signal BE. This brightness enable signal BE is given to the decoder 17,
When BE is at a high level, the scanning signal output from the decoder is prohibited and the lighting operation of the LED array 1 is stopped. This stop time corresponds to the pulse width of the brightness adjustment signal B, and therefore, the display brightness of the LED array 1 can be adjusted by this pulse width. Note that when the enable signal E is at a low level, the brightness adjustment signal B and the carry signal CA are ignored by the brightness adjustment circuit 30, so that no brightness adjustment is performed.

The unit panel 4 shown in FIG. 5 is constructed by arranging the unit display devices 3 shown in FIG. 2 in a matrix on, for example, a single printed circuit board. Here, the number of rows of the unit display device 3 is assumed to be M, and the number of columns arranged is N. However, unlike FIG. 3, FIG. 5 uses rows in the horizontal direction and columns in the vertical direction. This unit panel 4 receives from the unit driver 5 image data D, a reset signal R, a brightness adjustment signal B, an enable signal E, which is commonly given to all the unit display devices 3, and a select signal which is commonly given to the unit rows. Signals S1 to S _N and clock signals C1 to C _M commonly applied to the unit arrays are supplied.

FIG. 6 explains this unit driver 5 in more detail, and includes a well-known NTSC video signal processing circuit section 51 and this video signal processing circuit 51.
The control circuit section 52 receives the image data DA, horizontal synchronization signal H, and vertical synchronization signal V obtained from the above, and generates each signal to be applied to the above-mentioned unit panel 4. The video signal processing circuit section 51 includes a tuner 510, an intermediate frequency amplification circuit 511, an audio detection amplification circuit 512, a speaker 513, a video intermediate detection circuit 514, and a video circuit 51.
5. It is a general circuit including a color circuit 516, a synchronous separation/frequency division circuit 517, vertical and horizontal oscillation circuits 518 and 519, and the like.

Below, regarding the configuration and operation of Fig. 6, Fig. 7,
This will be explained with reference to FIG. First, in the video signal processing circuit section 51, the composite synchronization signal obtained by the synchronization separation frequency division circuit 517 is sent to the vertical oscillation circuit 518 and the horizontal oscillation circuit 519, and the vertical synchronization signal V,
A horizontal synchronization signal H is produced. On the other hand, the image data DA is processed by the video circuit 515 and the color circuit 516.
is obtained.

Next, in the control circuit unit 52, first, the image data DA is sent to a binarization circuit 525 whose threshold value is randomly modulated by a threshold modulation circuit 524.
This results in image data D having halftones converted as a binary signal of "1" or "0". Such binarization processing is called the Taser method.
On the other hand, the timing circuit 521 captures the synchronization pulse signals of the vertical synchronization signal V and the horizontal synchronization signal H, and generates a vertical synchronization pulse signal having a predetermined width.
VP and horizontal synchronization pulse signal HP are counter 7
The vertical synchronizing pulse signal VP is applied to a counter 74, a decoder 75, and a blanking circuit 75, and serves to reset the internal information of each circuit and return it to the base point. The original clock signal CK from the oscillator 70 is sent to the counter 72 and M number of AND gates 80 through the inverter 77 and the AND gate 71 when the output BR of the blanking circuit 76 is at the "0" level. Then, a count signal CT generated from the counter 72 every m clock counts is sent to the decoder 7.
3 and an AND gate 80 which ANDs the output of this decoder 73 and the clock signal CK.
The clock signals C1, C2, C3, . . . CM are sequentially output.

The frequency of the oscillator 70 is a speed at which the effective image data D included in 53 μs, which is approximately 84% of the effective scanning line length within the horizontal scanning period of 63.5 μs, is sampled.
For example, the number of pixels on the side of the unit panel is 320 mm.
In this case, it is approximately 6MHz. Then, the decoder 73 outputs one carry signal CY every time M scans are completed, and this carry signal CY is sent to the counter 74.

The counter 74 sends an output signal to the decoder 75 every n counts of the carry signal CY, and the decoder 75 generates select signals S1 to S _N.
Furthermore, one output signal indicating the end of the select signal S _N is given to the blanking circuit 76 to generate the blanking signal BR. This blanking signal
As mentioned above, BR is held until the blanking circuit 76 is reset by the vertical synchronizing pulse signal VP, and when n・N is 240, the horizontal value remaining after one field scan after the end of the select signal S _N Generation of the select signal is prohibited for a period of 22.5 synchronization signals H.

On the other hand, an output signal synchronized with the clock signal CK is sent from the counter 72 to a brightness adjustment signal generation circuit 78, and when m=16, a brightness adjustment signal BY whose pulse width is variable in a width of 1 to 15 clock cycles is generated. Then, the brightness adjustment signal BY and the blanking signal BR are combined by an OR gate 79 to form the final brightness adjustment signal B.

In addition, the unit driver 5 includes a refresh circuit 526 and an enable control 527, as described above, to provide more versatility.

The reset signal R may be set to an automatic reset circuit that maintains the level "1" for a suitable period of time after the power is turned on, or a vertical synchronizing signal may be used.

On the other hand, the enable signal may be generated by an external device if a switch is used to set the level to "1" or "0" or a light pen input means is used.

Furthermore, it goes without saying that the AND gates, OR gates, etc. used in each circuit may be replaced by NAND gates or other gates as long as the functions can be obtained.

[Brief explanation of drawings]

FIGS. 1a and 1b are diagrams schematically showing the basic configuration of a unit display device and a display unit constructed by arranging them in a matrix, and FIGS. 2 and 3 are diagrams showing the basic structure of a unit display device used in this invention. Figure 4 is a time chart showing its operation, and Figure 5 schematically shows the configuration of a unit panel consisting of M/N unit display devices and a unit driver of its drive circuit. 6 is a configuration diagram showing an embodiment of the present invention, FIG. 7 is a time chart showing the operation of the horizontal synchronization signal and vertical synchronization signal of the TV signal, and FIG. This is an operation time chart showing the correspondence between image data and clock pulses. 1...LED array (light emitting element array), 2...
Module driver, 3...Unit display device, 4...Unit panel, 5...Unit driver, 6...Display unit (display device), 10...Switching circuit, 15...
...Shift register, 17,73,75...Decoder, 18,19...Current amplifier circuit, 21,2
2, 72, 74...Counter, 70...Clock signal generation circuit (oscillator), 76...Blanging pulse generation circuit, 78...Brightness adjustment circuit, 7
9... Luminance signal synthesis circuit, D... Image data, R
...Reset signal, B...Brightness modulation signal, E...
Enable signal, C, C1 to C _M ...Clock signal, S, S1 to S _N ...Select signal, H...Horizontal synchronization signal, V...Vertical synchronization signal.

Claims (1)

[Claims] 1. A display element array formed by connecting display elements with a specific number of pixels (m x n) in a matrix, and a shift register consisting of the same number of stages as the number of pixels (m x n) of this display element array, which is operated by a clock signal from an external source. , receives a select signal and image data from the outside, inputs the image data into the shift register from the first stage when the select signal is at a first level, and outputs the final stage of the shift register when the select signal is at a second level. a switching circuit for inputting the clock signal to the first stage; a means for current amplifying the output of the first m stages of the shift register and supplying it to the column line of the display element array; A unit formed by connecting unit display devices in N rows and M columns, each including means for sequentially selecting row lines of an element array and a brightness adjustment circuit for inhibiting the selection operation of the row lines based on a brightness adjustment signal from the outside.・Equipped with a panel and a unit driver that drives this unit panel to display a television image, and the unit driver binarizes valid image data within the horizontal synchronization period of the television image signal and displays the unit. means for providing common information to each unit display device of the panel;
The horizontal synchronization starts when the vertical and horizontal synchronization signals of the television image signal are applied simultaneously, and the operation of sequentially outputting m clock signals to each column of the unit panel is performed with a predetermined pause period. A clock signal generating means repeats each time a signal arrives, and each time m×n clock signals are outputted to all columns of the unit panel by this means, a clock signal is generated to each row of the unit panel at the timing of the horizontal synchronization signal. select signal generating means for sequentially outputting a select signal; brightness adjustment signal generating means for outputting a common brightness adjustment signal to each of the unit display devices during the rest period of the clock signal; - During the period after all unit display devices of the panel are driven until the arrival of the next vertical synchronization signal, the clock signal output of the clock signal generation means is stopped, and at the same time, a display blanking pulse is applied to the output of the brightness adjustment signal generation means. A display device comprising: means for superimposing images.