JPH0475707B2 - - Google Patents

Abstract

PURPOSE:To display picture gradations correctly by a mechanism which converts picture information sent to a unit panel into plural stages of binary-coded digital signals having different threshold levels and a mechanism which holds them temporarily and outputs them selectively by making a specific scan. CONSTITUTION:Picture data DA is obtained by the video circuit 515 and color circuit 516 of a video signal processing circuit part 51. Then, a control circuit 52 converts the picture data DA into binary-coded signals AD1-ADN of ''1'' or ''0'' by a threshold value modulating and binary coding circuit 522 consisting of comparing circuits having different threshold levels, and those signals are inputted to a data holding circuit 523. The circuit 523, on the other hand, receives scanning signals S1-SN, an address signal ADR, a blanking signal BR, and a clock signal CP to generate plural binary-coded signals D1-Dn for switching and outputting the binary-coded signals having different comparison levels, one after another.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a display device using a display element such as a light emitting diode, and particularly relates to a display device that uses a display element such as a light emitting diode. The present invention relates to a display device for displaying improved television images.

[Technical background of the invention and its problems]

When creating a display device with a large screen area and an extremely large number of pixels by arranging display elements such as light emitting diodes (LEDs) in a matrix, for example CONFERENCE RECORD OF 1978
BIENNI−AL DISPLAY RESEACH
CONFERENCE OCTO−BER 2,4～26
1978, FL-AT-PANEL described in SID P20-21
A method is being considered, such as DISPLAY, in which a large number of small unit display devices each having a drive circuit on the back side of the substrate are connected together. The drive circuit attached to the above-mentioned unit display device has a number of memory elements corresponding to the number of pixels of the display element array of this unit display device, so the terminal interface for operating these display devices can be easily established. It can be said that it is configurable.

A large-scale display device in which a large screen is constructed by connecting such small-sized unit display devices can be schematically represented as shown in FIG. That is, 1 has a plurality of monolithic or hybrid structures constituting a given pixel on the substrate.
As a display section with LEDs arranged in a matrix
The LED array 2 is a module driver as a drive circuit that drives the LED array 1 using the line sequential scanning method.
A unit display device 3 is a unit display device 3 that integrates a module driver 2 with a display function. And this unit display device 3
A unit panel 4 is a unit panel 4 that is arranged in a matrix arrangement vertically and horizontally to form a screen of a desired size.A unit driver 5 supplies various signals and power to this unit panel 4. In combination with the unit driver 5, the display unit 6 has one display function as a whole.

The inventors have already developed the above unit display device,
In particular, we have developed an effective configuration method for the drive circuit (Japanese Patent Application No. 57-201113), and a method for projecting television images on a large-screen display device that is constructed by connecting a large number of unit display devices incorporating this circuit configuration. We have proposed a mechanism (Japanese Patent Application No. 57-171865).

First, the basic structure of the former proposal is as shown in FIGS. 2 to 4. In other words, as an image data storage circuit, an m×n stage static shift register is used for the number of pixels in each row and column direction of a matrix-arranged display element array (m, n), and the output of the first m stages is used to store the display elements. In addition to driving the column lines of the array, switching between inputting image data to the shift register and circulating the shift register is performed depending on the level of a binary-level select signal from the outside. And on the other hand,
Scanning of the row lines of the display element array is performed based on the count of clock signals.

By doing so, the circuit configuration of the module driver included in the unit display device can be simplified. The storage circuit for storing image data to be supplied to the display element array is mainly composed of shift registers, and pixel signals are taken in and read out only by switching the input of the shift register and shifting by a clock signal. This is because it can be done. Therefore, the power consumption of the module driver can be reduced, and
When this module driver is made into an IC, it is easy to incorporate it into the lower part of the substrate where the display element array is arranged.

Furthermore, when arranging such display devices as unit display devices in a matrix and configuring a large screen display device (display unit) as a unit panel, select signal lines and clock signal lines are connected in the row and column directions of the unit panel, respectively. By controlling each unit display device as a whole in the same manner as in line sequential scanning, the select signal and clock signal Since the unit display device can be controlled by a combination of the above, the number of wiring lines between the unit driver and each unit display device can be significantly reduced, and the configuration of the unit driver can also be simplified. Therefore, it is possible to relatively easily realize an extremely large screen with several hundred unit display devices.

The latter proposal attempts to display television images on a large-screen unit panel constructed by combining a large number of the above-mentioned unit display devices.

However, the television video signal is an analog signal, and in the interface circuit mentioned above, in order to convert this analog signal into a digital signal that is binarized into "1" or "0", OA (Off-Easy Automation) etc. Although there was no problem with regular pattern displays, correct image reproduction could not be obtained with displays that required image shading.

[Purpose of the invention]

An object of the present invention is to provide a display device that can correctly display television images with image shading on a large-screen unit panel constructed by combining a large number of unit display devices with a specific number of pixels. .

[Summary of the invention]

A display device according to the present invention includes a display element array formed by connecting display elements with a specific number of pixels (m x n) in a matrix, and stages of the same number as the number of pixels (m x n) of this display element array, and receives a clock signal from an external source. A storage means consisting of a shift register or the like which performs a shift operation according to the method, receives a select signal and image data from the outside, inputs the image data to the storage means from the first stage when the select signal is at the first level, and inputs the image data to the storage means from the first stage when the select signal is at the second level. a switching circuit for inputting the output of the last stage of the storage means to the first stage when the level of A unit display including means for sequentially selecting the row lines of the display element array every time m clock signals are input, and a brightness adjustment circuit for prohibiting selection of the row lines based on an external brightness adjustment signal. It is composed of a unit panel formed by connecting devices in N rows and M columns, and a unit driver that drives this unit panel to display a television image.

On the unit panel, select signals, reset signals, enable signals, and brightness adjustment signals given as common signals to all unit display devices, image data given in common to unit rows, and common signals to unit columns A clock signal given by:

On the other hand, the unit driver receives the image signal, vertical synchronization signal, and horizontal synchronization signal generated by the television's video circuit, color circuit, synchronization separation circuit, vertical synchronization circuit, and horizontal synchronization circuit, and generates each signal necessary for the unit panel. It will be done.

First, a clock separation circuit equipped with an internal oscillator generates a plurality of clock signals corresponding to the unit rows and a luminance signal. In addition, the data holding circuit compares valid image signals within the horizontal synchronization period of the television image signal in multiple stages with different levels for each unit row, depending on the conditions of the clock separation circuit, data selection circuit, and threshold modulation binarization circuit. It is equipped with a memory circuit that temporarily stores the binarized data, and has a device that sequentially switches and outputs the binarized data at multiple stages. Furthermore, a reset signal that initializes the unit panel, and enable and inhibit signals that change the display operation are also generated by this unit driver.

〔Effect of the invention〕

By combining the wiring of the unit panel and devising the unit driver as described above, even when displaying a large screen area, television images that require image shading can be produced without complicating the wiring configuration between the unit driver and the unit panel. is obtained.

[Embodiments of the invention]

First, the configuration of a unit display device according to the present invention and its time chart will be explained with reference to FIGS. 2 to 4. The LED array 1 as a display element array has m (row direction) x n (column direction) LEDs arranged in a matrix and connected to each intersection of m row lines and n column lines. It is configured. Here, the value of m.n is, for example, m=n=16.
For example, the LED array 1 is configured on one substrate. A module driver 2 for driving the LED array 1 is provided at the bottom of this board. This module driver 2 is configured as follows.

That is, the module driver 2 receives a select signal S, serial image data D, clock signal C,
A reset signal R, a brightness modulation signal B, and an enable signal E are input from the outside. Among these signals, select signal S, serial image data D
is input to a switching circuit 10 obtained by a configuration including an AND gate 11, an inverter 12, an AND gate 13, an OR gate 14, and the like. In this switching circuit 10, the level of the select signal S is S="1"
When S=0, the image data D is input to the shift register 15 from the first stage, and when S="0", the output from the last stage of the shift register 15 is input to the first stage.

The shift register 15 is an m×n stage static shift register, in other words, m stages are divided into 1
One block consists of n blocks B ₁ to _Bo . The first block of this shift register 15
B ₁ , that is, the outputs from the first stage to the mth stage, are applied to the row lines in the LED array 1 via a first drive circuit 18 consisting of m amplifiers that amplify the currents of these outputs.

On the other hand, the clock signal C is applied to the shift register 15 and is also input to the bit counter 21. Bit counter 21 and address
The counter 22 is set to an initial state by a reset signal R, and outputs a carry signal CA every time m=16 clock signals C are counted. It should be noted that the clock signal C has an idle period of about 10 to 100 times its period between the K.mth clock and the K.m+1th clock.
The address counter 22 uses this carry signal CA.
In response to this, address signals specifying column lines in the LED array 1 are sequentially output to the decoder 17.

A brightness adjustment circuit 30 composed of AND gates 31, 32 and an OR gate 33 is further provided in the unit display device, and a brightness adjustment circuit 30 is provided as an input signal for controlling brightness adjustment operation based on a brightness adjustment signal B. An enable signal E is prepared. In this case, the brightness adjustment signal B is
A pulse-like signal whose width can be arbitrarily modulated between 1 and 15 cycles of the clock signal applied during the above-mentioned rest period is used for every m=16 clock signals C.

The time chart in Figure 4 shows the situation.

This brightness adjustment signal B is sent to the first AND gate 31.
is input. On the other hand, the bit counter 21 outputs a carry signal CA which becomes low level when all of its A, B, C, and D outputs are high level, and the second
is input to the AND gate 32 and the address counter 22. Brightness adjustment signal B and carry signal
CA is AND when enable signal E is high level.
The signals pass through gates 31 and 32 and are combined at OR gate 33 to become a brightness enable signal BE. This brightness enable signal BE is given to the decoder 17,
When BE is at a high level, the scanning signal output from the decoder is prohibited and the lighting operation of the LED array 1 is stopped. This stop time corresponds to the pulse width of the brightness adjustment signal B, and therefore, the display brightness of the LED array 1 can be adjusted by this pulse width. Note that when the enable signal E is at a low level, the brightness adjustment signal B and the carry signal CA are ignored by the brightness adjustment circuit 30, so that no brightness adjustment is performed.

Next, a specific example of the configuration of the display device of the present invention will be explained.

The unit panel 4 shown in FIG. 5 is constructed by arranging the unit display devices 3 shown in FIG. 2 in a matrix on, for example, a single printed circuit board. Here, the number of rows of the unit display device 3 is assumed to be M, and the number of columns arranged is N. However, unlike FIG. 3, FIG. 5 uses rows in the horizontal direction and columns in the vertical direction. This unit panel 4 receives from the unit driver 5 a select signal S, a reset signal R, a brightness adjustment signal B, which is commonly given to all the unit display devices 3.
An enable signal E, image data D1-DN commonly applied to unit rows, and clock signals C1-CM commonly applied to unit columns are supplied.

FIG. 6 explains the unit driver 5 shown in FIG. 5 in more detail, using the well-known NTSC
system video signal processing circuit section 51 and image data obtained by this video signal processing circuit section 51
The control circuit section 52 receives the DA, horizontal synchronization signal H, and vertical synchronization signal V and generates each signal to be applied to the unit panel 4 described above. The video signal processing circuit section 51 is a tuner 51
0, intermediate frequency amplification circuit 511, audio detection amplification circuit 512, speaker 513, video intermediate detection circuit 51
4, video circuit 515, color circuit 516, synchronization separation frequency division circuit 517, vertical and horizontal oscillation circuit 518,
519 etc. are common ones.

Below, regarding the configuration and operation of Fig. 6, Fig. 7,
This will be explained with reference to FIG. First, in the video signal processing circuit section 51, the composite synchronization signal obtained by the synchronization separation frequency division circuit 517 is sent to the vertical oscillation circuit 518 and the horizontal oscillation circuit 519, and the vertical synchronization signal V,
A horizontal synchronization signal H is produced. On the other hand, the image data DA is processed by the video circuit 515 and the color circuit 516.
is obtained.

Next, in the control circuit unit 52, the image data DA is first processed by a threshold modulation binarization circuit 522, which converts the image data DA into a plurality of “1” or 0'' as binary signals AD1 to ADN.

On the other hand, the timing circuit 521 captures the synchronization signals of the vertical synchronization signal V and the horizontal synchronization signal H,
Then, a vertical synchronizing pulse signal VP and a horizontal synchronizing pulse signal HP having a predetermined width are generated. The horizontal synchronizing pulse signal HP is applied to a clock separation circuit 524, which separates the clock signals C1 to CM, the luminance signal B, and the clock signal
Carry signal generated for each sequential scan of C1 to CM
CY is created.

Further, the vertical synchronizing pulse signal VP is sent to the data select circuit 525, and various signals S1 to SN and ADR that influence the operation of the data holding circuit 523 and a blanking signal B to be applied to the clock separation circuit 524 are generated. The data holding circuit 523 receives a plurality of binary signals AD1 to ADN and the data select circuit 525.
scanning signals S1 to SN, address signal ADR from
The AND clock signal CP of the blanking signal BR of the data select circuit 525 and the internal oscillation clock signal of the clock separation circuit 524 is applied, and a plurality of binary signals with different comparison levels are sequentially switched and output. conversion signals D1 to DN are generated. The control circuit section 52 also receives a reset signal R for initializing each unit display device 3 of the unit panel 4, an enable signal E for changing the display mode, and a select signal S for changing the display mode, and a refresh circuit 526 and an enable control 52, respectively.
7 and a stop circuit 528.

Next, using FIG. 9, the threshold modulation binarization circuit 522, the refresh circuit 526, and the clock separation circuit 524 in the control circuit section 52 will be explained.
The operation of the data holding circuit 528 will be explained in more detail.

First, the image data DA is input to the threshold modulation binarization circuit 522, and the A/D (analog/digital) conversion circuit 210 determines the threshold level based on the combination of the reference potential level Vc and R1 and R2.
Binarized signals AD1 to ADN having different threshold levels are generated by the binarized circuits 21 to 2N each having a different threshold level.

Then, these binary signals AD1 to ADN are input to the data holding circuit 523. The data holding circuit 523 includes, for example, a number of data storage selection circuits 31 to 3 corresponding to the unit rows of the unit panel 4.
N, and the binary signals AD1 to ADN are output from AND circuits 311 to 31 of each data storage selection circuit 31 to 3N.
Input to N.

On the other hand, the horizontal synchronization pulse HP is applied to the counter 43 and decoder 44 of the clock separation circuit 524, and the vertical synchronization pulse signal VP is applied to the counter 510, decoder 530, and blanking circuit 540 of the select circuit 525. It functions to reset the internal information of the system and return it to the base point. The operation of the clock separation circuit 524 and the selection circuit 525 is as follows: First, the clock signal CK from the oscillator 41 is output from the blanking circuit 540.
As a logical product with BR, a new clock signal CP is generated and sent to the counter 43, M AND gates 48, and data holding circuit 523. Then, every m clock counts from counter 43, 1
The count signal CT generated in the number of times is sent to the decoder 44, and the AND gate 48 calculates the AND of the M number of outputs of the decoder 44 and the clock signal CP.
As a result, clock signals C1, C2, C3...CM are sequentially output. This decoder 44 outputs one carry signal every time M clock scans are completed.
CY is output and sent to counter 510.

The counter 510 sends the address signal ADR to the decoder 530 every n counts of the carry signal CY.
This decoder 530 sends a select signal
S1 to SN are generated sequentially. Furthermore, the select signal
One output signal indicating the end of SN is given to the blanking circuit 540 to generate a blanking signal BR. This blanking signal BR is held until the blanking circuit 540 is reset by the vertical synchronizing pulse signal VP as described above.
Select signal when n・N is 240
Generation of the select signal is prohibited for a period of 22.5 horizontal synchronizing signals H remaining in one field scan after the end of SN. Also, the frequency of the oscillator 41 is approximately 84% of the effective scanning line length within the horizontal scanning period of 63.5 μs.
This is the sampling speed of effective image data m・M included in 53 μs. For example, when the number of horizontal pixels mN of the unit panel is 320, it is approximately
It will be 6MHZ.

On the other hand, an output signal synchronized with the clock signal CK is sent from the counter 43 to a brightness adjustment signal generation circuit 46, and when m=16, a brightness adjustment signal BY whose pulse width is variable in a range of 1 to 15 clock cycles is generated. Then, the brightness adjustment signal BY and the blanking signal BR are combined by the OR gate 47 to form the final brightness adjustment signal B.

Next, to explain the operation of the data holding circuit 523, first, the clock signal CP is applied to the AND gates 342 to 34N in each data storage selection circuit 31 to 3N.
is input. And data storage selection circuit 31
-3N are input with one select signal S1-SN from the decoder 530, respectively, and constituted by ANDing with the binarized signals AD1-ADN from the threshold modulation binarization circuit 522. That is, when the select signal S1 is at the "1" level, the AND gates 311 to 3 in the data storage selection circuit 31
1N operates, unit row memories 342-34N
is memorized. Similarly, select signal S1 is “0”
When the select signal reaches the "1" level, it is stored in the unit memories 342 to 34N in the data storage selection circuit 32. Thereafter, similar operations are repeated to store information on the binary signals AD2 to ADN having different comparison levels in the data storage selection circuit 3N. At this time, for example, the switch circuit 350 of the data storage selection circuit 31 operates based on the address signal ADR from the counter 510, and when the select signal S1 is at the "1" level, the data from the AND gate 311 is directly output. The output image signal becomes D1, and the select signal S2 becomes “1”.
When the select signal S1 is at the "1" level, the data written to the unit row memory 342 becomes the output image signal D1 in synchronization with the movement of the clock signal CP.

Similarly, when the select signal S3 is at the "1" level, the OR gate 323 becomes "1" and the clock signal is sent from the AND gate 333 to the unit row memory 3.
43 and sent to the switch circuit to become the output image signal D1.

The other data storage selection circuits 32 to 3N operate similarly. That is, the data storage selection circuit 32
When the select signal S2 is at the "1" level, the binary data is stored in each unit row memory 342 to 34N.
AD2 to ADN are stored. However, in this data storage selection circuit 32, the select signal S1
The order of combination of ~SN is different, starting with the select signal S2 and completing one cycle with the select signal S1. Similarly, in the data storage selection circuits 33-3N, the order of the select signals S1-SN is different.
That is, the image signals D1-DN from each data storage selection circuit 31-3N are the select signals S1-SN
Other than those selected in , the image data is actually output as information delayed from the real time, but there is no problem with the display.

Binarized signals AD1 to ADN and select signal S1
-SN, data storage selection circuits 31 to 3N, and their image output signals D1 to DN are all handled as 1 to N, which corresponds to the number of unit matrices of the unit panel 4 described above.

That is, the predetermined time when all the binary data AD2 to ADN stored in each of the data storage selection circuits 31 to 3N is released and the timing at which each of the data storage selection circuits 31 to 3N is selected again are determined by one screen of the unit panel 4. Match on scanning.

However, this data storage selection circuit 31~
Even if the number 3N does not match the number of unit rows in the unit panel 4, it does not matter if, for example, one image data is given to two unit rows, or one image data is given to four unit rows of 3 unit rows. do not have.

However, in this case, each data storage selection circuit 3
Information corresponding to the unit rows spanned by each of the image data D1 to DN is required to indicate the number of data to be directly output by selecting the unit row memories 342 to 34N and the select signals S1 to SN within the unit rows 1 to 3N.

In short, select signals S1 to SN and address
The number of ADRs and unit row memories 342-34N may be set so as not to interfere with the unit rows of the unit panel 4 and their input image data D1-DN.

FIG. 10 shows another embodiment of the invention.

First, data storage selection circuits 31 to 3N include AND gates 361 to 36N and OR gates 37 instead of AND gates 311 to 31N shown in FIG.
1 to 37N, inverters 381 to 381N, and AND gates 391 to 39N.

Then, the binarized data AD1 to ADN from the threshold modulation binarization circuit 522 are respectively input to one side gate of the AND gates 361 to 36N, and each of the other gates is inputted to each of the AND gates 361 to 36N. , timing signals T1 to TN from a newly added decoder 520 are input into the data select circuit 525.

This decoder 520 operates in the same manner as the decoder 530, but receives a vertical synchronization pulse as an input signal.
In addition to VP and address signal ADR, there is also an inhibit signal
If INH is input, this inhibit signal
When INH goes to "1" level, all output signals T1 to TN go to "0" level.

Further, each of the timing signals T1 to TN from the decoder 520 and the select signals S1 to SN from the decoder 530 are sent to the data storage selection circuits 31 to 3.
When any one of the signals reaches the "1" level, each of the AND gates 331 to 33N inputs the unit row memories 341 to 34 according to the movement of the clock signal CP.
The data stored in N is sent to the switch circuit 350. Since the switch circuit 350 is controlled by the address signal ADR synchronized with the movements of the decoders 520 and 530, it is selected so that the decoders of the unit row memories 341 to 34N are outputted as image data D1 to DN. .

Here, the connection order of the select signals S1 to SN and the timing signals T1 to TN to the data holding circuit 523 is different from that in FIG.
3N.

Then, as described above, when the input inhibit signal 1NH to the decoder 520 goes to the "1" level, all the timing signals T1 to TN go to the "0" level and are stored in the unit row memories 341 to 34N in the data holding circuit 523. is the new binary signal AD
1 - ADR will no longer be written. However, the output data of the unit row memories 341-34N selected by the select signals S1-SN and the clock signal CP are in the process of being written back into the unit row memories through the respective AND gates 391-39N. During the period when the inhibit signal 1NH is at the "1" level, the same image information is repeatedly displayed.

As explained above, the invention consists of a mechanism for converting image information sent to a unit panel into a binary digital signal of multiple stages with different threshold levels, and a mechanism for holding this binary digital signal data and converting it into a predetermined signal. By selectively outputting during scanning, it is possible to correctly display images such as television, which require image shading.

In addition, if the select signal input to the unit panel 4 in FIG. 5 is at the "1" level, which is the same potential as the normal power supply, the above-described operation is possible. When set to the "0" level by the stop circuit shown in , the data written in the shift register in the unit display device is repeatedly displayed. In this way, by devising the arrangement of signal connections to the unit panel and the configuration of the unit driver, the functionality of the display device can be enhanced without complicating the wiring between the unit panel and the unit driver.

Note that the AND gates and OR gates used in each circuit can be replaced with other gates, switch circuits, and selector circuits as long as they achieve the desired function, and as a unit row memory used as a memory circuit, a shift register or a It is also possible to use RAM.

[Brief explanation of the drawing]

FIGS. 1a and 1b are diagrams schematically showing the basic configuration of a unit display device and a display unit configured by arranging them in a matrix, and FIGS. 2 and 3 are diagrams showing the basic configuration of a unit display device used in the present invention. FIG. 4 is a time chart showing the operation. FIG. 5 and FIG. 6 show a unit display device showing an embodiment of the present invention.
A diagram schematically showing the configuration of a unit panel made up of individual parts and a unit driver of its drive circuit, and
7 and 8 are time charts showing the operation of the horizontal synchronizing signal and vertical synchronizing signal to explain the television signal according to the present invention, and the correspondence between effective image data included in the horizontal scanning period and clock pulses. The operation time chart shown, and the ninth
The figure is a diagram for explaining in detail the unit driver circuit configuration of the present invention, and FIG. 10 is a diagram further devising the circuit configuration of FIG. 9. 1...LED array (light emitting element array), 2...
Module driver, 3...Unit display device, 4...Unit panel, 5...Unit driver, 6...Display unit (display device), 10...Switching circuit, 15...Shift register, 17, 44, 520 , 530... decoder, 18, 19... current amplifier circuit, 21, 22,
43, 510...Counter, 41...Clock signal generation circuit (oscillator), 54...Blanking pulse generation circuit, 46...Brightness adjustment circuit, 47...
Brightness signal synthesis circuit, R...Reset signal, B...Brightness modulation signal, E...Enable signal, C, C1~
CM...Clock signal, S, S1~SN...Select signal, H...Horizontal synchronization signal, V...Vertical synchronization signal, DA...Analog image data, AD1~
ADN...Binarized image signal, 341-34N...
Unit row memory, 350...Switch circuit, 3
1...Data storage selection circuit, D1-DN...Image data, T1-TN...Timing signal, INH...
...Inhibit signal, 522...Threshold modulation 2
Value circuit.

Claims (1)

[Scope of Claims] 1. A display element array formed by connecting display elements with a specific number of pixels (m×n) in a matrix, a storage means having a capacity equal to the number of pixels (m×n) of this display element array, and this storage means. a switching means for inputting external image data when a select signal is at a first level and inputting an output from the final stage of the storage means when the select signal is at a second level, according to the operation of a clock signal; A unit display device comprising means for current amplifying and controlling the output of the first stage of the means and supplying it to the column lines of the display element array, and a brightness adjustment means for prohibiting the selection operation of the row lines based on a brightness adjustment signal from the outside. A unit panel consisting of N rows and M columns connected together, a select signal, a reset signal, an enable signal, and a brightness adjustment signal given as common signals to all the unit display devices of this unit panel, and a common signal for each unit row. The unit driver is equipped with a unit driver that supplies image data to be given to each unit row, and a clock signal that is commonly given to each unit column. It is initialized by receiving the image signal, vertical synchronization signal and horizontal synchronization circuit generated by a clock generating means that repeats the output operation every time a horizontal synchronizing signal arrives with a predetermined pause period; and a brightness adjustment signal generator that outputs a common brightness adjustment signal to each of the unit display devices during the pause period of the clock signal. means for binarizing the valid image data within the horizontal synchronization period using a plurality of thresholds with different comparison levels for each row of the unit panel; and 2 clock signals to be applied to each unit row of the unit panel by means of a horizontal synchronizing signal, its decoded output signal, and an address signal each time m×n clock signals are outputted to each unit column of the unit panel. 1. A display device comprising means for sequentially switching and outputting digitized image data. 2. A clock signal, a decode signal, and the same address signal as the address signal that scans this decode signal are used as control signals for storing a plurality of pixel data binarized with different comparison level thresholds in each unit row memory. A timing signal to operate is input, and the output of this timing signal is operated in the same manner as the decode signal when the input inhibit signal from the outside is at the first level, and is completely inhibited when it is at the second level, thereby threshold modulation 2 is performed. Select either to input the new binary image data created by the digitization circuit into the unit row memory, or input the data stored in the unit row memory into the unit row memory by repeatedly feeding it back. 2. The display device according to claim 1, further comprising data input switching means.