JPH0121560B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention connects a plurality of circuits with the same circuit configuration in series, and calculates an address corresponding to each circuit from a single piece of serially transferred data. The present invention relates to a data setting device having a function of assigning and setting arbitrary data to a circuit corresponding to the address.

[Prior art]

First, a conventional device for setting data to a plurality of devices will be explained.

FIG. 1 is a circuit configuration diagram of a conventional data setting device for a plurality of devices. In FIG. 1, 1 is a control circuit, and A ₀ to _{A o-1} are registers.

When setting data to registers A ₀ to A _o-1 in Figure 1, first set the data at address 0 to the DATA signal, input the SET (0) signal after setting the data, and set the data to register A ₀ . do. Next, set the data at address 1 to the DATA signal, input the SET(1) signal after setting the data, set the data in register A ₁ , and so on. of
Input the SET signal and set data in the specified register.

This data setting device is effective when the number of addresses is small, but when the number of addresses increases, a separate SET signal is required for each address, so the control circuit 1 The number of signal lines will also increase. Therefore, when connecting signals using cables, the number of cables increases, the number of connectors and connector mounting locations increase, the causes of failures such as disconnections and short circuits of signal lines increase, and reliability decreases. descend. Furthermore, when a multilayer substrate is used, there are drawbacks such as an increase in the number of signal layers.

[Summary of the invention]

Therefore, this invention eliminates these drawbacks and
The present invention provides a data setting device capable of setting data corresponding to each of a plurality of data setting circuits having the same circuit configuration using three signal lines.

[Embodiments of the invention]

FIG. 2 is a block diagram of a data setting device according to the present invention, in which 1 is a control circuit and B ₀ to _{B o-1} are data setting circuits.

FIG. 3 is a diagram showing an embodiment of the data setting circuit configuration according to the present invention, in which 2 is a first shift register, 3 is a second shift register, 4 is a data shift register, and 5 is an up/down counter ( (hereinafter abbreviated as U/D counter), 6 is for start detection
NAND gate circuit, 7 is binary counter, 8 is m
digit counter, 9 is F/F circuit for mode switching, 10
11 is a check bit determination circuit, 12 is an AND gate circuit for address set, 13 is an address register, 14 is an address comparison circuit, 15 is an AND gate circuit for data set, and 16 is a data register. .

Figure 4 shows a timing chart of data transfer from the control circuit 1 in Figure 2, and Figure 5 shows start data, mode data, data (0) to data (n-1) when setting an address, and data when setting data. The data format of data (0) to data (n-1) is shown in Figures 6 to 9 as address (n-1).
10 to 13 show timing charts when setting data at address (n-1).

First, the operation up to t(2) in FIG. 4 in the data setting circuit B _o-1 in FIG. 2 during address setting will be explained using FIG. 7. However, in Figure 7
Refer to FIG. 6 for the data division of the DATA-IN signal and DATA-OUT signal.

The start data at t(0) in FIG. 4, that is, the start data part of the DATA-IN signal in FIG. The data is transferred from the first shift register 2 to the data shift register 4 as shown in the figure, and when all the start data has been captured, it is used for start detection.
The output st of the NAND gate circuit 6 changes from "H" to "L" as shown in FIG. 7, and the binary counter 7 and the set termination F/F circuit 10 shown in FIG. 3 are reset. At this time, the MSB of the start data is output as the DATA-OUT signal as shown in FIG. 7, and this DATA-OUT signal becomes the DATA-IN signal of the next data setting circuit B _o-2 . In addition, in this reset state, the mode data "0" of FIG. 5B is taken into the first shift register 2, and the output st of the start detection NAND gate circuit 6 of FIG. 3 becomes "0" as shown in FIG. The binary counter 7 in FIG. 3 starts counting from the falling edge of the CLOCK signal after it becomes "H", and after 2 counts, the output Ms of the binary counter 7
changes from "L" to "H" as shown in FIG. 7, and the mode data is taken into the mode switching F/F circuit 9 of FIG. Q1 changes from "L" to "H" as shown in FIG. At the same time, the m-adic counter 8 in Figure 3
The reset is canceled when the clock signal changes from "H" to "L" at the next falling edge of the clock signal as shown in Ms in Figure 7, and the m-adic count starts from the next falling edge of the CLOCK signal. starts, and the binary counter 7 stops. At this time, the DATA-IN signal outputs address setting data (0), which is a set of address judgment data (n), address data (0), and check bits, as shown in Figure 5c.
MSB is input, and when this data (0) is taken into the first shift register 2, second shift register 3, and U/D counter 5 in FIG.
The output Cb of the check bit determination circuit 11 changes from "L" to "H" as shown in FIG.

Then, I imported the LSB of data (0)
At the next falling edge after the rising edge of the CLOCK signal, Tp of the m-ary counter 8 in FIG. 3 changes from "L" to "H", and the output As of the AND gate circuit 12 for address setting changes as shown in FIG. Changes from “L” to “H”. At the rising edge of As, the address data (0) stored in the second shift register 3 in FIG.
At the same time as U/
It is used as a countdown clock for the D counter 5, and the address judgment data (n) is set to (n-1). Then, the address data (0) (S _A in FIG. 7) taken into the address register 13 and the output C _A of the U/D counter 5 in FIG. 3 are compared in the address comparison circuit 14. At this time, since the two do not match, the output _C0 of the address comparison circuit 14 remains "L" as shown in FIG. 7, and the output terminal Q of the set completion F/F circuit 10 in FIG. As shown in FIG. 7, _{signal 2} also remains at the "L" level and does not change.

Next, data (1) of the DATA-IN signal in Figure 7 is
At the same time, the data (0) that has been taken in so far is outputted one bit at a time starting from the MSB, as shown in the DATA-OUT signal in Figure 6. .
However, the address judgment data (n) at the time of input is
Address judgment data counted down by 1 (n
-1).

Repeat the above operation until t(n) in Figure 4,
The data (n-1) of the DATA-IN signal in Figure 8 is
At the rising edge of the CLOCK signal, the first shift register 2, second shift register 3, and U/D counter 5 take in the signal. At the falling edge of the next CLOCK signal, the address setting AND gate circuit 12 shown in FIG. As shown in FIG. 9, As changes from "L" to "H", and at the rising edge, the address data (n-1) stored in the second shift register 3 in FIG. 3 is taken into the address register 13. At the same time, the address determination data (n) of the U/D counter 5 is set to (n-1), and the address comparison circuit 14 compares the two. At this time, since the two match, the output _C0 of the address comparison circuit 14 changes from "L" to "H" as shown in FIG. 9, and the output terminal Q of the set completion F/F circuit 10 in FIG. ₂ is the 9th
As shown in the figure, it changes from “L” to “H” and the third
The m-ary counter 8 in the figure stops at the next falling edge of CLOCK, and does not operate thereafter until the start data is input and the output terminal _Q2 of the set completion F/F circuit 10 changes from "H" to "L". , the output As of the address set AND gate circuit 12 does not change, and desired address data (n-1) is set in the address register 13.

Next, the method of setting data will be explained.

Regarding data setting, data from start data at t(0) to data (n-1) at t(n) is transferred, as shown in FIG. 4, in the same way as when setting addresses. The contents of the data at this time are as shown in B and D in Fig. 5. The mode data of B changes from "00" to "01" when setting the address, and the data (0) to
Data (n-1) is a combination of address data, set data, and check bits.

The operation is almost the same as when setting an address, as shown in the DATA-IN signal in Figure 10.
When the start data is input to the first shift register 2, second shift register 3, and U/D counter 5 shown in FIG. 3, the output St of the start detection NAND gate circuit 6 becomes "as shown in FIG. The signal changes from "H" to "L" and resets the binary counter 7 in FIG. 3 and the set end F/F circuit 10 as shown in Ms and _Q2 in FIG. 11.

Next, the mode data "0" is taken into the first shift register 2 in FIG. 3 at the rising edge of the CLOCK signal, and at the next falling edge of the CLOCK signal,
The output Ms of the advance counter 7 changes from "L" to "H" as shown in FIG. 11, and the mode data is taken into the mode switching F/F circuit 9 shown in FIG.
from “L” to “H” as shown in Figure 11,
The address set AND gate circuit 12 is blocked, and the data set AND gate circuit 15 is unblocked. and DATA−IN
Data from the MSB of data (0) is continuously transferred to the signal, and when all data (0) is taken in, the output Tp of the m-ary counter 8 in FIG. 3 and the output Cb of the check bit judgment circuit 11 are as shown in FIG. 11. As shown, both become "H", but U/D in Figure 3
Since the address data (0) of the data (0) taken into the counter 5 and the address data (n-1) taken into the address register 13 do not match, the output C ₀ of the address comparison circuit 14 is as shown in FIG. As shown in FIG. 7, it remains "L" and does not change, so the data set AND gate circuit 1 in FIG.
Since the output Ds of the shift register 5 remains "L" as shown in FIG. 11, the set data (0) taken into the second shift register 3 is not taken into the data register 16.

Similarly, since the addresses do not match from data (1) to data (n-2), the contents of the data register 6 do not change.

Then, when the data (n-1) is fetched, the address data (n-1) fetched into the U/D counter 5 in FIG. 3 and the data fetched into the address register 13 match, and the address comparison circuit The output _C0 of the shift register 14 changes from "L" to "H" as shown in FIG. At the same time as reading into the register 16, the m-ary counter 8 is stopped at the falling edge of the next CLOCK signal, and the m-ary counter 8 does not operate until the start data is input, just like when setting the address, and the data set AND gate is Since circuit 15 is blocked, the contents of data register 16 do not change.

〔Effect of the invention〕

By using the data setting device of the present invention based on the above principle, no matter how much the number of addresses to be set increases, the number of signal lines with the control circuit 1 does not increase, and the number of cables, connectors, and connector mounting positions also increases. This improves workability and reliability, and eliminates the need for increasing the number of board layers even when a multilayer board is used.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of a conventional data setting device, FIG. 2 is a diagram showing a circuit configuration of a data setting device according to the present invention, and FIG. 3 is a diagram showing a circuit configuration of the data setting circuit of FIG. 2. , Figure 4 is the same as Figure 2.
Figure 5 shows a timing chart of data transfer at time t of the DATA-IN signal.
Figures 6 and 7 are diagrams showing the format of data input to the -IN signal.
1), FIGS. 8 and 9 are diagrams showing timing charts at the end of address setting in the data setting circuit (n-1), and FIGS. 10 and 11 are diagrams showing timing charts at the start of address setting. A diagram showing a timing chart at the start of data setting in the data setting circuit (n-1), FIG.
FIG. 13 is a diagram showing a timing chart when data setting is completed in the data setting circuit (n-1). In the figure, 1 is a control circuit, A ₀ to _{A o-1} are registers,
B ₀ to B _o-1 are data setting circuits, 2 and 3 are shift registers, 4 is data shift register, 5 is U/D
Counter, 6 is NAND circuit for start detection, 7
8 is a binary counter, 8 is an m-ary counter, 9 is a flip-flop circuit for mode switching, 10 is a flip-flop circuit for completing set, 11 is a check bit determination circuit, 12 is an AND circuit for address set,
13 is an address register, 14 is an address comparison circuit, 15 is an AND circuit for data setting, and 16 is a data register. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims] 1. In a data setting device in which N circuits having the same circuit configuration are connected in series, start data indicating the beginning of data, mode data setting the type of data, address data setting addresses to N circuits, The transfer data consisting of and the setting data given to each circuit is introduced using the same transfer line, and after the start data in the transfer data is transferred, the mode data is transferred, and the next data to be transferred is the address means for determining whether it is data or setting data, and when it is determined by this means that it is address data, one is set at a setting address 0 to N-
1. A means for configuring data as a pair with the other address being N, subtracting 1 from the other address data N each time it passes through one circuit, and storing the address when both addresses match, and setting. The present invention is characterized by comprising means for transferring data as a pair of addresses 0 to N-1 and desired setting data, and setting desired setting data in each circuit at the time when the data matches the stored address. Data setting device.