JPH0257382B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention connects a plurality of circuits with the same circuit configuration in series, and sets addresses and data corresponding to each circuit from serially transferred data. The present invention relates to a device having a monitoring function for determining whether or not the set address and data are set to desired values.

[Prior art]

The conventional data transfer system only has the functions of address and data setting, and its operation will be described below.

FIG. 1 is a circuit configuration diagram of a data transfer method to a plurality of circuits, in which 1 is a control circuit, 1a is a failure detection circuit, and A ₀ to _{A o-1} are data transfer circuits.

FIG. 2 shows an example of a conventional data transfer circuit, in which 2 is a shift register, 3 is a data shift register, 4 is an up-down counter (hereinafter abbreviated as U/D counter), 5 is a start detection gate circuit,
6 is a ternary counter, 7 is an m-ary counter, 8 is a mode register, 9 is a mode selector, 10 is an F/F circuit for setting completion, 11 is a check bit judgment circuit, 12 is a gate circuit for address set, and 13 is an address register. , 14 is an address comparison circuit, 1
5 is a data set gate circuit, and 16 is a data register.

Figure 3 shows a timing chart of data transfer from the control circuit in Figure 1. Figure 4 shows start data, mode data, data (0) to data (n-1) during address setting and data setting. The data format of data (0) to data (n-1) is shown in Figures 5 and 6, and the timing charts at the start of address setting at address (n-1) are shown in Figures 7 and 8. A timing chart at the time of address setting in (n-1) is shown.

First, the operation up to t ₍₂₎ in FIG. 3 in the data transfer circuit of FIG. 1 A _o-1 at the start of address setting will be explained using FIG. 6. However, in Figure 6
Refer to FIG. 5 for data division of the DATA-IN signal and DAHA-OUT signal.

The starting data in Figure 3, that is, in Figure 6
The start data part of the DATA-IN signal is
In synchronization with the rising edge of the CLOCK signal, the MSB of the start data in Figure 4 is shifted and captured one bit at a time from shift register 2 to data shift register 3 in Figure 2, and starts when all the start data is captured. Detection gate circuit 5
The output S ^t changes from “H” to “L” as shown in Figure 6.
The ternary counter 6 and the set end F/F circuit 10 shown in FIG. 2 are reset. At this time
The MSB of the start data is output to the DATA-OUT signal as shown in Figure 6, and this DATA-OUT signal is
The OUT signal is transferred to the next data transfer circuit shown in Figure 1.
This becomes the DATA-IN signal of A _o-2 . In addition, in this reset state, the MSB of the mode data shown in FIG. 4B is loaded into the shift register 2, and the output S ^t of the start detection gate circuit 5 shown in FIG. ”, and from the rise of the CLOCK signal after it becomes “H”, the ternary counter 6 in FIG. 2 starts counting, and after 3 counts, it reaches 3.
The output MS of the decimal counter 6 changes from "L" to "H" as shown in FIG. 6, and the mode data is taken into the mode register 8 of FIG. 2 as shown at t ₍₀₎ of FIG. The output AD of the selector 9 changes from "L" to "H" as shown in FIG. At the same time, the m-ary counter 7 shown in FIG. 2 is reset. This reset state is released when the signal goes from "H" to "L" at the next falling edge of the clock, as shown by MS in FIG. starts, and the ternary counter 6 stops. At this time, address determination data (n) as shown in FIG. 4C is output from the DATA-IN signal.
Address setting data (0), which is a set of address data (0) and check bit, is input from the MSB, and when this data O is taken into the shift register 2 and U/D counter 4 in Fig. 2, check bit judgment is made. The output Cb of the circuit 11 changes from "L" to "H" as shown in FIG.

Then, I imported the LSB of data (0)
At the next falling edge after the rising edge of the CLOCK signal,
Tp of decimal counter 7 changes from “L” to “H”,
The output AS of the address set gate circuit 12 changes from "L" to "H" as shown in FIG. this
At the rising edge of AS, address data O stored in shift register 2 in Figure 2 is transferred to address register 1.
At the same time, it is used as a countdown clock for the U/D counter 4, and address determination data (n) is set to (n-1). And in Figure 7
The address comparison circuit 14 compares the address data (0) taken into the address register 13 indicated by SA with the output CA of the U/D counter 4 shown in FIG.
At this time, since the two do not match, the output CO of the address comparison circuit 14 remains "L" as shown in FIG. 6, and does not change.
The output Q of 0 also remains unchanged at the "L" level as shown in FIG.

Next, data 1 of the DATA-IN signal in Figure 6 is
At the same time, the data (0) that has been taken in so far is outputted bit by bit from the MSB as shown in the DATA-OUT signal in FIG. however,
Address determination data (n) at the time of input is output as address determination data (n-1) that is counted down by one.

Repeat the above operation until t(n) in Figure 3,
The data (n-1) of the DATA-IN signal in Figure 7 is
At the next fall of the CLOCK signal, which is taken into the shift register 2 and U/D counter 4 at the rising edge of the CLOCK signal, the output AS of the address set gate circuit 12 in FIG. L"
The level changes from "H" to "H", and at the rising edge, the address data (n-
1) into the address register 13, the address determination data (n) of the U/D counter 4 is set to (n-1), and the two are compared in the address comparison circuit 14. At this time, since the two match, the output CO of the address comparison circuit 14 changes from "L" to "H" as shown in FIG. 8, and the output Q of the set end F/F circuit 10 in FIG. As shown in FIG. 8, the level changes from "L" to "H", and the m-ary counter 7 in FIG. 10 does not operate until the output Q changes from "H" to "L", the output AS of the address set gate circuit 12 does not change and the desired address data (n
-1) is set.

Next is the data setting.Compared to the address setting, in the DATA-IN signal in Figure 1, the mode data contents change from "000" to "001" as shown in Figure 4B. , the contents of data (0) to data (n-1) change from C to D in Figure 4,
Operationally, as the mode data changes, the mode selector 9 output AD in FIG. 2 changes from "H" to "L", and the address set gate circuit 12 changes.
is blocked, and DT changes from “L” to “H” instead.
Then, the data set gate circuit 15 is opened, and the data in the address register 13 and FIG.
The comparison circuit 14 compares the address data of
changes from “L” to “H”, and the data register 16
The only difference is that the set data shown in FIG. 4D is taken in, but the rest is the same as when setting the address, so a description thereof will be omitted.

The above are the functions of the conventional data transfer method, and since it only has the function of simply setting the address and data of the data transfer circuit,
Even if the DATA-OUT signal in the figure is normal, if the address register 13, data register 16, etc. in Figure 2 is broken and the set data in Figure 4 D is not being input normally, multiple data transfer circuits It is very difficult to discover which part of the circuit is abnormal and which part of the circuit is malfunctioning.

[Summary of the Invention] Therefore, the present invention improves these drawbacks without increasing the number of signal lines, and by monitoring the address and set data of each data transfer circuit,
This circuit enables early detection of failures and detection of failure locations.

[Embodiments of the invention]

FIG. 9 shows an embodiment of the data transfer circuit according to the present invention, in which the data registers from shift register 2 to 16 are the same as the conventional ones, 17 is a byte select gate circuit, 18 is a byte selector, and 19 is a clock control circuit. , 20 are gate circuits for clock control. Figure 10 shows the data formats of data (0) to data (n-1) at the time of start data, mode data, address setting, data setting, byte address setting, and byte data setting. Figure 12 shows the timing chart when byte data setting starts at address (n-1), and Figures 13 and 14 show the timing chart at address (n-1).
1) shows a timing chart when setting byte data.

The operation of the data transfer circuit according to the present invention will be explained below, but the difference between byte address setting and byte data setting is that the mode selector 9 output in FIG.
Difference between BA and AD and output of byte selector 18
The only difference is that the contents of the SD are the contents of the address register 13 or the contents of the data register 16, and since the operations are the same, the explanation of the operation for setting the byte address will be omitted, and only the operation for setting the byte data will be explained.

First, the operation up to t ₍₂₎ in FIG. 3 will be explained using FIG. 12. However, DATA− in Figure 12
See Figure 11 for the data divisions of the IN signal and DATA-OUT signal.

The start data part of the DATA-IN signal in Figure 12 is synchronized with the rising edge of the CLOCK signal.
Starting with the MSB in Figure 0, bit by bit is transferred from the shift register 2 to the data shift register 3 in Figure 9, and when all the start data has been acquired, the start detection gate circuit 5
The output S ^t changes from "H" to "L" as shown in FIG. 12, and the ternary counter 6 and set end F/F circuit 10 in FIG. 9 are changed to MS and Q in FIG. 10. Reset as follows. In this reset state, the MSB of the mode data shown in FIG. 10B is taken into the shift register 2, and the output S ^t of the start detection gate circuit 5 shown in FIG. 9 changes from "L" to "H" as shown in FIG. The ternary counter 6 in FIG. 9 starts counting from the rise of the CLOCK signal after it becomes "H", and after 3 counts, the ternary counter 6 starts counting.
The output MS of the advance counter 6 changes from "L" to "H" as shown in FIG. 12, and the mode data is taken into the mode register 8 shown in FIG.
The output BD of the byte selector 18 is changed from "L" to "H" as shown in FIG. west,
The clock control circuit 19 is put into operation.

Further, the output MS of the ternary counter 6 resets the m-ary counter 7 shown in FIG. This reset state is released when the signal goes from "H" to "L" at the next falling edge of the clock, as shown by MS in FIG. starts, and the ternary counter 6 stops. Also, at this time, the first
Byte data setting data (0), which is a set of address data, byte data, and check bits as shown in Figure F, is input from the MSB, and this data (0) is input to shift register 2 and data shift in Figure 9. When captured in register 3, the 4th
The address data in FIG. F, that is, the input CA of the comparator circuit 14 in FIG.
Since it does not match the address data SA that is input to
Since the output Q of 0 also remains at the "L" level as shown in FIG. 12, the clock control circuit 19 also does not operate, and the output of the clock control gate circuit 21
The CLOCK signal is directly output to CC, and the next byte data (1) is loaded into the shift register 2 shown in FIG.

Repeat the above operation until t(n) in Figure 3,
When the byte setting data (n-1) of the DATA-IN signal in Figure 14 is taken into the shift register 2 and data shift register 3 in Figure 9 at the rising edge of the CLOCK signal, the address data in Figure 4F In other words, since the input CA of the comparison circuit 14 in FIG. 9 and the address data SA already input to the address register 13 match, the output CO of the comparison circuit 14 becomes "L" as shown in FIG. From “H”
The output Q of the F/F circuit 10 changes from "L" to "H" as shown in FIG. 14, causing the clock control circuit 19 to operate. The operation of this clock control circuit 19 is as shown in FIG.
Outputs clock pulses. During this change in the output SC of the clock control circuit 19, the shift register 2 changes the function of shifting the previous data to the byte selector 18 that is input in parallel.
The function is to take in the output SD of the byte data, and at the next clock rise after taking the byte data setting data (n-1) into the shift register 2 and data shift register 3, the 9th byte data of FIG.
By blocking the clock control gate circuit 20 at the same time as taking in the output SD of the byte selector 18 shown in the figure, the CLOCK clock is set as shown in FIG. 14 CC.
By blocking the signal by one clock, the output SD of the previous byte selector 18 is taken into the data shift register 3 while being taken into the shift register 2. This prevents address data from shifting.

Therefore, data (0) to data (n _{-1) of the byte data setting in FIG. 10F corresponding to each of the data transfer circuits A0 to A o-1} in FIG.
Moreover, the byte data part is set to contain the data contents of each data register 16 in FIG.
Data is transferred to the control circuit 1 from the DATA-OUT signal, and the data transfer circuits A0 to A0 are transferred by the failure detection circuit 1a.
It can be confirmed whether the set data shown in FIG. 10D is set for each of A _o-1 .

〔Effect of the invention〕

By using the data transfer circuit of the present invention based on the above principle, it is possible to determine whether or not the address and data settings are reliably set in each data transfer circuit, and even in the event of an abnormality, the location can be easily identified. In addition, the number of signal lines connected to the control circuit 1 of FIG. 1 does not increase even if the number of addresses increases, which further improves workability and reliability.

[Brief explanation of drawings]

Figure 1 is a diagram showing the circuit configuration of a data transfer method, Figure 2 is a diagram showing the circuit configuration of a conventional data transfer circuit, and Figure 3 is a diagram showing the time t of the DATA-IN signal in Figure 1. Figure 4 is a diagram showing the timing chart of data transfer in
Figures 6 and 6 show timing charts when setting addresses in the data transfer circuit A _o-1 , and Figures 7 and 8 show timing charts when setting data in the data transfer circuit A _o-1. 9 shows the circuit configuration of the data transfer device according to the present invention, and FIG. 10 shows the DATA-transfer device according to the present invention.
A diagram showing the format of data input to the IN signal, Figures 11 and 12 are data transfer circuits.
₁₃ and 14 are diagrams showing timing charts at the time of setting byte data in the data transfer circuit A _o-1 . In the figure, 1 is a control circuit, 1a is a failure detection circuit, A0 to A _o-1 are data transfer circuits, 2 is a shift register, 3 is a data shift register, 4 is a U/D counter, and 5 is a start detection gate. 6 is a ternary counter, 7 is an m-ary counter, 8 is a mode register, 9 is a mode selector, 10 is a set end F/F circuit, 11 is a check bit determination circuit, 12 is a gate circuit for address set, 1
3 is an address register, 14 is an address comparison circuit, 15 is a data set gate circuit, 16 is a data register, 17 is a byte select gate circuit, 18 is a byte selector, 19 is a clock control circuit, 20 is a clock control gate circuit It is.
It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims] 1 In a data transfer line in which N circuits with the same circuit configuration are connected in series, the transfer data is set as start data indicating the beginning of the data, a mode for setting the data type, and an address for the N circuits. It consists of address data and setting data to be given to each circuit. First, start data, address setting mode, and N address setting data are transferred in this order. After setting addresses to N circuits, start data, Data setting mode, N
The data setting data are transferred in order to set the desired data in the registers built into the N circuits, and then the start data, the byte data setting mode, and the N byte data setting data are transferred in this order. The data that was set in the data setting mode in the register of each circuit is simultaneously transferred onto the transfer line, and the data is sent out in the data setting mode by a control circuit that is added externally.
A data transfer device characterized in that it is possible to check for abnormalities in circuits and transfer lines by comparing data read in a byte data setting mode and checking for a match.