JPH0122648B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is capable of detecting a word that matches an input word from among a large number of headwords stored in advance by electronic means, and outputting stored information corresponding to the matched headword. The present invention is applied to such electronic devices, and relates to a device for detecting a match between a headword and an input word. For example, in an English-Japanese electronic dictionary, an English word is stored as a headword, and a corresponding Japanese translation of the English word is also stored. Outputs the Japanese translation corresponding to the heading from among the heading words. In such devices, when storing headwords, translations, etc., in order to improve storage density, frequently occurring character strings, such as st and ing in English words, are encoded as single characters and matched. At the time of detection, the compressed code is converted to the original st or
ing to detect a match, or compress the input character string using the same method as the headword compression rule and then detect a match. However, all of these methods only detect a complete match between the input word and the character string of the headword. On the other hand, not only in English, but for headwords, words with the exact same meaning but spelled differently or with some letters or symbols missing are commonly used as a customary notation. There are cases,
There are cases where it is undesirable to specify the spelling exactly as entered. For example, there are synonyms with different spellings such as GRAY/GREY, and there are synonyms such as FOB/FOB that are synonymous even if a part of the spelling is omitted. In this way, when two or more types of notation exist, in a method for detecting a complete character string match, for example, words in all the notations for FOB and FOB must be recorded as headwords. However, in this method, it is necessary to record two or three or more words even though it is actually one word, and storage space is required accordingly. When detecting a match between a headword and an input word, the present invention eliminates certain characters or symbols from the character strings that make up the headword, such as FOB/FOB. There are two types of notation, and words that omit part of the character string from one of them are recorded in one word's worth of memory space, and no matter which type of notation is input, unrecorded words will be recorded. This is to prevent it from being processed as . Examples of synonyms in English that are the subject of the present invention are as follows. 1. Examples of notations that omit ``FOB/FOB PM/PM OK/OK 2 Examples of notations that omit ``E'' JUDGEMENT/JUDGMENT COOD-
BYE/GOOD-BY 3 Examples of notations that omit U LABOUR/LABOR COLOUR/COLOR
HONOUR/HONOR 4 Other examples TRAVELER/TRAVELER WAGGON/
WAGON OMELLETE／OMELET
ROUMANIA/RUMANIA In addition, examples of Japanese include the following. Note that the voiced sound symbol itself is usually treated as one character. 1 Examples of writings that omit the 〃 (voiced sound) Amethyst/Amethyst Smooth/Smooth 2 Examples of writings that add O (cha)/Ochiya (tea) Kaasan (mother)/Okaasan (mother) 3 Other Examples Transistor/Transistor Matrix/Matrix FIG. 1 shows an overall block diagram of an embodiment in which the present invention is implemented in a device for translating English words into Japanese. The input device 1 is alphabetic A to Z, dots, etc.
It is equipped with an input key for inputting symbols such as a hyphen. The translation instruction key 2 is a key operated when requesting to display the Japanese translation after inputting the spelling of an English word from the input device 1, and the address counter 5 is reset by inputting this key. The first memory 3 records English words serving as headwords, and the second memory 4 stores Japanese translations corresponding to each English word. An address counter 5 that indicates the address of the memories 3 and 4 corresponds to the address of the memories 3 and 4.
Read out the English words and their corresponding Japanese translations from 4. The match detection device 6 includes a register that temporarily stores the English word input from the input device 1 and the entry word output from the memory, compares the two, and outputs a match signal 7 when they match. If they do not match, a non-match signal 8 is output. The display device 9 displays the output contents of the memory 4 when the coincidence signal 7 is applied. In such a device, when a word is input from the input device 1, that word is stored in a register in the match detection device 6, and when the translation instruction key 2 is operated next, the address counter 5 is reset. Indicating the address of the first word, the first memory 3 therefore outputs the English word stored at the first address and another register in the match detection device 6 stores that English word. When the input word and the entry word do not match, the match detection device 6 outputs a non-match signal 8, and in accordance with this, the address counter 5 advances and indicates the next entry word. When such an operation is repeated and the input word and the entry word match, the match detection device outputs a match signal 7, the address counter 5 stops advancing, and the output of the second memory 4, that is, corresponds to the input word. Display Japanese translation. If the address advances to the last address without a match, the address counter 5 outputs a signal (not shown) for processing as non-recording. FIG. 2 shows a specific configuration of the coincidence detection device 6 of FIG. 1. In the figure, 11 is a register that stores the headword read out from the memory 3, and 12 is a register that stores the input word input from the input device 1. When storing words in these registers 11 and 12, the characters and symbols are encoded and stored as shown in Table 1, and the last part of the string is

【table】

[Table] The control code shown in Table 2 is the word register 11,1.
It is memorized every time it is memorized in 2. for example,
When APPLE is output from memory 3 or input device 1 and introduced into the register, register 11 or 1
2 stores a control code in the next digit (indicated by diagonal lines) after the end of APPLE, as shown in FIG. Note that this control code input circuit is not shown in FIG. In FIG. 2, 13 is an address counter that indicates the character string of the word stored in the register 11;
14 is an address counter that indicates the character string of the word stored in the register 12; These address counters 13 and 14 indicate the "0" character each time a new headword is introduced into the register 11, and the outputs of the AND gate 27 and OR gate 33 indicate the address of the next character. Registers 11 and 12 then output the characters at the addresses indicated by address counters 13 and 14. Reference numeral 15 denotes a control code detection circuit which detects when the code output from the register 11 is a control code and outputs a signal 19. 1
6 is a circuit that detects that the 0th bit of a character is "0", and when this is detected, a signal 20 is output.
Output. 17 outputs a signal 21 when the contents of the first to seventh bits of the characters output from registers 11 and 12 respectively match. Reference numeral 18 denotes a control code detection circuit which detects when the code output from the register 12 is a control code and outputs a signal 22.
23, 24, 25, 26 are inverters (NOT logic circuits), 27, 28, 29, 30, 31, 32
is an AND gate circuit, 33 and 34 are OR gate circuits, and 7 and 8 are the same signal and non-coincidence signal as in FIG. Figure 4 shows the method of storing headwords in memory 3 in Figure 1 using FOB/FOB and
OMELETTE/OMELET is shown as an example. When storing a headword, two types of character codes are used, as shown in Table 1: a complete match character code and an omissible character code. FOB／FOB
In the case of , use the non-abbreviated notation, that is, the code for the FOB that cannot be omitted, and use the code for the notation that can be omitted, that is, the three dots. OMELLETE／
The same is true for OMELET, but if the same letters are lined up and one of them can be omitted (LL→L, TT→T), the latter character is treated as an omissible character. In this way, the headword is stored in the memory 3. Note that the asterisk (*) in Figure 4 indicates characters that follow the encoding, and the parentheses () indicate characters and symbols that should use the optional character code. Characters in the following encodings are represented by adding parentheses. Next, the operation of the circuit configuration shown in FIG. 2 will be explained with reference to FIG. For example, from the input device 1 in FIG.
Assume that ABLE has been input. ABLE is stored in register 12, with a control code following the last character "E". Next, by operating the translation instruction key 2, the address counters 5 of the memories 3 and 4 are reset, and the first headword stored in the memory 3, for example ABHOR, is output and stored in the register 11. A control code is also included in this case. This state is shown in FIG. Further, since the new headword has been stored in register 11, address counters 13 and 14 of registers 11 and 12 are reset, and the contents of the 0th character of registers 11 and 12 are output. Note that each word stored in the register 11 is coded with a character that cannot be omitted. register 11,1
Since the outputs of the 0th character of 2 are both "A", the output 21 of the match detection device 17 is "1".
At this time, the other detection circuits 15, 16, and 18 do not output. Therefore, the AND gate 27 opens and increments the address counter 14, and also increments the other address counter 13 via the OR gate 33. Address counters 13 and 14 indicate the next character, ie, the first character. The character "B" is output from the register 11, the character "B" is also output from the register 12, and the match detection device 1 is outputted as before.
7 is output, AND gate 27 and OR gate 33 are opened to increment both address counters 13 and 14, and output the next characters "H" and "L". At this time, since all outputs of the detection circuits 15, 16, 17, and 18 are "O", the AND gate 31
opens and outputs the non-coincidence signal 8 via the OR gate 34. As a result of this non-matching signal, the address counter 5 outputs the next headword, the same non-matching signal is repeated, and eventually the memory 3 outputs the next headword.
ABLE is output and stored in register 11. As in the previous explanation, the characters are compared one by one starting from the 0th character, and after a match is made up to the final character "E",
When the control code is output from both registers 11 and 12, control code detection circuits 15 and 18 both output detection signals 19 and 22, AND gate 32 is opened and coincidence detection signal 7 is output. In the following example, MEET is input from input device 1, and MEET is input from memory 3 as a headword.
Assume that ME has been output. As shown in FIG. 5, the 0th character and the 1st character are both ME, so the AND gate 27 is opened, and when the next 2nd character is compared, the control code is output from the register 11 and the register 12 is Outputs E. Therefore, only the detection circuit 15 outputs "1", the AND gate 29 is opened, and the non-coincidence signal 8 is outputted via the OR gate 34. Next, FOB/FOB input will be explained.
In this case, since it is possible to input FOB or both, the headword is coded as shown in FIG. 4A. First, if you input FOB, as shown in Figure 5, F(・)O(・)B(・)
is stored with a control code, and the FOB is stored in register 12 with a control code. When the address counters 13 and 14 indicate the first character, the detection circuit 16 outputs it because the 0th bit of the (.) code is "0", and the 1st to 7th bits of the first character are Since they match, the detection circuit 17 also outputs an output. Therefore, only AND gate 27 is opened to increment address counters 13 and 14, respectively. In this way, if there is an optional character code in a certain digit of register 11, even if the 0th bit of the same digit in register 12 is "1", if the 1st to 7th bits are the same, the characters are the same. It is determined that the coincidence detection signal 7 is output. Next, if you omit the dot and simply enter FOB,
The contents of registers 11 and 12 are as shown in FIG. In this case, when the first character (.) and 0 are output, only the output 20 of the detection circuit 16 becomes "1", so the AND gate 28 opens and only one address counter 13 steps through the OR gate 33. proceed. As a result, a comparison between 0 and 0 is performed. In this way, when register 11 is an optional character code and both registers 11 and 1
When the contents of the 1st to 7th bits of 2 are different,
Since only the AND gate 28 is opened and only the address counter 13 related to the headword is incremented, only the omissible character code is shifted by one character, and finally the match detection signal 7 is output. According to the present invention, as described above, an omissible character is stored in the headword memory in advance as a code that can be determined, and when an omissible character appears in the match detection device between a headword and an input word, this corresponds to the omitted character. If it matches the character of the input word in the digit, it is judged as a match, and if it does not match, only the optional character is shifted and the comparison with the next character can be performed. Even without storing words redundantly in the headword memory, headwords can be found without being omitted in searches, reducing memory capacity as much as possible and increasing reliability. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the internal configuration of the coincidence detection device 6 of FIG. 1. Figure 3 is the second
FIG. 2 is a diagram illustrating the structure of words in registers 11 and 12 in the figure. FIG. 4 is a diagram illustrating the bit structure of a headword. FIG. 5 is an explanatory diagram of the operation of FIG. 2. 1... Input device, 3... Memory for headwords,
4...Memory of data corresponding to headword, 5
... Address counter, 6 ... Match detection device, 9
...Output device, 11...Headword register, 1
2...Input word register, 15, 16, 17, 1
8...Detection circuit.

Claims (1)

[Claims] 1. In an electronic device that detects a word that matches an input word from among a large number of headwords pre-stored in a memory and outputs stored information corresponding to the matched headword, a memory for storing headwords composed of allowed characters and exact matching characters; and a determining means for determining omissible characters of headwords stored in the memory;
Comparison means for shifting the optional character and comparing the next character with the constituent characters of the input word when the characters constituting the headword are optional characters and do not match the constituent characters of the input word. A headword matching detection device characterized by: