JPH0123827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an identification control device for a paper sheet recognition machine that identifies paper sheets such as banknotes and sheets.

(Prior Art) Conventionally, a normal banknote validating machine searches the paper surface of a conveyed banknote using a photoelectric detection device or a magnetic detection device installed in a conveyance path, and detects printed patterns, watermarks, and magnetic properties obtained from these detection devices. It is configured to identify the authenticity or denomination of the banknote based on the distribution of the material, etc., but in order to more accurately search for patterns and distribution, a clock with a shorter cycle is used.
A conceivable method is to count clocks after a certain detection signal is obtained, and then determine whether or not the pattern or distribution is a predetermined one, depending on whether or not the next detection signal is obtained within a predetermined range.

(Problems to be Solved by the Invention) However, when using this method, there is a drawback that accurate identification is not possible if the conveying speed of the banknote changes. If a clock synchronized with the conveyance speed of banknotes is used, it is possible to cope with changes in the conveyance speed, but such a clock has a long cycle and cannot be directly applied to the above method.

In addition, in the above method, the timing at which a detection signal is obtained changes even when the bill is conveyed in an oblique position due to diagonal insertion into the conveyance path, etc., so accurate identification is not possible and it is difficult to identify a genuine note as a genuine note. As the pass rate decreases, the possibility of distinguishing the denomination from other denominations with similar patterns and other features increases, which causes a decrease in reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a recognition control device for a paper sheet recognition machine that can perform accurate recognition even if the conveyance speed changes or the banknotes are skewed.

[Structure of the invention]

(Means for Solving the Problems) The identification control device for a paper sheet identification machine according to the present invention includes:
A paper sheet identification device configured to identify the paper sheets by searching the pattern of the paper sheets being conveyed, which includes: a) a speed detection signal of pulses having a period length synchronized with the conveyance speed of the paper sheets; a speed detection signal generating means for generating MS; b) a skew amount detecting means for detecting the amount of skew of the paper sheets to be conveyed; and c) the speed detection signal generating means for searching the pattern of the paper sheets. A search clock whose cycle is shorter than that of the speed detection signal MS is based on the speed data from the skew amount detection means and the skew data from the skew amount detection means.
d) a pattern detection signal that outputs a pattern detection signal DS according to the pattern of the paper sheet; e) after the pattern detection signal DS is obtained, the search clock CM is counted and a predetermined number of search clocks are generated. identification means for outputting an identification signal CS when the next pattern detection signal DS is obtained within the count value range of the search clock;
It is characterized in that the CM is changed according to the conveyance speed of paper sheets and the amount of skew.

(Function) A clock with a short period is changed according to the conveying speed of the banknote and the amount of skew of the banknote, and this search clock is counted after a pattern detection signal is obtained, and when the counted value is within a predetermined range. The identification signal is obtained depending on whether or not the next pattern detection signal is obtained.

(Example) FIG. 1 shows a schematic configuration of a banknote validator according to the present invention, in which a conveyor belt 3 is wound around conveyor rollers 1 and 2 that are rotated by a drive motor (not shown). A speed detection plate 5 having cutting teeth 4 for detecting the transport speed over the entire circumference is attached to the transport roller 1. A magnet 6 for magnetizing the incisor teeth 4 is disposed around the speed detection plate 5, and a detection head 7 for detecting the magnetism of the incisor teeth 4 is also disposed. The detection head 7 detects the magnetism of the incisor 4 and outputs a pulse signal, and these constitute a speed detection signal generating means. Magnetic heads 11 and 12 are provided above and below the center of the transport section of the transport mechanism 10 as pattern detection means for magnetically detecting the patterns on the front and back sides of the banknotes being transported. Further, the bill insertion portion of the conveyance mechanism 10 is equipped with a photoelectric bill detector 13 for detecting the inserted bill IT, and a skew amount provided at both ends of the conveyance belt 3 for detecting the oblique posture of the bill IT. Photoelectric banknote detectors 14 and 15 forming part of the detection means are provided, and the banknotes are transported in the N direction by the transport mechanism 10, and the inserted banknotes IT are detected by a separate control circuit system. The banknotes are either accepted as good banknotes AT or returned as bad banknotes RT.

Next, the configuration of the search clock generating means and identifying means according to the present invention will be explained with reference to FIGS. 2A and 2B.

The clock generator 20 includes a crystal oscillator 21 that oscillates at a stable frequency of 4MHz, and a crystal oscillator 21 that oscillates at a stable frequency of 4MHz.
The clock pulse CP1 from
The banknote detection signals 14S and 15S from the MS and banknote detectors 14 and 15 are respectively input to the flip-flop circuit 8, and the speed detection signal MSB, which is the _O1 output, is sent to the BCD counter 3 of the conveyance counting circuit 30.
The signals are input to load terminals LD 1 and 32, respectively. Therefore, the outputs of the counters 31 and 32 are once latched by the latch circuit 33, and then are input to the input terminals of the parallel adder circuit 41 constituting the correction calculation circuit 40.
Input to _B1 to _B8 . Furthermore, the banknote detection signal 14 which is the _O3 output of the flip-flop circuit 8 is
The SA is input to the OR circuit 51 and the AND circuit 52 in the skew counting circuit 50, and the banknote detection signal 15SA, which is the _O4 output, is also input to the OR circuit 51 and the AND circuit 52. Thus, the output of the OR circuit 51 is input to the D terminal and the clear terminal CLR of the D-type flip-flop 53, and is input to the AND circuit 54 and the load terminal LD of the BCD counter 55. is input to the clock terminal CK. Also,
The Q output of the flip-flop 53 is connected to the AND circuit 54.
and the output of this AND circuit 54 is BCD
It is input to the CKE terminal of the counter 55. The output (Q _c , Q _d ) of the BCD counter 55 is sent to the parallel adder circuit 4
1, and the addition result of this parallel addition circuit 41 is input to the input terminals A ₁ and A ₂ of the parallel addition circuit 41.
The count coincidence signals CN1 and CN2 of these counters 61 and 62 are inputted to the D terminal of a D-type flip-flop 64 via an AND circuit 63. Furthermore, the Q output of the flip-flop 64 is output to the BCD counter 6.
The clock is input to each load terminal LD of 1 and 62, and is also input to the flip-flop circuit 7 in the latch control circuit 70 as the search clock CM via the buffer 65.
It is input to the _I4 terminal of 1. In this flip-flop circuit 71, the clock pulse CP2 is inputted to the clock terminal CK, the pattern detection signal DS from the magnetic head 12 or 11 is inputted to the input terminal _I1 , and the _O4 output of the flip-flop circuit 71 is input to the period counting control circuit. It is input to the clock terminal CK of the counter 81 in the counter 80. Further, the output signal DT1 of the AND circuit 72 that processes the Q ₁ to _{Q 3} outputs of the flip-flop 71 is input to the AND circuit 84, the output signal DT2 of the AND circuit 74 is input to the clear terminal CLR of the counter 81, and the OR circuit 8
2 to the reset terminal R of the flip-flop 83.
is input. However, flip-flop 83
The Q output is input to an AND circuit 84, and output from this AND circuit 84 as an identification signal CS.

By the way, the BCD counters 31, 32, 61, and 62 each output the terminals I A to ₆₂ at the rising edge (L→H) of the signal applied to the load terminal LD.
The input data of _ID is preset, and the pulse signals to the clock terminal CK are counted until the preset value is reached, and when the counters 61 and 62 reach the counted value, they output match signals CN1 and CN2. Also,
The CKE terminal of the counter 55 performs a counting operation only when the signal applied thereto is at H level, and holds the counted value when it goes to L level. Furthermore, the flip-flop circuits 8 and 71 incorporate four flip-flops, and the signals at the input terminals _I1 to _I4 are sent to the clock terminals.
Corresponding to the signal input to CK, the same level signals are output from output terminals _O1 to _O4, respectively.

The carrier counting circuit 30 also includes BCD counters 31 and 32 that count the cycle length of the speed detection signal MS (approximately 2 KHz) output by the detection head 7 using a clock pulse CP2, and BCD counters 31 and 32 that count the cycle length of the speed detection signal MS (approximately 2 KHz) output by the detection head 7, and count the cycle length of the speed detection signal MS (approximately 2 KHz) every time the speed detection signal MS is input. The latch circuit 33 memorizes and holds the clock cycle length until the clock cycle length of the clock is counted. It is now converted and output. Furthermore, after either of the banknote detectors 14 and 15 detects a banknote, the skew counting circuit 50
and 15 both detect the banknote, and count the speed detection signal MS as the amount of skew of the banknote, and store and hold this counted value until the next banknote is detected. The correction calculation circuit 40 is the conveyance counting circuit 30
Based on the speed data corresponding to the transport speed output by the skew counter circuit 50 and the skew data outputted by the skew counting circuit 50 corresponding to the amount of banknote skew, the cycle length of the search clock required for searching for the characteristics of the banknote is determined. The correction counting circuit 60 uses the period length data of the search clock output from the correction calculation circuit 40 and the clock generator 20.
A necessary search clock CM is formed based on the clock pulse CP1 outputted by the search clock CM. in this case,
When the clock pulses CP1 are counted up to the period length data value outputted by the correction calculation circuit 40, the search clock CM is outputted, and the period length data is again output from the correction calculation circuit 40 by the signal corresponding to this search clock CM. When the clock pulse CP1 is counted up to this value, the next search clock CM is sent out, and the same operation is repeated thereafter. In other words, this search clock
The cycle length of the CM is controlled to increase or decrease in a predetermined relationship based on the conveyance speed of the conveyance mechanism 10 and the skew amount of the conveyed bill.

On the other hand, the latch control circuit 70 receives the pattern detection signal DS.
It is controlled by a clock pulse CP2 having a frequency higher than that of the search clock CM, and the circuit operation is prohibited by a clear signal CR except during banknote identification operations. When the pattern detection signal DS is input as an H level pulse, the H level signal DT1 is outputted in synchronization with the clock pulse CP2, and then the signal DT2 is outputted as a signal each having a length of one clock. Further, when the signals DT1 and DT2 based on the pattern detection signal DS are input, the period counting control circuit 80 serving as an identification means counts the search clock CM until the next signal DT1 is input after the signal DT2, and also counts the search clock CM until the next signal DT1 is input after the signal DT2. The next signal DT1 is output as the identification signal CS only when the numerical value is within a predetermined value range, and the identification signal CS is not output when the next DT1 is not input within the predetermined allowable count value.
Note that the allowable count value "146 to 154" of the counter 81 is predetermined in accordance with the denomination of the banknote. That is, the allowable count value can be arbitrarily changed depending on the type of banknote to be identified.

In such a configuration, a case where banknotes are conveyed in an oblique position will be described with reference to FIG. 3A.

After the banknote detector 15 detects the banknote IT, the transfer distance until the other banknote detector 14 detects the banknote IT is _l1 , and the banknote detectors 14 and 1
₅ , the length of the banknote detected by the banknote detector 14 is _l2 , and the length of the banknote IT is _l3 , then the banknote lengths _l2 and _l3
The relationship is as shown in the following equation.

Note that the line connecting the banknote detectors 14 and 15 is perpendicular to the transport direction N.

On the other hand, FIG. 3B shows another embodiment of FIG.
4, 15A or 14A, 15, when the 14A-15A line is parallel to the 14-15 line and the gap between these two lines is _l4 , and the banknote detectors 14A and 15 are configured, The above 1 equation becomes the following 2 equations.

Note that these two types show the case where the banknote detector 14A does not detect a banknote at a timing earlier than 15, and for other cases where the banknote detector 14A detects a banknote at a timing earlier than 15,
A similar result can be obtained by modifying the above equation 1.

Here, the present invention uses magnetic heads 11 and 12 provided at the rear stage to detect the magnetic field of the banknote surface based on the transfer difference _l1 between the two banknote detectors 14 and 15 arranged at an interval _l0 . The pattern spacing is detected as the true magnetic pattern spacing of the banknote. Note that in this example, the third
Assume that the configuration is as shown in Figure A.

When the transport mechanism 10 starts operating, the clock pulse CP1 and the clock pulse CP1 are generated from the clock generator 20.
At the same time that CP2 is output, a speed detection signal MS corresponding to the transport speed is output from the detection head 7. This speed detection signal MS (H level) is input to the _I2 terminal of the flip-flop circuit 8, and the H level signal MSA is output from the _O2 terminal at the timing of the clock pulse CP2. _I1 terminal of circuit 8 and clock terminal of BCD counter 55
Input to CK. The input of the _I1 terminal is output to the _O1 terminal at the next timing of clock pulse CP2,
This MSB signal loads BCD counters 31 and 32, and BCD counters 31 and 32 start counting clock pulses CP2. The count values of the counters 31 and 32 are latched by the latch circuit 33 at the _O2 output of the flip-flop 8 in response to the next speed detection signal MS.

On the other hand, the banknote detectors 14 and 15 detect the conveyance of the inserted banknote IT as described above, and these detection signals 14S and 15S are input to the flip-flop circuit 8, and the output thereof is input to the OR circuit 51 and the AND circuit 52. has been done. However, OR circuit 5
The output of the AND circuit 52 is connected to the D terminal of the flip-flop 53, and the output of the AND circuit 52 is connected to the D terminal of the flip-flop 53.
Since each input is input to the CK terminal, if the inserted banknote IT is slanted, the input timing will be shifted. After the D terminal becomes H level, the flip-flop 53 is inverted by the H level input to the CK terminal. Here, when the D terminal is at "L" level, that is, the banknote detector 14 or 1
5 does not detect a banknote, the flip-flop 53 is cleared and its Q output is "H" and is input to the AND circuit 54. When either of the banknote detectors 14 and 15 detects a banknote, the output of the OR circuit 51 becomes "H", and the output of the AND circuit 54 becomes "H", so that the counter 55 becomes ready for counting operation. . At this time, the load terminal LD of the counter 55 is also at "H". Thus, the counter 55 starts counting the speed detection signal MSA from the detection head 7 from the moment the bill is detected. When the two banknote detectors 14 and 15 detect a banknote, the output of the AND circuit 52 becomes "H", which inverts the flip-flop 53, and the output of the AND circuit 54 becomes "L". The coefficients of counter 55 are stopped, which makes it possible to obtain the length l ₁ of FIG. 3A.

The count value of the counter 55 is input to the parallel adder circuit 41 and added to the value from the latch circuit 33.
This addition data is preset in counters 61 and 62, and the counters count clock pulses CP1. Then, when this count value reaches the preset value mentioned above, a match signal (Z terminal) is output,
The signal is inputted to the D terminal of the flip-flop 64 through the AND circuit 63. As a result, the flip-flop 64 outputs D at the timing of clock pulse CP1.
Outputs the terminal level and obtains the search clock CM. Also, since this is the load signal for the counters 61 and 62, the addition data of the parallel addition circuit 41 is preset again. In this way, signals corresponding to the transport speed and corrected by the amount of skew are sequentially sent out as search clocks CM.

Such search clock CM (FIG. 5A) is input to the _I4 terminal of the flip-flop circuit 71, and its _O4
The output is input to a counter 81 and counted. On the other hand, the pattern detection signal DS (FIG. 4A) is input to the _I1 terminal of the flip-flop circuit 71 (at the point in time in FIG. 4).
_t1 ), and at the timing of the next clock pulse CP2 (time _t2 in Figure 4), the input "H" is output from the _O1 terminal and input to the AND circuit 72 and the _I2 terminal (Figure 4B). . The input "H" of this _I2 terminal is the timing of the next clock pulse CP2 (time _t3 in Figure 4).
The signal is output from the _O2 terminal and input to the inverter 73, AND circuit 74, and _I3 terminal (FIG. 4C).
Furthermore, the input "H" of this _I3 terminal is similarly outputted as a signal KM3 at time _A4 in FIG.
Figure D). Here, the output of the AND circuit 72
DT1 becomes "H" at the timing from time t ₂ to t ₃ in FIG. 4E, and the output DT2 of the AND circuit 74 becomes "H" at the timing from time t ₃ to t ₄ in FIG. The AND circuit 84 receives the signal DT2.
passes through the OR circuit 82 to the R of the flip-flop 83.
are input to each terminal. Therefore, the count value of the counter 81 in the flip-flop 83 is "146".
Since it is set at ``154'' and reset at ``154'', the Q output KC of the flip-flop 83 becomes ``H'' at time _t0 , as shown in FIG. 4G. Then, when the signal DT2 is output (time _t3 ), the flip-flop 83 is reset, but while it is at "H", the flip-flop ₈₃ is
The identification signal CS is output at _t3 . In other words, as shown in FIGS. 5A to 5D, when the pattern detection signals DS are input sequentially, the next pattern detection signal DS is within a predetermined count value range based on the count of the search clock CM from the front end of each pattern detection signal DS. It is determined whether or not the leading edge is input, and this is output as an identification signal CS.
Therefore, this identification signal CS indicates that the banknote is of a specific denomination. Note that this identification signal CS may be counted and the counted value may be used to identify a specific denomination.Alternatively, a banknote may be divided into multiple parts and the counted value of each part may be compared to identify a specific denomination. It's okay. In this case, the pattern is determined by comparing it with a pattern previously stored in a separate memory.

Here, in this invention, even if the pattern detection signal DS changes as shown in FIG. 5E due to the conveyance speed or skew, the period length of the search clock CM also changes as shown in FIG. 5F. , thereby identifying the identification signal
CS can be reliably output (Figure 5G).

〔Effect of the invention〕

As described above, according to the present invention, the search clock whose cycle is shorter than the speed detection signal whose cycle length is synchronized with the conveyance speed of the paper sheet is changed in accordance with the conveyance speed of the banknote and the amount of skew of the banknote. This allows for more accurate pattern detection and accurate identification.

[Brief explanation of drawings]

Fig. 1 is a mechanical diagram showing an example of the configuration of a banknote detection unit and a banknote transport unit of the present invention, Figs. 2A and B are circuit diagrams showing an example of a control system thereof, and Figs. 3A and B are banknotes of this invention. Diagram 4 for explaining an example of the operation of the detection unit
Figures A to H and Figures 5A to G are time charts showing operation examples of the present invention, respectively. 1, 2... Conveyance roller, 3... Conveyance belt, 4
... Incisor, 5 ... Speed detection plate, 6 ... Magnet, 7 ... Detection head, 6 ... Flip-flop circuit, 10 ... Conveyance mechanism, 11, 12 ... Magnetic head, 13-15 ... Banknote detection device, 20... clock generator, 21... crystal oscillator, 22... frequency divider, 30... carrier counting circuit, 31, 32...
BCD counter, 33...Latch circuit, 40...
Correction calculation circuit, 41... Parallel addition circuit, 50...
Diagonal counting circuit, 53...Flip-flop, 55
... BCD counter, 60 ... Correction counting circuit, 6
1, 62... BCD counter, 64... Flip-flop, 65... Inverter, 70... Latch control circuit, 71... Flip-flop circuit, 80
...Period counting control circuit, 81...Counter, 83
...Flip flop.

Claims (1)

[Scope of Claims] 1. A paper sheet identification machine configured to identify paper sheets by searching the pattern of the paper sheets being conveyed, which includes: a) a cycle length synchronized with the conveyance speed of the paper sheets; (a) a speed detection signal generating means for generating a pulse speed detection signal MS consisting of; (b) a skew amount detection means for detecting the amount of skew of the conveyed paper sheet; (c) for searching the pattern of the paper sheet. , a search clock having a shorter period than the speed detection signal MS based on the speed data from the speed detection signal generating means and the skew data from the skew amount detection means;
d) a pattern detection unit that outputs a pattern detection signal DS according to the pattern of the paper sheet; e) counting the search clock CM after the pattern detection signal DS is obtained; Identification signal when the next pattern detection signal DS is obtained within the predetermined count range
1. An identification control device for a paper sheet discriminator, comprising: an identification means for outputting a CS, and the search clock CM is changed in accordance with the conveyance speed and skew amount of the paper sheet.