JPS5847078B2 - banknote identification device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a banknote identification device that identifies the type and authenticity of banknotes by determining the continuity of pattern detection signals obtained from banknotes.

In conventional devices that identify the type and authenticity of a banknote from the pattern of the banknote, it is determined whether the pattern detection signal obtained from the banknote continues for a predetermined period of time after a certain period of time. Banknotes are identified based on whether or not a predetermined number of patterns are consecutively spaced at regular intervals.

In this way, since the interval between the banknote patterns is simply considered as the time interval of the pattern detection signal, if the conveyance speed of the banknote changes for some reason, the time interval at which the pattern detection signal is obtained will change. However, even though the patterns on banknotes are continuous at regular intervals, they are mistakenly judged to be discontinuous.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a banknote identification device that does not have these drawbacks.

This invention will be explained below.

The present invention relates to a banknote identification device, and as shown in FIG.
A pattern detection device 10 for detecting the pattern of banknotes, and each time a pattern detection signal PDA obtained from this pattern detection device 10 is input, elapsed time signals TPI to TP3 of a predetermined time width are inputted when the pattern detection signal PDA is input. A time signal generating device 20 generates a signal after a predetermined time period corresponding to the transport speed of the banknote, and when the time elapsed signals TPI to TP3 are obtained, it counts when the next pattern detection signal PD is obtained, and also generates a time elapsed signal TPI. A frequency counting device 30 is provided which clears the counting contents when the next pattern detection signal PD is obtained when ~TP3 is not obtained, and the pattern detection signal P is determined based on the counting contents of this frequency counting device 30.
It is determined whether or not D is obtained continuously for a predetermined time at predetermined time intervals, thereby identifying the authenticity of the banknote.

Here, the pattern detection device 10 includes a magnetic head 11 that scans the surface of a banknote being conveyed, and a waveform shaping circuit 12 that amplifies and shapes a detection signal from the magnetic head 11.
Then, when the output signal WF from the waveform shaping circuit 12 rises (or falls), a one-shot circuit (single) outputs a pulse width Norse signal that is sufficiently shorter than the width of the output signal WF as the pattern detection signal PD. It is composed of a stable multivibrator) 13 and a delay circuit 14 that delays the pattern detection signal PD for a short time and outputs it.

The elapsed signal generation device 20 also includes a reference clock signal forming device 200 that forms and outputs a reference clock signal SCL (described later), a counter 21 that counts the reference clock signal SCL, and a flip-flop that reads the counted value of the counter 21. a counter reading circuit 22 that outputs set signals ST1 to ST3 and reset signals R31 to R83;
It is composed of flip-flops 26-28.

Note that the reset signals R81 to R83 are sent to the OR circuit 2 along with the pattern detection signal PDA from the pattern detection device 10.
3 to 25, and is input to each reset terminal R of flip-flops 26 to 28.

The reason why the three flip-flops 26 to 28 that output the elapsed time signals TP1 to TP3 are provided here is to identify three types of banknotes (-1,000 yen, whole yen, and 10,000 yen).

Furthermore, the frequency counter 30 is composed of a frequency counter 300 for 10,000 yen banknotes, a frequency counter 310 for round yen banknotes, and a frequency counter 320 for 10,000 yen banknotes. The containers 300, 310, and 320 have the same configuration.

Therefore, the frequency counter 300 will be explained here. This frequency counter 300 counts an AND circuit 301 which inputs the pattern detection signal PD and the elapsed time signal TP1, and an identification signal ND1 which is the output of this AND circuit 301. A counter 305, a NOR circuit 302 that receives the output of the counter 305 and the elapsed time signal TP1, an AND circuit 303 that receives the output of the NOR circuit 302 and the pattern detection signal PD, and the output of the AND circuit 303 and banknotes. It is composed of an OR circuit 304 that resets a counter 305 by inputting a signal obtained from the output of the division point signal NTD through a delay circuit 50.

Further, a discriminator 40 is provided downstream of the frequency counter 30, and discriminators 400, 410, 420 for each denomination are provided.
Equipped with:

Thus, the discriminator 400 has a shift register 401 that shifts and stores the output state of the counter 305 at that time every time the banknote dividing point signal NTD is input, and a banknote when the contents of the shift register 401 are predetermined contents. Selector circuit 40 that outputs discrimination signal CN1 (-1000 yen banknote)
2, and the discriminators 410 and 420 have a similar structure, and each has a banknote identification signal CN2 (
Outputs egg yen banknotes) and CN5 (10,000 yen banknotes).

Note that the reference clock signal forming circuit 200 generates a reference clock signal SCL with an extremely short period corresponding to the speed of the transport mechanism that transports banknotes. For example, when a banknote is moved by 17 nm by the transport mechanism, about 100 A reference clock signal pulse is generated.

Further, the counter 305 of the frequency counter 300 counts the identification signal ND1 from the AND circuit 301, and when the counted value reaches the predetermined value, outputs an "H" level signal to the shift register 401 of the discriminator 400 in the subsequent stage. and
It is detected whether a predetermined number of consecutive patterns (for example, vertical stripes) are present at a certain interval.

The counter 305 transmits the banknote dividing point signal NTD to the delay circuit 50.
The banknote dividing point signal NTD is reset by the delayed signal and the output of the AND circuit 303, but this banknote dividing point signal NTD is separately output every time the banknote moves a predetermined distance from the start of recognition, for example, every time the banknote reaches a position where it is divided into 10 parts. It has become.

Furthermore, the selector circuit 402 is constituted by a decoder that receives, for example, the binary output of the shift register 401 in parallel and converts it into a decimal number.

On the other hand, as shown in FIG. 2, the reference clock signal generation device 200 includes a synchronization signal generation mechanism 20 that generates a synchronization signal synchronized with the drive operation of the conveyance mechanism section CN that conveys the banknotes 205.
9, a synchronization signal detection circuit 214 that detects a synchronization signal and generates a division signal DS, and a clock signal H that is not synchronized with the drive operation of the transport mechanism section CN and has a shorter period than the synchronization signal.
1 and H2, and a control clock signal CCL, a counter 216 that counts the clock signal H1 while the division signal DS is obtained from the synchronization signal detection circuit 214, and this counter 216.
A launch circuit 217 that stores the counted value CV of
It consists of a counter 218 that generates a reference clock signal SCL and reloads the value of the latch circuit 217 using this reference clock signal SCL, and a control circuit 213 that controls the operation of each of the circuits described above using a control clock signal CCL. Thus, the reference clock signal SC synchronized with the transport mechanism section CN
This is to obtain L.

Here, the transport mechanism unit CN includes a pair of upper and lower transport bells) 201
.

201A, and pulleys 202, 202A, which are driven by a motor 203.
An identification unit 204 is disposed between 201 and 202A, and the banknotes 205 are conveyed by the conveyance bell) 201 and 201A.
are inspected optically or magnetically.

Further, a gear 207 is attached to one of the pulley shafts 206 of the conveyance mechanism section CN, and a permanent magnet 208 as a magnetizing means is disposed near this gear 207. The permanent magnet 208 constitutes a synchronization signal generation mechanism 209 that generates a synchronization signal synchronized with the drive operation of the transport mechanism section CN.

Furthermore, a magnetic head 210 is provided near the gear 207 for detecting the magnetized state as a synchronization signal, and the detection signal is input to a waveform shaping circuit 211 including an amplifier circuit, and after being waveform-shaped, it is sent to a counter. 212.

Thus, when the counter 212 counts two pulses of the synchronization signal, it outputs the division signal DS, and when this division signal DS is input to the control circuit 213, it is cleared by the reset signal R81 to prepare for the next count. This function takes into account the variation error in the pitch of the teeth of the gear 207 and averages out the pitch error.

The magnetic head 210, waveform shaping circuit 211, and counter 212 constitute a synchronous signal detection circuit 214.

On the other hand, the clock signal generation circuit 215 generates the clock signal H1.
and R2 (>Hl) and a control clock signal CCL, and the counter 216 counts this clock signal H1 and is cleared by a reset signal R82 from the control circuit 213.

Further, the latch circuit 217 latches the count value Cv of the counter 216 based on the latch signal LT from the control circuit 213, and the counter 218 loads the value latched in the latch circuit 217 based on the load signal LD from the control circuit 213. At the same time, the clock signal H2 from the clock signal generation circuit 215 is counted, and when the counted value reaches the above load value, a coincidence signal is outputted as the reference clock signal SCL.

Note that the latch signal LT is outputted before the division signal DS is outputted from the synchronization signal detection circuit 214 and the counter 216 is reset, and the latch signal LT is outputted from the synchronization signal detection circuit 214 before the counter 216 is reset.
A load signal LD is output from the control circuit 213 to the counter 218 by CL, and the value of the latch circuit 217 is loaded into the counter 218 again.

Note that the above-mentioned banknote division point signal NTD is output when the division signal DS is counted after the start of the discrimination operation and the counted value reaches a predetermined value.

Here, first, such reference clock signal forming device 200
The operation will be explained with reference to FIGS. 3A to 3E.

When the transport mechanism section CN is driven by the motor 203, a synchronization signal is generated from the synchronization signal generation mechanism 209, and a synchronization signal as shown in FIG. 3A is input to the counter 212 via the magnetic head 210 and the waveform shaping circuit 211. be done.

The counter 212 outputs the division signal DS to the control circuit 213 when it counts two pulses of the synchronization signal as shown in FIG. Reset signals R81, R82 and latch signal L
T and further outputs a load signal LD.

The clock signal generation circuit 215 also generates a lock signal H1 (for example, 20 KHz) as shown in FIG. 3C, and a lock signal H2 having a higher frequency as shown in the same figure.
(for example, 200 KHz), which are counted by counters 216 and 218, respectively.

Here, when the division signal DS is given to the control circuit 213, the control circuit 213 first resets the counter 212 by the reset signal R81, and outputs the latch signal LT to set the count value Cv of the counter 216 (at the time point in this example). In tn, =l s o I+) is used as latch circuit 2
17 to memorize it.

Thus, after the count value C is stored in the latch circuit 217, the control circuit 213 sends the reset signal R to the counter 216.
82 and reset the counter 216.

This operation is performed every time the division signal DS is obtained, and the latch circuit 217 stores a value corresponding to the speed of the transport mechanism section CN.

The counter 218 receives the load signal LD from the control circuit 213 after outputting the reference clock signal SCL, and receives the value ("so") stored in the latch circuit 217.
”), and from this time the clock signal H2 is counted, and when it reaches the loaded value, the next reference clock signal SCL is output.

The value of the latch circuit 217 is loaded again by this reference clock signal SCL, and the same operation is repeated thereafter.

Here, in this example, the period of the clock signal H2 is set to 1/10 of the clock signal H1, so the reference clock signal SCL has a time that is 1/10 of the time required for two teeth of the gear 207 to pass. One pulse will be output.

In other words, if the conveyance speed remains unchanged, ten pulses of the reference clock signal SCL will be output until the next division signal DS is obtained (FIG. 3E).

Similarly, if the period of the clock signal H2 is set to 1/100, that is, 100 times the frequency of the clock signal H1, a reference clock signal SCL of 100 pulses can be obtained between the division signals DS.

The above description is based on a case where the conveyance speed is constant, but next, a case where the conveyance speed of the conveyance mechanism section CN changes (in this case, it becomes slower) will be explained.

As the transport speed becomes slower, the time required to obtain the next sorting signal DS becomes longer, so the input timing of the reset signal R820 to the counter 216 is delayed from the previous time
16, the clock signal H1 is counted more than the previous time (for example, 1'90").

Then, when the synchronization signal detection circuit 214 outputs the division signal DS, the control circuit 213 outputs the latch signal LT, and the latch circuit 217 outputs the count value Cv(
"'90"1) is stored (time tn+,).

Therefore, the latch circuit 217 receives this new value (90II
) is output from the counter 218, the counter 218 loads this new value (If 901+), and when it counts the clock signal H2 up to this value, it outputs the next reference clock signal SCL.
will be output, but this will take longer than the previous time.

Here, since the speed of the transport mechanism section CN is high and the gear 207 is also rotating at a high speed, the time interval at which the classification signal DS is obtained does not change abruptly even if the transport speed changes.

Therefore, even when the conveyance speed becomes slow, the latch circuit 21
The values stored in 7 gradually increase, and the period of the reference clock signal SCL changes every time the value of the latch circuit 217 is updated (at time ET11 y jn , tH+1 j・
・・・－・・・・・・) It gets longer.

Conversely, when the transport speed becomes faster, the period of the reference clock signal SCL becomes shorter.

Thus, the reference clock signal forming device 200 obtains a reference clock signal that is synchronized with the transport speed and has a higher frequency than the division signal.

Next, the operation of the apparatus shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

When the banknote 205 is sent to the conveyance mechanism unit CN and reaches the position of the identification unit 204, a separate detection means detects this and from this point on outputs the banknote dividing point signal NTD.
Start counting S.

Also, at this time, the counter 21. flip flop 26~2
8. Counters 305 to 325 and shift register 401
.about.421 are each initialized.

On the other hand, the magnetic head 11 of the pattern detection device 10 comes into contact with the surface of the banknote, but since there is no printed pattern (for example, vertical stripes) on the edge of the banknote, no detection signal is obtained yet.

As a result, the bill 205 moves further and the magnetic head 11
When detecting a pattern, the one-shot circuit 1 is activated at the rising edge of the pulse signal WF output from the waveform shaping circuit 12.
3 outputs a narrow pulse width pattern detection signal PD (FIG. 4A), and the delay circuit 14 also outputs a pattern detection signal PDA with an instantaneous delay.
1 and flip-flops 26-28 are each reset.

Therefore, the counter 21 is connected to the reference clock signal forming device 2.
Counting the reference clock signal SCL from 00, the counter reading circuit 22 either sets the flip-flops 26-28 at the subsequent stage depending on the count contents of the counter 21, or resets the flip-flops 26-28 via the OR circuits 23-25.

For example, the flip-flop 26 for -1,000 yen banknotes is set when the count value of the counter 21 reaches If 20 If, and is reset when the count value of the counter 21 reaches "+251+," and the flip-flop 27 for round 1,000 yen banknotes is set at the counter 20.
It is set when the 1 value of 1 becomes II 30 II, and is reset when it becomes If 35 If.

In addition, the flip-flop 28 for the ten thousand yen bill is connected to the counter 2.
It is set when the count value of 1 becomes If 25 II, and reset when it becomes If 28It.

Now, the counter 21 outputs a reference clock signal SC of 24 pulses.
When counting L, when the next pattern is detected by the magnetic head 11, the one-shot circuit 13 outputs the pattern detection signal PD, but since only the flip-flop 26 is set, this pattern detection signal PD
passes only through the AND circuit 301, thereby incrementing the counter 305 (FIG. 4D, for example, at time T9).

At this time, since the output of the NOR circuit 302 is at the rLJ level, the output of the AND circuit 303 is also at the "L" level, and the counter 305 is not reset even if the pattern detection signal PD is input.

Therefore, when the next pattern detection signal PD is obtained, TI
If the flip-flop 26 is set to O, the counter 305 is incremented again (FIGS. 4A-D).

In this way, when a predetermined number of consecutive pattern detection signals PD (in this example, 18 degrees) are obtained (times T9 to T1),
6) When the counter 305 finishes counting (time T16)
The rHl level is outputted to the shift register 401 and the NOR circuit 302.

Thus, when the output of the counter 305 reaches the rHJ level and is input to the shift register 401 in the discriminator 400, it is sequentially shifted by the banknote division point signal NTD.

In addition, after counting a predetermined number, that is, once the counter 305 has reached rH
When the output reaches l level, the counter 305 does not perform counting operation after that, and when the banknote dividing point signal NTDA from the delay circuit 50 is input to the OR circuit 304 (
It is reset at time T19).

In this way, banknotes can be identified according to their dividing points.

On the other hand, if the continuity of the pattern detection signal PD is interrupted before the counter 305 counts a predetermined number, that is, when its output is at the rLJ level, and the next pattern detection signal PD is obtained when the flip-flop 26 is not set ( At time T4, T8), the counter 305 is reset via the AND circuit 303 and the OR circuit 304.

As a result, the counter 305 starts counting again from 10゛1.

Similarly, depending on the count contents of counter 31/5.325,
The IHj level signal or rLl level signal is stored in the Kashifuji register 41L421, respectively.

Therefore, if all banknote dividing point signals NTD are obtained,
Selector circuits 402 to 42 determine whether the contents of shift registers 401 to 421 at that time are the same as predetermined contents.
If they are the same, banknote discrimination signals CNI to CN3 at rHl level are output.

The same applies to other denominations (Tenshi yen banknotes, 10,000 yen banknotes).

Note that the banknote discrimination signals CNI to CN3 are output from the selector circuit 40.
If the banknote is output from any one of selector circuits 402 to 422 and cannot be obtained from any of the selector circuits 402 to 422, the banknote is identified as a counterfeit banknote.

As described above, according to the present invention, time is measured from when one pattern detection signal is obtained, and this is counted only when the next pattern detection signal is obtained after a predetermined time corresponding to the conveyance speed has elapsed. However, it is determined whether the interval and continuity of the banknote pattern is normal based on whether or not a predetermined number of pattern signals are counted in succession. It is possible.

Although magnetic means are used as the pattern detection device in the above-described embodiments, it is also possible to detect the pattern using optical means.

In addition, the time-lapse signal generator is not limited to the one shown in the embodiment, and in short, every time a detection signal from the pattern detection device is input, a pulse signal of a predetermined width is generated corresponding to the conveyance speed from the time of input. It may be of any kind as long as it is output after a predetermined period of time has elapsed.

Furthermore, when using a computer, the output of the counter of the frequency counting device is temporarily stored in a latch section, and the CPU
The contents of the latch section may be read by a command from a microprocessor and determined within the CPU.

On the other hand, the above-mentioned embodiment is configured to identify one side of a banknote, but in order to identify both the front and back sides, another set of the same device, that is, is installed to be able to detect both sides of the transported banknote. That's fine.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram showing an example of a reference clock signal forming device used in this invention, and FIGS. 3A to 3E are diagrams for explaining its operation. Time charts, FIGS. 4A to 4E are time charts for explaining the operation of FIG. 1. 10... Pattern detection device, 11...
Magnetic head, 12... Waveform shaping circuit, 13...
... One-shot circuit, 14 ... Delay circuit, 20 ... Time signal generator, 21 ...
・Counter, 22...Counter reading circuit, 23
~25...OR circuit, 26~28...
Flip-flop, 200... Reference clock signal forming device, 204... Identification unit, 205...
- Banknotes, 209...Synchronization signal generation mechanism, 214
. . . Synchronous signal detection circuit, 215 . . . Clock signal generation circuit, 30 . . . Frequency counting device, 3
05, 315, 325...Counter, 40...
・-・-Discrimination device, 40L411゜421...
Shift register, 402, 412° 422...
Selector circuit, 50...Delay circuit.

Claims (1)

[Claims] 1 A pattern detection device for detecting a pattern on a banknote, and each time a pattern detection signal obtained from this pattern detection device is input, a time-lapse signal of a predetermined time width is transmitted from the time of input of the pattern detection signal to the conveyance of the banknote. A time-lapse signal generating device that generates a signal after a predetermined time period corresponding to the speed, and a time-lapse signal generator that counts when the next pattern detection signal is obtained when the time-lapse signal is obtained, and a time-lapse signal generator that generates a time-lapse signal when the next pattern detection signal is obtained when the time-lapse signal is obtained, and a time-lapse signal generator that generates a time-lapse signal after a predetermined time period corresponding to the speed. a frequency counting device that clears counting contents when a pattern detection signal of 1. A banknote identification device, characterized in that it determines whether a banknote is genuine or false.