JPH0126107B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method for an input/output device, and particularly to a multiple priority interrupt control method for a process input/output device. Such a technique will be explained with reference to FIG.

FIG. 3 shows the overall configuration of the process input/output device, where 1 is a control computer, 2 is a process input/output unit, and 3 is a process input/output bus. Here, each of the process input/output units 2 is assigned a unit number U ₀ , U _{1 .} . . as shown in the figure.
Each input/output module 22 is also assigned a channel number such as IO ₀ and IO ₁ , and each unit controller 21 is connected to the process input/output bus 3 to transmit process information between the control computer 1 and each input/output module 22. transfer control.

Now, in a process input/output device having such a configuration, various service requests are generated by each input/output module 22, such as a request for service upon completion of analog-to-digital conversion from an analog input module, and an input from a digital input module. In order to transmit service requests associated with state changes to the control computer 1 and have the control computer execute predetermined processing in response to the service requests, when a large number of process input/output units 2 simultaneously make interrupt requests, the predetermined Multi-priority interrupt control is adopted in which an interrupt request from one process input/output unit is accepted based on the priority of the process input/output unit.

[Prior art and its problems]

FIG. 4 shows the overall configuration of a conventional process input/output device, in which 31 is an interrupt request transfer bus, 32
is an interrupt request confirmation signal line. In the figure, the same reference numerals as in FIG. 3 indicate the same components.

In FIG. 4, the input/output bus 3 shown in FIG. 3 includes an interrupt request transfer bus 31 and an interrupt request confirmation signal line 32 that connects the control computer 1 and each process input/output unit 2 in cascade. It is being

The interrupt request transfer bus 31 is configured to transfer the interrupt request signal sent from the interrupt request output QO of the unit controller 21 of each process input/output unit 2 to the interrupt request input QI of the control computer 1. Process input/output unit 2 with unit number U _M such as ₀ , U ₁ ...
Assuming that the process input/output unit is the corresponding process input/output unit, the interrupt request confirmation signal line 32 receives an interrupt sent from the interrupt request confirmation output GO of the control computer 1 or the unit controller 21 of the process input/output unit with unit number U _M-1 in the previous stage. Transfer the request confirmation signal to the interrupt request confirmation input GI of the unit controller 21 of the process input/output unit,
The interrupt request confirmation signal sent from the interrupt request confirmation output GO of the unit controller 21 of the process input/output unit is sent to the next stage unit number U _M+1.
Multiple interrupt control is performed by transferring the request to the interrupt request confirmation input GI of the unit controller 21 of the process input/output unit.

FIG. 5 shows an example of a multiple priority interrupt control circuit in the unit controller of the process input/output unit shown in FIG. 4, where 4 is a bus receiver, 5,
5' is a bus driver; 6 is a positive edge trigger D-type flip-flop (hereinafter simply referred to as a flip-flop) having data input D, clock input T, memory output Q, and inverted memory output; OR ₁
is an OR gate, AND ₁ and AND ₂ are AND gates.

Now, the interrupt request confirmation signal is input from the control computer 1 or the previous process input/output unit through the interrupt request confirmation signal line 32.
Once transferred to the GI, the interrupt request acknowledge signal is received by bus receiver 4 and sent to flip-flop 6.
clock input T and AND gates AND ₁ , AND ₂
in order to store the logic of the data input D of the flip-flop 6 at the leading edge of its signal input.
At this time, if the logic of the data input D is "0", the logic of the storage output Q becomes "0", and the logic of the inverted storage output becomes "1".

From this, the interrupt request confirmation signal is a logical product.
Output through AND ₂ and bus driver 5', and output from interrupt request confirmation output GO to interrupt request confirmation signal line 3.
Interrupt request confirmation input to the unit controller 21 of the next stage process input/output unit.
Transferred to GI. Furthermore, if the logic of the data input D of the flip-flop 6 is "1", the logic of the memory output Q is "1", the inverted memory output is "0", and the interrupt request confirmation signal is not transmitted to the bus driver 5'. Then, the interrupt request acceptance signal ACK is transmitted to the internal logic circuit by the AND gate _AND1 .

Therefore, when a service request is generated by any input/output module in the process input/output unit, the service request signal SQ ₀ ,
Among SQ ₁ , SQ ₂ ..., the service request signal of the input/output module that generated the service request is logic "1"
So, the logic of the output of OR gate OR ₁ is "1"
is output through the bus driver 5, and sent from the interrupt request output QO to the interrupt request transfer bus 31 to issue an interrupt request.
Since the logic of data input D is set to "1",
Similarly, even if a subsequent process input/output unit issues an interrupt request, the interrupt request confirmation signal is not transmitted to the subsequent process input/output unit accepted by the process input/output unit. This means that the process input/output unit has a higher priority for interrupt requests than the process input/output units in the next and subsequent stages.

In this way, the system shown in FIGS. 4 and 5 has the advantage that multiple priority interrupt control can be performed with a simple circuit configuration, but on the other hand, the priority of each process input/output unit with respect to interrupt requests is determined by each process. This has the disadvantage that it is determined by the physical connection order between input and output units.

This means that if the priority order were to be changed, the routing of the cables that constitute the process input/output bus would have to be changed. moreover,
For process input/output units that have not requested an interrupt, the interrupt request confirmation signal is bypassed to the next stage process input/output unit through the multiple priority interrupt control circuit of the unit controller, so that processes to which power is not supplied are bypassed. If there is an input/output unit, the interrupt request confirmation signal will not be bypassed from that process input/output unit, and as a result, subsequent process input/output units will not be able to request an interrupt, causing system operation to stop. . In other words, some process input/output units cannot be disconnected for maintenance or the like by cutting off the power while the system is in operation.

[Structure of the invention]

In view of the above-mentioned points, the present invention enables the priority order of interrupt requests to be freely set for each process input/output unit without depending on the physical connection order between the process input/output units,
Furthermore, a highly flexible process input/output device is provided in which the interrupt request confirmation signal is directly transmitted from the control computer to the process input/output unit making the interrupt request without bypassing the unit controller of each process input/output unit. The present invention provides a multiple priority interrupt control method. Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is shown to explain the process input device according to the present invention, and 1' is a control computer;
2' is a process input/output unit, and 34 is an interrupt request confirmation transfer bus. In the figure, the same reference numerals as in FIG. 4 indicate parts having the same functions.

That is, in the system shown in FIG. 1, the interrupt request transfer bus 3 is used as the process input/output bus.
1, a synchronization signal transfer bus 33, and an interrupt request confirmation transfer bus 34 are provided, and the interrupt request input/output of the unit controller 21' of each process input/output unit 2' is carried out on the interrupt request transfer bus 31.
Transfers the interrupt request signal sent from QIO to the interrupt request input QI of control computer 1',
It is transferred to the interrupt input/output QIO of the unit controller 21' of each process input/output unit 2', and the control computer 1' receives the control signal from the synchronous signal generation circuit (not shown) on the synchronous signal transfer bus 33. A synchronizing signal of a fixed period sent from the synchronizing signal output SO of the computer 1' is transferred to the synchronizing signal input SI of the unit controller 21' of each process input/output unit 2', and the interrupt request confirmation transfer bus 34 is used for control. The interrupt request confirmation signal sent from the interrupt request confirmation output GO of the computer 1' is sent to the interrupt request confirmation input GI of the unit controller 21' of each process input/output unit 2'.
to be forwarded to.

Furthermore, only when no interrupt request signal is sent to the interrupt request transfer bus 31 to the unit controller 21' of each process input/output unit 2', at the start of one cycle of the synchronization signal transferred to the synchronization signal input SI. Count the check pulses from
At the time when the number of check pulses corresponding to the priority set value unique to each process input/output unit is counted in advance, if a service request is generated by the input/output module and an interrupt is sent to the interrupt request transfer bus 31. If no request signal has been sent, an interrupt request signal is sent from the interrupt request output QO to the interrupt request transfer bus 31 to request an interrupt, and only when this interrupt request is being made is it transferred to the interrupt request confirmation input GI. It has a multi-priority interrupt function that allows it to receive interrupt request confirmation signals.

Next, such a function will be explained in detail using an example in FIG.

FIG. 2 shows a specific circuit configuration example of the multiple priority interrupt control circuit in the unit controller of the process input/output unit according to the present invention.
4', 4'', 4 are bus receivers, 5'' are bus drivers, 6', 6'' are set input S and reset input R.
and a storage output Q, a positive edge trigger D type flip-flop having a data input D, a clock input T, a reset input R and a storage output Q; 1, a one-shot circuit that is triggered by the rising edge of the clock input T and outputs a one-shot pulse from the pulse output Q;
8 is a check pulse generator that provides a check pulse from the pulse output CLK during the period when the logic of the pulse oscillation enable input EN is "1"; 9 is a load input LD, a preset data input PD, a subtraction pulse input TD, and a borrow output BR. 10 is a priority setter, OR ₂ is an OR gate, AND ₃ , AND ₄ are AND gates, NOT ₁ ,
NOT ₂ is an inverter gate.

That is, the functions of this circuit configuration are as follows.

Now, the interrupt request signal sent to the interrupt request transfer bus 31 and transferred to the interrupt request input QI of the control computer 1 is transmitted to each process input/output unit 2'.
Interrupt request input to unit controller 21'
QIO is also transferred to the bus receiver 4″ and is received by the inverter gate NOT ₁
After the logic is inverted by this NOT ₁ , it is applied to the AND gate AND ₃ and the data input D of the one shot circuit 7.

On the other hand, the synchronization signal sent to the synchronization signal transfer bus 33 and transferred to the synchronization signal input SI is received by the bus receiver 4 and input to the clock input T of the one shot circuit 7. This one-shot circuit 7 checks the logic state of the data input D at every rising edge that is the start of one cycle of the synchronization signal, and triggers and outputs a pulse only when the logic of the data input D is "1". Since Q acts to generate a starting pulse, when no interrupt request is made in any process input/output unit, the interrupt request signal is not transferred to the interrupt request input/output QIO, so the logic of bus receiver 4'' output is It is "0" and is inverted by the inverter gate NOT ₁ , so that the logic of the data input D of the one shot circuit 7 becomes "1", and the one shot circuit 7 is triggered by the rising edge of the synchronization signal input to the clock input T. A starting pulse is output from pulse output Q.

Furthermore, since the pulse output Q of the one-shot circuit 7 is connected to the load input LD of the check pulse counter 9 and the set input S of the flip-flop 6', the above-mentioned starting pulse is controlled by the priority setter 10 such as a switch. The priority set value that has been set and is input to the preset data input PD is preset to the check pulse counter 9, and the flip-flop 6' is set to set the logic of the memory output Q to "1", so a check pulse is generated. When the logic of the pulse oscillation enable input EN becomes "1", the device 8 outputs a check pulse train from the pulse output CLK. Pulse output of check pulse generator 8
Since CLK is connected to the subtraction pulse input TD of the check pulse counter 9, the check pulse counter 9 subtracts the count value by 1 every time one check pulse of the above-mentioned check pulse train is input.
When the preset priority setting value is subtracted and the number of check pulses corresponding to the priority setting value is counted, an interrupt check signal is output from the borrow output BR.

Furthermore, the borrow output BR of the check pulse counter 9 is connected to the reset input R of the flip-flop 6'.
is connected to the clock input T of flip-flop 6'', so that the aforementioned interrupt check signal resets flip-flop 6' and outputs the memory output Q.
Since the logic of the check pulse generator 8 becomes "0", the logic of the pulse oscillation enable input EN becomes "0" and stops outputting check pulses.
On the other hand, the logic of the data input D is stored in the flip-flop 6'' at its leading edge, and the logic of the data input D is further sent out from the storage output Q, and connected to the bus driver 5'' and the AND gate.
AND ₄ , so that the logic of data input D of flip-flop 6'' is "1".
Since the logic of the memory output Q is "1" when the current state is 1, an interrupt request signal is sent from the interrupt request input/output QIO to the interrupt request transfer bus 31 through the bus driver 5'', and an interrupt request is made. , when the interrupt request confirmation signal is sent to the interrupt request confirmation transfer bus 34, transferred to the interrupt request confirmation input GI, and received by the bus receiver 4',
Since the interrupt request confirmation signal is inputted to the other input of the AND gate _AND4 , the interrupt request acceptance signal ACK is transmitted to the internal logic circuit by the AND gate _AND4 .

By the way, since the logic of the data input D of the flip-flop 6'' is determined by the logical product of the output of the inverter gate NOT ₁ in the AND gate AND ₃ and the logic of the output of the OR gate OR ₂ , There are the following three logics depending on the presence or absence of a service request generated from an input/output module and the presence or absence of an interrupt request generated from another process input/output unit.

(1) When no service request is generated by any input/output module, the service request signals SQ ₀ , SQ ₁ , SQ ₂ , etc. Since the logic of _{the 2} outputs is "0", the logic of the AND ₃ output of the AND gate is "0".

(2) When an interrupt request is made by any process input/output unit, the logic of the bus receiver 4'' output is "1" and is inverted by the inverter gate NOT ₁ .
Since the logic of the NOT ₁ output is "0", the logic of the output of the OR gate OR ₂ , that is, the logic of the AND ₃ output is "0" regardless of the presence or absence of a service request generated by the input/output module.
It is.

(3) When a service request is generated by any input/output module and no interrupt request is issued by any process input/output unit, the service request signals SQ ₀ , SQ ₁ ,
Among SQ ₂ , ..., the service request signal of the input/output module generating the service request is logic "1", the logic of the OR gate OR ₂ output is "1", and the bus receiver 4'' output The logic of is "0" and the inverter gate NOT ₁
is inverted and the logic of the inverter gate NOT ₁ output becomes "1", so the AND gate AND ₃
The logic of the output is "1".

Therefore, in (1) above, there is no need to issue an interrupt request because no service request is generated by the input/output module. Also, the above (2)
This is a case where interrupt requests are prohibited even if a service request is generated by an input/output module because a process input/output unit with a lower priority setting value than the process input/output unit is requesting an interrupt. . Furthermore, the above (3)
is allowed to issue an interrupt request because a process input/output unit with a lower priority setting value than the relevant process input/output unit has not issued an interrupt request, and a service request has been generated by the input/output module. This is the case when an interrupt request is made. Therefore, in the case of (3), by issuing an interrupt request, the interrupt request of a process input/output unit having a higher priority level than that of the process input/output unit is prohibited.

Next, the one-shot circuit 7' has a data input D
The logic of is fixed to "1", and when the interrupt request acceptance signal ACK is inverted by the inverter gate NOT ₂ and transmitted to the clock input T, the trailing edge of the interrupt request acceptance signal ACK, and therefore the interrupt request confirmation signal. A reset pulse is generated from the pulse output Q by being triggered at the trailing edge of .

The pulse output Q of this one-shot circuit 7' is connected to the reset input R of the flip-flop 6'', and the aforementioned reset pulse resets the flip-flop 6'' and sets the logic of the memory output Q to "0".
and cancels the interrupt request signal sent from the interrupt request input/output QIO to the interrupt request transfer bus 31 through the bus driver 5''.

〔Effect of the invention〕

In the present invention, as described with reference to FIGS. 1 and 2, the priorities for interrupt requests of each process input/output unit are preset from the priority setter 10 to the check pulse counter 9 simply by a start pulse. Since the priority setting value is determined only by the magnitude of the priority setting value, the priority setting device 10 is a switch or other variable setting device that can be easily set and changed. By setting unique data as the priority setting value, the priority for interrupt requests can be set freely for each process I/O unit depending on the priority setting value, regardless of the physical connection order between each process I/O unit. A method can be provided that can realize a device with a simple configuration that can be allocated.

Furthermore, by providing a shared interrupt request confirmation transfer bus 34 to each process input/output unit as a means for transferring an interrupt request confirmation signal, a direct interrupt request can be made only to the process input/output unit that is making an interrupt request from the control computer. Because the confirmation signal is transmitted, even if there is a process input/output unit to which power is not supplied, it can be interrupted by other process input/output units without any problem, making it extremely flexible and with a large degree of freedom. It is possible to realize a device using a multi-priority interrupt control method for a process input/output device.

In the present invention, a subtraction counter with a preset function is used in the check pulse counting section to perform subtraction counting of the priority setting value, but this is a means for counting the number of check pulses corresponding to the priority setting value. Of course, they can be substituted.

[Brief explanation of drawings]

1 and 2 are a system diagram shown to explain a process input/output device according to the present invention, a circuit diagram showing a specific example of a multiple priority interrupt control circuit in a unit controller of the process input/output unit, and FIG. FIG. 4 is a system diagram showing the overall configuration of a process input/output device, and FIGS. 4 and 5 are a system diagram and a partial circuit diagram thereof shown to explain a conventional multiple priority interrupt control system for a process input/output device. 1, 1'... Control computer, 2, 2'... Process input/output unit, 31... Interrupt request transfer bus, 33... Synchronous signal transfer bus, 34... Interrupt request confirmation transfer bus, 6, 6' ,6″...Flip-flop, 7,7′...One-shot circuit, 8...
Check pulse generator, 9...Check pulse counter, 10...Priority setter.

Claims (1)

[Claims] 1. By providing an interrupt request transfer bus, a synchronization signal transfer bus, and an interrupt request confirmation transfer bus in the process input/output bus, interrupts sent from the interrupt request input/output of the unit controller of each process input/output unit can be processed on the interrupt request transfer bus. The request signal is transferred to the interrupt request input of the control computer, and is also transferred to the interrupt request input/output of the unit controller, and the synchronization signal of a constant period sent from the synchronization signal output of the control computer is transferred to each of the synchronization signal transfer buses. The interrupt request confirmation signal sent from the interrupt request confirmation output of the control computer on the interrupt request confirmation transfer bus is transferred to the synchronization signal input of the unit controller of each process input/output unit. A multi-priority interrupt control circuit having a priority setter, a check pulse generator, and a check pulse counter is provided in the unit controller of each process input/output unit, and a synchronization signal is transferred to the synchronization signal input. By checking the presence or absence of an interrupt request signal transferred to the interrupt request input/output at each start of one cycle of the signal, the check pulse generator generates a check pulse only when no interrupt request signal is sent to the interrupt request transfer bus. is generated and counted by the check pulse counter, and at the time when the check pulse counter counts check pulses equivalent to the priority setting value set by the priority setting device, whether or not a service request has occurred and an interrupt is generated. By checking the presence or absence of an interrupt request signal transferred to the request input/output, it is possible to transfer the interrupt request signal from the interrupt request input/output to the interrupt request transfer bus only when a service request signal is generated and no interrupt request signal is sent to the interrupt request transfer bus. 1. An interrupt control method for an input/output device, characterized in that the interrupt request signal is sent to the input/output device, and the interrupt request confirmation signal is transferred to the interrupt request confirmation input.