JPH0128392B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal display device, and particularly to a circuit optimal for a character display device.

Unlike numeric display devices such as wristwatches that display numbers by segment display, LCD character display devices display alphanumeric characters, numbers, kana, etc. by combining multiple pixels 2, as shown in Figure 1. It is something to do. From now on, pixels will be called dots.

In Figure 2, one character consists of 5 dots horizontally and 7 dots vertically.
An example of character display when composed of 35 dot matrices is shown.

FIG. 3 shows a circuit for driving the liquid crystal panel shown in FIG. 1 to display characters.

The driving voltages applied to the scanning electrodes 5 and signal electrodes 6 of the liquid crystal panel 1 are applied to the liquid crystal matrix driving circuits 3 and 4.
Generate with.

The liquid crystal matrix drive circuits 3 and 4 are composed of serial/parallel conversion circuits 3C and 4C, latch circuits 3b and 4b, and drive voltage output circuits 3a and 4a. Further, external trigger input terminals 7a, 7b, external clock input terminals 7c, 7d, data input terminals 7e, 7
A driving voltage to the electrodes 5 and 6 is generated by applying a predetermined signal to each of the electrodes f.

On the other hand, in liquid crystal matrix driving, a line sequential scanning method is used in which each dot on a liquid crystal panel is selected by scanning a scanning electrode at a constant period. That is, as shown in FIG. 4, scanning electrodes 1 to m are sequentially scanned. In this case, on/off voltages for each dot are applied to the signal electrodes 1 to n in accordance with the scanning timing.

A display signal D for turning each dot on or off is input to the data input terminal 7f. At this time, for example, the signal of scan electrode 2 is input during the time when scan electrode 1 is selected.

A conventional example of a circuit for controlling the liquid crystal matrix drive circuits 3 and 4 is shown in FIG. The control circuit 8 converts the character code signal from the character code signal generation circuit 17 into a display signal D, and also generates signals CL1, CL2, CL2, which control the liquid crystal matrix drive circuit 16.
Generate FLM,M. Therefore, FIG. 6 shows the state of each signal. Signal FLM is a start signal for scanning one screen. That is, display of one screen starts from time Ts.

Signal CL1 is a start signal for scanning each line. The lines to be scanned are sequentially shifted for each signal. Further, this signal is also used as a trigger signal to take in the output of the serial/parallel conversion circuit 4C shown in FIG. 3 into the latch circuit 4b.

The signal CL2 is a timing signal for taking in the display signal D into the serial/parallel conversion circuit 4C.

On the other hand, the signal M is used for AC driving the liquid crystal.

Next, the operation of each part will be briefly explained.

When the character code signal is input, the character code signal writing circuit 9 sequentially writes the character code signal into the frame memory 12. For this reason, the frame memory 12
A character code signal and a write address signal that determines the writing position are input to the .

On the other hand, the character code signals written in the frame memory 12 are sequentially read out by the refresh counter 11 and sent to the character pattern generator 13. Note that 10 is an address selection circuit that selects a write address signal and a read address signal and sends it to the frame memory 12. Character pattern generator 13 generates a character pattern signal based on the character code signal and the row address signal from refresh counter 11. This character pattern signal is converted into a serial signal by a parallel/serial conversion circuit 14, and this becomes a character signal D.

The refresh counter 11 is composed of four counters: a column dot counter 11a, a column counter 11b, a row dot counter 11c, and a row counter 11d.

Now, assuming that the number of columns of the liquid crystal panel is M and the number of rows is N, the contents of the frame memory 12 can be expressed by the schematic diagram shown in FIG. At this time, the character code signal is sequentially written from address 0 to address M-1 in each row of the frame memory.

The contents of the frame memory 12 are stored in the column counter 11.
b and the output of the line counter 11d and sent to the character pattern generator.

As a result, the clock frequency CL2 to the refresh counter 11 can be expressed by the following equation.

CL2≧ _F × M × N × P × Q (Hz) ... (1) In formula (1), _F is the frame frequency for scanning one screen of the liquid crystal panel, which should be approximately 40 to 100 Hz due to the characteristics of liquid crystal. is desirable. Further, P and Q are the numbers of dots forming one character.

Incidentally, in order to reduce the size and power consumption of the liquid crystal display device, integration of the control device 8 is an essential condition. In this case, it is desirable to be able to freely change the control contents in accordance with the specifications of the liquid crystal panel, such as the number of characters to be displayed, in order to provide expandability to the control and provide an integrated circuit with excellent versatility.

In order to change the number of displayed characters and the number of displayed lines in the conventional circuit shown in FIG. 5, it is necessary to change the count contents of the counters 11b and 11d. Along with this, the frame frequency _F fluctuates greatly. To prevent this, the oscillation frequency of the oscillation circuit can be varied, or, as shown in FIG. method was adopted.

In either method, the operating frequency of the integrated circuit varies greatly depending on the number of displayed characters and the like. For this reason, as the number of displayed characters and lines decreases, the operating frequency becomes lower, making dynamic circuit operation impossible, which has been a problem in integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device in which the count number of a refresh counter is constant regardless of display conditions, and the operating frequency is constant.

A feature of the present invention is that the product of the count numbers of the column counter and the row counter constituting the refresh counter is constant, and the product of the column count value arbitrarily set from the outside and the column counter The output signal is added to a comparison circuit, and this matching output is used as a start signal for one line, so that the operating frequency of the circuit is kept constant regardless of the number of rows and columns of displayed characters.

Examples of the present invention are shown in FIGS. 9 and 10. The following is a step-by-step explanation.

FIG. 9 shows a circuit section that reads character code signals written in the frame memory 20 and converts them into character pattern signals.

A clock signal CL2 generated by the oscillation circuit 24 is supplied to the refresh counter 25. At this time,
The refresh counter 25 includes a column dot counter 25a, a column counter 25b, and a row dot counter 2.
5c and a row counter 25d.

The count values of the column dot counter 25a and the row dot counter 25c correspond to the number of horizontal and vertical dots of the displayed character. Generally, a 5×7 dot or 7×9 dot configuration is used. Here, we will fix it to one of the character patterns.

Now, if the count value of the column counter 25b is m, the column signal changes from 0 to m-1, and furthermore, if the count value of the row counter 25d is n, the row signal changes from 0 to n-1.

At this time, the count value m of the column counter 25b,
The count value n of the row counter 25d is determined by the contents stored in the column number register 29 and the display row register 22. Therefore, the operation of each counter will be explained.

First, the operation of the column counter 25b will be explained. Each time the output signal CP1 of the column dot counter 25a is input, the column counter 25b counts up by +1. When the output matches the contents of the column number register 29, a reset signal RST1 is supplied from the comparison circuit 28 to the column counter 25b. As a result, the column counter 25b is reset and all outputs become "0". From now on, repeat this operation.

On the other hand, the row counter 25d counts up by +1 each time the output signal CP2 of the row dot counter 25c is input. When the output of this counter matches the contents of the display row register 22, a reset signal RST2 is supplied from the comparison circuit 23 to the row counter 25d. As a result, the row counter 25d is reset and all outputs become "0", and this series of operations is repeated thereafter.

The display line register 22 is used to set the number of display lines on the liquid crystal panel. Accordingly, a value that satisfies the following equation is set in the column number register 29.

m=c/n...(2) In formula (2), m is the set value to the column number register 29,
n is a set value of the display row register, and c is an arbitrary constant value.

On the other hand, the number of columns of display characters on the liquid crystal panel is set in the display column register 27. As a result, each time the output of the column counter 25b and the number of columns match, the comparison circuit 26
A match signal CL1 is outputted from.

Furthermore, if the number of character rows on the liquid crystal panel is M, then
The value of c shown in equation (2) is determined so that M≧m is satisfied.

FIG. 10 shows the column number register 29 shown in FIG.
Instead, a division circuit 29a is provided to obtain m in equation (2). For example, as shown in FIG. 11, for display rows 1 to 16, display columns 512 to 16
Find 32. As a result, the column counter 25b is
512 to 32-decimal counter, and the line counter 25d is
It becomes a binary to hexadecimal counter.

The operation of the circuit shown in Figs. 9 and 10 is explained in the first section.
The case where characters are displayed on the liquid crystal panel shown in FIG. 2 will be explained as an example. At this time, one character consists of 5 dots horizontally and 7 dots vertically, with 2 display rows and 4 display columns. Therefore, there are 14 lines of scanning electrodes X and 20 lines of signal electrodes Y. Further, c shown in equation (2) is set as 512.

FIG. 13 shows the timing of each signal. The count content of the row counter 25d is 1.
It is reset every time. Further, the row dot counter 25c is reset every time the count reaches six. Further, the column counter 25b is reset every time the count reaches 255 from the relationship of equation (2).

On the other hand, since there are four display columns, when reading up to four columns of the frame memory 20 is completed, the comparison circuit 26 outputs the signal CL1.

Also, the frequency of signal CP1 is 1/5 of signal CL2.
It is divided into.

Through the series of operations described above, a 5-bit parallel pattern output is obtained from the character pattern generator 21. This is converted into a serial signal by the parallel/serial conversion circuit 30, and this becomes the display signal D.

FIG. 14 shows a timing diagram of the display signal D and the signals CL2 and CL1. Note that the signal CL2 is the first
This is a shift signal applied to the serial/parallel conversion circuit 31a included in the liquid crystal matrix drive circuit 31 shown in FIG. 5, and shifts the display signal D at the falling edge of H→L. Further, the signal CL1 is a latch signal of the latch circuit 31b, and at the time of falling, the output of the serial/parallel conversion circuit 31a is taken into the latch circuit 31b.

Now, set the position of each pixel on the liquid crystal panel to
When defined as Y1 to Y20, the display signal D includes the signal
On/off signals for each pixel appear in synchronization with CL2. Taking the first line as an example, 20 of signal CL2
On and off signals of pixels X1 and Y20 appear on the pulse. Thereafter, the parallel-converted display signals are taken into the latch circuit at the timing of the signal CL1. The subsequent display signal D becomes a signal unrelated to actual display. This state continues for 256 characters, that is, until the 1280th pulse. After this is completed, the display signal D moves to the second line.

At the falling timing of signal CL1 from H to L,
Drive voltages V _X1,Y1 to V _X1,Y20 corresponding to on and off signals appear at each output terminal 32d.

FIG. 16 shows input signals to the drive circuit 31 when driving the scanning side, and FIG. 17 shows a timing diagram of the signals at that time.

The clock input terminal 32a receives the signal CL1, and the data input terminal receives the output signal of the row counter 25d.
Add FLM. Furthermore, the trigger input terminal 32c
adds signal CL2.

As a result, at the timing of the fall of the signal CL1 from "H" to "L", the outputs S1 to S1 of the latch circuit 31b
S14 sequentially becomes "H" level, and output terminal 3
A scanning voltage is output from 2d.

Also, at this time, the display signal D shown in FIG.
As shown by diagonal lines in FIG. 17, the serial/parallel conversion circuit 31 is
It is incorporated into a.

Generally, the shape of letters is 5 x 7 dots or 7
A ×9 dot configuration is used. Therefore, in order to create a circuit that satisfies both conditions, the first
The count values of the column dot counter 25a and the row dot counter 25c shown in FIG. 8 may be made variable to 5, 7 or 7, 9, respectively. At this time, if the oscillation frequency of the oscillation circuit is constant, the frame frequency varies. Therefore, by providing a frequency dividing circuit 33 with a frequency division ratio of 1 or 1/2, it is possible to vary the frequency of the signal CL2 to the refresh counter 25 and reduce fluctuations in frame frequency.

According to the present invention, when the oscillation frequency of the oscillation circuit is kept constant, the operating frequency of the refresh circuit can be kept constant regardless of the number of characters and lines displayed on the liquid crystal panel. Accordingly, the frame frequency can also be kept constant.

From this, it is possible to provide an optimal circuit for integrating the control circuit of the liquid crystal matrix drive circuit including the refresh circuit.

That is, it is sufficient to suppress the fluctuation in the oscillation frequency within the permissible fluctuation in the frame frequency. This allows the process conditions for the integrated circuit to be relaxed.

Furthermore, if the oscillation frequency is set to an appropriate value, the integrated circuit can be constructed with dynamic gates without being affected by display conditions, and the circuit area can be reduced.

Further, a large-scale frequency dividing circuit for keeping the frame frequency constant is not required, and the circuit can be simplified.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of a liquid crystal matrix panel, Figure 2 is an example of character display using a dot matrix, Figure 3 is a drive circuit for the liquid crystal panel, Figure 4 is a timing diagram for line sequential scanning, and Figure 4 is a timing diagram for line sequential scanning. Figure 5 shows the control circuit of the conventionally used liquid crystal matrix drive circuit, Figure 6 is the timing diagram of the output signal of the control circuit, Figure 7 is a schematic diagram of the frame memory, and Figure 8 shows the control circuit of the conventionally used liquid crystal matrix drive circuit. The frame frequency stabilizing circuit, FIGS. 9 and 10, are the embodiments of the present invention, the first
Figure 1 is the functional diagram of Figure 10, Figures 12 to 17 are
Figures 9 and 10 showing specific operations, Figure 1
FIG. 8 shows a modified example. 1... Liquid crystal panel, 3, 4, 16, 31... Liquid crystal matrix drive circuit, 8... Control circuit, 12, 20...
Frame memory, 13, 21... Character pattern generator, 23, 26... Comparison circuit, 29... Column number register.

Claims (1)

[Claims] 1. A liquid crystal panel, a drive circuit that drives the liquid crystal panel, and a control circuit that controls the drive circuit, the control circuit specifying character display information to be displayed on the liquid crystal panel. a frame memory that records a character code signal read out from the frame memory, a character pattern generator that converts the character code signal read from the frame memory into a character pattern signal of dots, and a clock signal that sequentially counts clock signals of a constant period. a fourth stage counter, the first stage and third stage counters have count values equal to the number of horizontal and vertical pixels of characters displayed on the liquid crystal panel; The outputs of the counters in the third and fourth stages are used as read signals for the frame memory, and the outputs of the counters in the third stage are used as line signals for the character pattern generator, and characters are printed on the liquid crystal panel by line sequential scanning. In the liquid crystal display device, the control circuit includes a column number register that sets a set value m of the second stage counter, and a row number register that sets the set value n of the fourth stage counter. , a first comparator circuit that detects a match between the count value of the second stage counter and the set value m of the column number register and resets the count value of the second stage counter; a second comparison circuit that detects a match between the count value of the counter in the fourth stage and the set value n of the line number register and resets the count value of the counter in the fourth stage; a display column register that stores the number of columns M; and a third comparison circuit that compares the count value of the second stage counter with the number of columns M stored in the display column register and generates a match signal. the set value m of the second stage counter and the fourth stage counter;
Set the contents of the column number register and the row number register so that the product with the set value n of the counter in the second stage is constant, input the match signal to the drive circuit, and set the timing of the match signal. A liquid crystal display device characterized by performing line sequential scanning.