JPH0149951B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a matrix display device and a control circuit thereof, and more particularly to a control circuit for a matrix display device suitable for drive control of a liquid crystal matrix panel having a large number of display pixels. .

[Background of the invention]

2. Description of the Related Art For drive control of matrix display devices that display pixels such as characters and symbols using a liquid crystal matrix panel, a line sequential scanning method as shown in FIG. 1, for example, is widely known. The liquid crystal matrix panel 1 is configured such that display information signals and scanning signals are supplied to its signal electrodes 2 and scanning electrodes 3, respectively, so that pixels such as predetermined characters or signals are sequentially and selectively displayed by a line sequential scanning method. ing. Signal electrode 2
The drive circuit for the scan electrode 3 consists of a serial/parallel conversion circuit 4 for converting character pattern signals into parallel, a line memory 5, and a signal drive circuit 6, while the drive circuit for the scan electrode 3 consists of a scan circuit 7 and a scan drive circuit 8. being touched. The serial/parallel conversion circuit 4, line memory 5, and scanning circuit 7 in each drive circuit are controlled by a control circuit 10.

The control circuit 10 includes a refresh memory 11 that stores display information, a character pattern generator 12, a parallel/serial conversion circuit 13, and a series of refresh counter units 1 that control the timing of these elements.
Consists of 4. The counter section includes an oscillation circuit 15, a dot counter 16, a column counter 17, a line counter 18, and a row counter 19.

The count values of the dot counter 16 and the line counter 18 correspond to the number of horizontal dots and the number of vertical dots of the displayed character. The column counter 17 counts up by +1 each time the output signal of the dot counter 16 is input, and is reset when it reaches a certain value. The line counter 19 counts up by +1 each time the output signal of the line counter 18 is input, and is reset when it reaches a certain constant value.

The refresh memory 11 stores information I (hereinafter referred to as a character code signal) such as characters and signals to be displayed on the liquid crystal matrix panel 1 in the form of a code. The character pattern generator 12 receives a character code signal and generates a character display pattern for each line. This pattern signal is then converted into a serial signal by a parallel/serial conversion circuit 13.

Here, a timing diagram of the pattern signal D in series with the signals CP1, CP2, and CP3 is shown in FIG. 2 for one frame scanning time F _T . Signal CP3 is a timing signal to start scanning one screen. Further, the signal CP2 is a timing signal for sequentially scanning each row. Furthermore, CP1 is a timing signal for taking the pattern signal D into the serial/parallel conversion circuit 4. Of these, the signal CP2 is also used as a timing signal for loading one line of character patterns converted by the serial/parallel conversion circuit 4 into the line memory 5.

By the way, the number of scans for one screen is the frame frequency
When f _F (Hz), the frequency of signal CP1 must satisfy the following equation.

CP1≧f _F・M・N (Hz) However, M=number of signal electrodes, N=number of scanning electrodes.Therefore, the operating frequency required of the control circuit 10 must be a value that at least satisfies the above equation.

Here, as an example, one character is 5 x 8 dots, the number of displayed characters is 160, and the frame frequency f _F = 100
Hz, CP1≧640KHz, that is, an operating frequency of at least 60KHz is required. On the other hand, since driving a liquid crystal matrix is complicated, the number of components constituting a control circuit used therein increases, making it difficult to downsize and reduce power consumption of a matrix display device. For this reason, it is essential to implement the control circuit into an LSI, and it is particularly desirable to implement the control circuit into an LSI using a C-MOS (complementary MOS) process. There is an upper limit to the frequency, and in particular, in the case of an LSI circuit based on the C-MOS process, the upper limit of the operating frequency is lower than that in the case of the N-MOS process. Therefore, the number of pixels (M,
N) was limited, and there was a limit to the number of display characters that could be controlled.

[Purpose of the invention]

An object of the present invention is to provide a control circuit for a matrix display device that can smoothly control the display of a matrix panel regardless of the number of display pixels, does not require a high operating frequency, and can be miniaturized. A further object of the present invention is to provide expandability to the control circuit of a matrix display device, and to easily provide a large-sized matrix display device.

[Summary of the invention]

The present invention provides a matrix display device that is equipped with a refresh memory that stores display information and a refresh counter that controls the timing of the refresh memory, and that drives a matrix panel using a line sequential scanning method to display pixels. The control circuit has a function of generating a timing signal according to a certain count value of the refresh counter, and a function of setting the count value of the refresh counter according to a timing signal input from the outside. It is characterized by Further, in the present invention, the signal electrode and the scanning electrode intersect, the pixel at the intersection is displayed, and N display blocks (N≧2) are displayed.
A matrix panel divided into P〓 to P _N , a refresh memory that stores display information, a refresh counter that controls the timing of the refresh memory, and an external The N display blocks P have a function of generating a first timing signal to the display block P and a function of setting the count value of the refresh counter to a constant value by a second timing signal inputted from the outside. N control circuits ~N corresponding to ~P _N and respective display information signals from the N control circuits ~N to display the N display blocks P〓 ~P _N
and a scanning device for driving common scan electrodes of the N display blocks P-- _{P N by} the display information signal. and an electrode driving device, wherein the first timing signal generated by one of the N control circuits is used as the second timing signal of another control circuit.

[Embodiments of the invention]

Embodiments of a control circuit for a matrix display device according to the present invention will be described below with reference to FIGS. 3 to 10.

The control circuit 20 shown in FIG. 3 basically has a configuration corresponding to the control circuit 10 shown in FIG.
, a parallel/serial conversion circuit 23, and a series of refresh counter sections 24 for controlling these circuits. The refresh counter section 24 includes an oscillation circuit 25, a dot counter 26, a column counter 27, a line counter 28, and a row counter 29.
It consists of

The count values of the dot counter 26 and the line counter 28 correspond to the number of horizontal dots and the number of vertical dots of the displayed character. The column counter 27 counts up by +1 every time the output signal of the dot counter 26 is input, and is reset when it reaches a certain value. The line counter 29 counts up by +1 each time the output signal of the line counter is input, and is reset when it reaches a certain constant value.

To specifically explain the above, a case will be considered in which a liquid crystal matrix panel representing two characters vertically and two characters horizontally is controlled by the control circuit 20 of FIG. One character is displayed as 7 dots vertically and 5 dots horizontally. In this case, the count value of the dot counter 26 corresponds to the number of horizontal dots of the displayed character, so it shows five values from 0 to 4. The count value of the column counter 27 corresponds to the number of rows of characters to be displayed, so it shows two values from 0 to 1. The count value of the line counter 28 corresponds to the number of vertical dots of the characters to be displayed, so it shows seven values from 0 to 6. The count value of the line counter 29 corresponds to the number of vertical lines of characters to be displayed, so it shows two values from 0 to 1. Each time the dot counter 26 counts from 0 to 4 and is reset to 0, the count value of the column counter 27 increases by 1. Also, each time the column counter 27 counts from 0 to 1 and is reset to 0, the count value increases by 1 to the line counter 28. Line counter 28 is 0
Each time the count is counted up to 6 and reset to 0 again, the count value of the row counter 29 increases by 1. That is, when the row counter 29 counts from 0 to 1 and is reset to 0 again, the count values of the dot counter 26, column counter 27, and line counter 28 are all reset to 0, respectively.

Each of the counters 26 to 29 is configured as an up counter, and the count output from the column counter 27 and the count output from the row counter 29 are sent to the refresh memory 21, and the count output from the line counter 28 is sent to the character pattern generator 2.
It is designed to be added to 2. As a result, the character code signals written in the refresh memory 21 are sequentially read out to the character pattern generator 2.
2, where a character pattern is generated line by line. The character pattern is parallel/serial conversion circuit 23
The signal is converted into a serial character pattern signal D and sent to a driving device (not shown) for the liquid crystal matrix panel.

In this embodiment, the oscillation circuit 25 of the counter section 24 performs self-oscillation by connecting a resistor between its oscillation terminals J and K, and also connects one of these terminals J and K with an external source. It is formed so that it can also oscillate by adding a clock signal. A specific example of the oscillation circuit 25 used in this embodiment is shown in FIG. In the figure, 25A, 25B
is a not gate, 25C is a capacitor,
J and K are connection terminals installed so that an external clock signal can be applied.

A frame synchronization signal generation circuit 30 is provided on the output side of the row counter 29 at the final stage to generate a timing signal, that is, a frame synchronization signal SO in synchronization with the frequency division count output CP3. L indicates its output terminal.

Figure 5 shows the oscillation clock signal CP1, the divided output signals CP2 and CP of the column counter 27 and row counter 29.
3 and the frame synchronization signal SO. signal
CP3 is a timing signal for starting scanning with a frame period _fr of one screen, and this signal is synchronized with the frame synchronization signal SO.

FIG. 6 shows in detail the timing of generation of the frame synchronization signal SO. Signal counters 26-29
If configured to operate in synchronization with the rising edge of CP1, 1 of the frequency-divided output signal CP3 of the row counter 29
Dot counter 26 and column counter 2 every cycle
7. There is a period in which the cant values of the line counter 28 and the row counter 29 are simultaneously "0". In other words, the entire count value of the refresh counter is CT
If so, the total count value CT is "0" only during one period TC of the signal CP1, which is the same state as when the counter is reset. On the other hand, the frame synchronization signal SO is
This is generated in the first half of the period in which the total count value CT is "0". This causes the frame synchronization signal
SO will occur every time one frame of scanning starts. In this embodiment, each counter 26 to 29 receives a timing signal, that is, a synchronization setting signal SI, which is applied from the outside at any appropriate timing.
This allows each count value to be reset to the initial value (0). M in FIG. 3 is an input terminal for the synchronization setting signal SI.

The control circuit shown in Fig. 3 having the above functions is
The operation when a control circuit is constructed using the stand will be explained with reference to FIG. A resistor RL is connected between terminals J and K in the oscillation circuit of the control circuit to generate a clock signal, and the clock signal is applied to the oscillation circuit of the control circuit. Further, the frame synchronization signal SO of the control circuit is used as a reset signal for the counter of the control circuit, that is, a synchronization setting signal SI. As a result, both counters 26 to 29 operate at exactly the same timing. As a result, both signals CP1 and CP
2. CP3 occurs at the same timing.

Furthermore, as shown in FIG. 8, an arbitrary number of control circuits ~N are combined and operated synchronously, and character pattern signals D〓, D〓~D _N are generated from each display information block ~, ~ _N , respectively. Obtainable. Accordingly, as shown in FIG. 9, the liquid crystal display panel P is divided into display blocks P〓, P〓 to P _N , and the display blocks are divided for the control circuits, to N.
By making P〓, P〓 to P _N correspond to each other on a one-to-one basis and driving them through the signal electrode A and the scanning electrode B, it is possible to drive the entire display panel.

FIG. 10 shows an embodiment of a matrix display device constructed by using a plurality of unit units including the control circuit and the signal electrode driving device according to the present invention as described above. The liquid crystal matrix panel 31 is divided into a plurality of display blocks P~ _PN ,
Each block is driven for display by a respective signal electrode 32 and a common scanning electrode 33. The drive device for driving each signal electrode is divided into G≦ to _GN , each of which is formed of a serial/parallel conversion circuit 34, a line memory 35, and a signal drive circuit 36. Correspondingly, N control circuits 40 are used to apply character pattern signals D~D _N output from the husband to each serial/parallel conversion circuit 34 of each drive device G~G _N. being done. In addition, in the figure, H is a common driving device for the scanning electrodes, and is formed from a scanning circuit 37 and a scanning driving circuit 38.

Note that one character in one display block is 5x7.
It has a dot configuration, and one block displays four characters.

FIG. 13 shows the configuration of the counter. In this case, the dot counter 26 divides the frequency by 1/5,
The column counter 27 has a frequency divided by 1/4, and the line counter 28 has a frequency divided by 1/7. The line counter can be omitted since only one line is displayed.

Now, the case where the characters A, B, C, and D shown in FIG. 12 are displayed on one display block will be explained.

When the output signal CLM of the column counter 27 is 0 and the output signal LINE of the line counter 28 is 0, the character A is output from the refresh memory 21.
The code signal CHR is read out. From the read character code signal and the LINE signal (0), the output signal DOT of the character pattern generator 22 becomes a 5-bit pattern signal (parallel signal) of the first line of character A. The pattern signal thus obtained is converted into a serial signal D by a parallel/serial conversion circuit 23.

When this operation is completed, the output signal of the column counter 27 is incremented by 1, so the code signal of the character B is read out, and the 1 of the character B is read out by the above-described operation.
The line pattern is converted into a serial signal.
Thereafter, when this operation is repeated up to the letter D, the output signal LINE of the line counter 28 is incremented by 1, and the output signal CIM of the column counter 27 is again 0.
becomes.

Thereafter, the same operation as when reading out the first line pattern of characters A to D is repeated.

In this way, letters 1 to 7 of A, B, C, D
Line patterns can be read out.

Here, when the number of display blocks on the liquid crystal matrix panel 31 is N and N control circuits 40 are used, the character pattern signals D~D _N obtained from each control circuit and the output of each counter are The timing is shown in FIG.

Since the counters of each control circuit are synchronized, the signals CP1 to CP3 are output from each control circuit in synchronization. Furthermore, character pattern signals D≓ to D _N from each control circuit are also output in synchronization.

For example, the character patterns P〓 ₍ 〓 ₎ to P〓 _(N) on the first line of blocks ~N are output at the same timing.

In this embodiment, the frame synchronization signal is generated in synchronization with the output pulse CP3 of the refresh counter every scan synchronization of one screen (at the start of each scan synchronization).
Ability to generate SO and this frame synchronization signal
A plurality of control circuits 40 (I to N), each having a function of resetting a refresh counter using SO as a synchronization setting signal SI, are used to control the driving of display blocks P to P _N of the liquid crystal matrix panel, respectively. Therefore, the character pattern signal obtained by processing the display information ~ _N in each control circuit 40
Each display block P〓 to P _N can be driven synchronously by D〓 to D _N. Therefore, even when a liquid crystal matrix panel has a large number of pixels, the operating frequency of the control circuit can be increased by using a display panel and a corresponding number of control circuits divided into arbitrary plurality of display blocks. The drive of the matrix display device can be controlled smoothly and accurately without causing any disturbance. Moreover, in this embodiment, since each control circuit is provided with an output terminal for the frame synchronization signal SO and an input terminal for the reset pulse, that is, the synchronization setting signal SI, it is easy to combine these control circuits to obtain synchronization timing. Can be done.

In this way, in this embodiment, there is no need to change the operating frequency of the control circuit depending on the number of pixels to be displayed, so it is possible to implement the control circuit into an LSI, especially an LSI using a C-MOS process, and the matrix display device This makes it possible to downsize and reduce power consumption.

The matrix display device shown in FIG. 10 can be further configured as shown in FIG. 11 in practical use. In this device, an interface circuit 50 is provided on the display information input side of each control circuit 40, and the interface circuit 50 receives display information _ID from an external control system MP composed of a microcomputer or the like according to the contents of an address signal _IA . The signals are inputted to the respective control circuits. According to such a configuration, the versatility of the matrix display device can be further improved.

〔Effect of the invention〕

As described above, according to the present invention, the control circuit of a matrix display device can be easily controlled regardless of the number of display pixels.
It can be made into an LSI, which allows for smaller size and lower power consumption. Further, if the control circuit and the signal electrode driving device are made into a unit, a large-sized matrix display device can be easily obtained by increasing the number of units.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional matrix display device, FIG. 2 is a time chart of output signals of the control circuit of the device shown in FIG. 1, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a block diagram of the main part of the embodiment, FIGS. 5 and 6 are time charts of output signals of the embodiment of the present invention, and FIGS. 7 and 8 are
FIG. 9 is a diagram showing how the embodiment of the present invention is used,
10 and 11 are block diagrams of a matrix display device using an embodiment of the present invention, FIG. 12 is a diagram showing a display block of an embodiment of the present invention, and FIG.
14 is a diagram showing the configuration of a counter according to an embodiment of the present invention, and FIG. 14 is a diagram showing a character pattern signal and an output of the counter according to an embodiment of the present invention. 20... Control circuit, 21... Refresh memory,
22...Character pattern generator, 26-29...Refresh counter, 31...Liquid crystal matrix panel,
J, K...Oscillation terminal, L...Frame synchronization signal terminal,
M...Synchronization setting signal terminal.

Claims (1)

[Scope of Claims] 1. Consisting of a plurality of display blocks, comprising a refresh memory that stores display information corresponding to each of the display blocks to be controlled, and a refresh counter that controls the timing of the refresh memory. In the control circuit of a matrix display device that is equipped with a plurality of control circuits and drives signal electrodes of a matrix panel to display pixels using a line sequential scanning method, the count value of a refresh counter corresponding to one of the display blocks is and a function of setting the count value of the refresh counter corresponding to the other display block to the count value of the one refresh counter using the timing signal. A control circuit for a matrix display device characterized by: 2. The signal electrode and the scanning electrode intersect, display the pixel at the intersection, and display N (N≧2) display blocks.
A matrix panel divided into P _I to P _N , a refresh memory that stores display information corresponding to the display block to be controlled, a refresh counter that controls the timing of the refresh memory, and a refresh counter that controls the timing of the refresh memory. A function to generate a first timing signal to the outside according to a certain count value, and a function to generate a second timing signal input from the outside.
N control circuits ~N corresponding to the N display blocks P~ _PN , each having a function of setting the count value of the refresh counter to a constant value using a timing signal; The N display blocks P〓~P _N are controlled by respective display information signals from the control circuit ~N.
and a scanning device for driving common scan electrodes of the N display blocks P-- _{P N by} the display information signal. and an electrode driving device, wherein the first timing signal generated by one of the N control circuits I to N is used as the second timing signal of the other control circuits. Device.