JPH0129475B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a defect compensation circuit for a solid-state image sensor.

<Prior Art> It is difficult to manufacture a defect-free solid-state imaging device using a CCD or the like, and the problem is that the manufacturing yield is low. For this reason, various methods have been devised to compensate for defects by adding electrical circuits, to bring elements containing several defects to a practical level, and to substantially improve yield. One of those methods
One of the correction methods is to store the defect position in advance in a memory and replace the data of the defective point with data of a nearby normal point.

FIG. 1 shows an example of a conventional defect compensation device. 1
is a solid-state image sensor, 2 is a delay circuit, 3 is an analog switch, 4 is a memory that stores defect position information of the solid-state image sensor 1, 5 is a counter that counts addresses of the memory 4, and 6 is a counter that counts pixel positions. , 7 is a pulse generator that provides control signals for each circuit. The memory 4 contains information _I1 about how many clocks are away from the reference point to the first defective point, and information In how many clocks are away from the n-th and subsequent defective points from the n-1st defective point. (n≧2) is stored. Each time one screen is output from the solid-state image sensor 1, the address counter 5 is reset to 0, and the information _I1 stored at the beginning of the memory 4 is read out and loaded into the counter 6. The counter 6 is subtracted by a clock φ ₅ outputted from a pulse generator 7 synchronized with the transfer clock of the solid-state image sensor 1 .
The value of the information I1 transferred to the counter ₆ is set in such a way that the counter 6 becomes 0 exactly when the solid-state image sensor 1 outputs the data of the first defective point, and the correction pulse T is output. . In this way, the correction pulse T synchronized with the data of the defective point is output.
The correction pulse T is applied to the analog switch 3 to control switching of the contacts, and the pixel in which defective data is detected is replaced with normal data from a nearby point through the delay circuit 2.

FIG. 2 shows the inputs S ₀ and S ₁ and the output signal S ₂ of the analog switch 3. S ₀ is a direct signal from the solid-state image sensor 1, S ₁ is an output signal of the delay circuit 2, T is a compensation pulse, and S ₂ is an output signal of the analog switch 3, which is the result of defect compensation. When the correction pulse T is output from the pixel position counter 6, the address counter 5 is incremented by one, and the information _I2 stored in the memory 4 is loaded into the counter 6. Subsequently, the counter 6 is subtracted by φ _s in the same manner as in the above operation, and when it becomes 0, the corrected Hals T is output. By repeating the above steps, defect compensation is performed according to the information stored in the memory 4.

By the way, the amount of information required to memorize the defect position using this defect compensation method is 500 x 400 = 200000, assuming that the resolution of the solid-state image sensor 1 is approximately 500 x 400, and 2 ¹⁷ < 200000 < 2. ¹⁸ , so 18 bits are required to store the position information for one screen. However, most of the memories currently on the market have an 8-bit configuration, and if this is used, 24 bits (8 x 3) will be used to store 18 bits, resulting in poor memory storage efficiency. Furthermore, as the number of bits increases to 24 bits, the circuit becomes more complex, which hinders the construction of defect compensation circuits at low cost.

<Object of the Invention> The present invention eliminates the drawbacks of the conventional defect compensation circuit described above, and provides a circuit that stores position information in a memory of a predetermined number of bits (for example, 16 bits). Defects that cannot be expressed (defect positions whose interval is more than a predetermined number of bits) are
The present invention provides a defect compensation circuit for a solid-state image sensing device that can improve memory utilization efficiency by providing a temporary defect point so that it can be expressed with a predetermined number of bits.

<Example> First, Figures 3a and 3b show the state of scanning by the interlaced method of a solid-state image sensor showing odd and even fields, where A is the actual display period and B is the horizontal retrace line. The period C corresponds to the vertical retrace period.

FIG. 4 shows basic clock pulses in one frame of the solid-state image sensor. The pulse within period A corresponds to a transfer clock, and image information is transmitted in synchronization with this pulse, and no image information is transmitted between horizontal retrace period B and vertical retrace period C. In order to store defect position information in order to efficiently use the memory area, numbers are assigned to the basic clock pulses from the beginning as shown in Figure 4, and the pulse number of the first defect position is memorized, and n is For the nth defect position, which is a number greater than or equal to 2, the relative distance is stored by the number of pulses existing between that pulse and the pulse corresponding to the (n-1)th defect. The maximum value that this relative distance can take is about the number of pulses included in one frame, and the number N is 2 ¹⁷ <N < 2 ¹⁸ for a solid-state image sensor with a resolution of 500 vertically and 400 horizontally.
In this way, there may be cases where relative distance cannot be expressed using 16 bits. To deal with this case, several temporary defects are set in advance between the actual defects, and the relative distances between the defect points are all set to be less than 2 ¹⁶ . That is, it is stored as an integral multiple of 8 bits and within a smaller capacity.

Furthermore, in order to simplify the compensation circuit, it is convenient to treat the set temporary defect as the same without distinguishing it from the actual defect. However, if compensation is performed even on a temporary defective point, there is a problem in that a compensation error will occur at that point depending on the image.

Therefore, in this embodiment, the temporary defect point is set to a point within the horizontal retrace period B that is unrelated to display. In other words, the position information of the defective point is stored using the relative position of the pulse, and if the amount of information exceeds 16 bits, several points within an appropriate horizontal retrace interval between the defective points are stored as temporary defective points. By storing, the relative distance between each defect point is set to be less than ²¹⁶ . The temporary defect point can be set at which pulse in which horizontal retrace period in any number of ways, but how it is selected is not an essential problem. Also, the required number of temporary defects is
Since 2 ¹⁸ ÷ 2 ¹⁶ = 4, it is sufficient to set a maximum of 4 to 5 points and the memory capacity will not be affected.

The above explanation was about the relative distance between the second and subsequent defect positions and the previous defect position, but 1
Even if the second defect position exists at a position where ²¹⁶ or more pulses were counted, by setting several temporary defect points before the first defect using the same concept, the defect position can be set to 16 bits. It can be expressed as Figure 5 shows the relative distance of each defective point by setting temporary defective points _B1 , _B2 , and _B3 within the horizontal blanking period B for an image sensor whose actual defective points are _A1 and _A2 . Show that it can be made less than 2 ¹⁶ .

FIG. 6 shows a circuit block diagram of an embodiment of the present invention. The other configurations in the figure except for the memory are the same as in FIG. 1, and their explanation will be omitted. The memory 8 stores 16-bit information indicating the positions of actual defective points and temporary defective points selected from periods unrelated to display as described above.

First, each time one screen is output from the solid-state image sensor 1, the address counter 5 is reset to 0, and the 16-bit information I ₁ ' stored at the beginning of the memory 8 is loaded into the counter 6. Next, solid-state image sensor 1
The counter 6 is decremented by the basic clock φ. The value of I ₁ ' is preset to a value at which the counter 6 becomes 0 and the correction pulse T is output at the pulse position of the first defective point or a temporary defective point.
The analog switch 3 is switched under the control of the correction pulse T, and the output of the solid-state image sensor 1 is transferred to the delay circuit 2.
It is replaced with the data of the nearby point that passed through. If there is an actual defect, compensation for the defect is performed as shown in FIG. If it is a temporary defective point, the data is replaced in the same way, but since the temporary defective point is selected as a point within the horizontal retrace period B, it does not affect the display at all. When the correction pulse T is output, the address counter 5 is incremented by one, and the 16-bit information I ₂ ' stored in the memory 8 is loaded into the counter 6. Repeat the above operation to reach counter 6.
is subtracted by φ, and when the content becomes 0, the next correction pulse T is output.

As is clear from the above explanation, in the present invention, an appropriate point of the basic clock pulse of the solid-state image sensor during a period in which no display is performed is stored in the memory as a temporary defect point, thereby creating a gap between the defect points. This method is equivalent to the conventional method that does not create temporary defect points by setting the interval to less than a predetermined value such as less than 2 ¹⁶ , storing the value of the interval in memory, and performing defect compensation according to that information. A compensatory effect can be obtained. If the method of the present invention is used, the position information of the defective point is given in 16 bits, so it is possible to effectively utilize the currently mainstream 8-bit memory.

<Effects> According to the present invention, the position of a defective point can be efficiently stored in a memory, and when position information is stored in a memory with a predetermined number of bits, defects that cannot be expressed with a predetermined number of bits can be stored efficiently. By providing a temporary defect point, a predetermined number of bits is stored in the memory, and as a result, even for solid-state image sensors with a relatively large number of pixels, the defect compensation circuit cannot be constructed using the conventional method. Comparatively, it is possible to obtain a compensation circuit that can be constructed at low cost and has high practical value.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the conventional device, FIG. 2 is a waveform diagram for explaining defect compensation operation, FIG. 3 is a diagram showing interlaced scanning, and FIGS. 4 and 5 are part of the present invention. FIG. 6 is a diagram showing the relationship between pixel scanning and defective pixels for explaining an embodiment. FIG. 6 is a block diagram of an embodiment according to the present invention. 1: Fixed image sensor, 3: Analog switch,
5: Address counter, 6: Counter, 7: Pulse generator, 8: Memory.

Claims (1)

[Scope of Claims] 1. A solid-state image sensor comprising a plurality of image sensors arranged in an array, and a memory for storing positional information indicating the defective position of the solid-state image sensor, and based on the positional information read from the memory. In the defect compensation circuit that replaces the signal of a defective pixel of the solid-state image sensor with the signal of another pixel having a high correlation with the defective pixel, the position information stored in the memory with a predetermined number of bits is determined by the interval between adjacent defects. The defect position where the interval is greater than or equal to the predetermined number of bits is determined by presetting a point within the retrace period that is located between the adjacent defects and not displayed on the screen, and temporarily changing the position of the point. Position information indicating the position of the defect is stored in the memory. Defect compensation circuit for solid-state image sensors. 2 The solid-state image sensor has an imaging pixel number N (2 ⁱ ≦N<
2 ⁱ⁺¹ ), and if 8m≦i<8(m+1), the memory for storing defects is characterized in that the memory stores one defect position information expressed in a maximum of 8m bits. 2. A defect compensation circuit for a solid-state image sensor according to item 1.