JPH0130303B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a transistor structure that expands the safe operating area of the transistor and improves its reliability.

It is known to connect a ballast resistor to the base or emitter of a transistor in order to expand the safe operating area of the transistor. Conventional examples of ballast resistors are shown in FIGS. 1, 2, and 3. FIG. 1 shows that an N-type base region 2 is selectively diffused into a P-type collector region 1 of a PNP transistor, and a P-type emitter region 3 is selectively diffused into a part of the base region 2. A base electrode 4 and an emitter electrode 5 are provided in contact with each of these regions, and a highly doped N-type region 6 is further formed in the base region 2 in a portion where the base electrode 4 is to be formed for the purpose of lowering the contact resistance. The figure shows a transistor with Further, in this device, 7 is a surface-inactivated insulating film made of silicon dioxide, for example. Furthermore, in this device, an auxiliary diffusion region 8 of the same conductivity type as the emitter is selectively diffused and formed in the base region 2 so as to surround the emitter region 3 at the same time as the emitter region 3 is formed, so that the emitter junction and the base electrode are bonded. A resistance region 9 is provided for making the current path go around and compress under the auxiliary diffusion region 8,
This region 9 is used as a base ballast resistor.

In FIG. 2, a ballast resistor is formed in the emitter region to serve as an emitter ballast resistor. Furthermore, there is also a structure in which the ballast resistor is not formed in the semiconductor substrate, but is made of, for example, polycrystalline silicon by chemical vapor deposition, and is made into an emitter ballast resistor.

FIG. 3 shows an example of forming a ballast resistor using polycrystalline silicon. After forming the emitter region 3 and base/contact region 6 according to the normal transistor process, the oxide film 7 is selectively photoetched to expose a predetermined emitter surface, and polycrystalline silicon 10 is deposited on the entire surface. Then, this was patterned to form a connection electrode part with the metal wiring film at the other end, and the polycrystalline silicon film part parallel to the substrate between the emitter electrode in contact with the substrate emitter surface and the connection electrode was used as a resistance region 9. It is something.
This polycrystalline silicon 10 is doped with phosphorus or boron at the same time as it is deposited, or after the polycrystalline silicon 10 is formed, it is doped with phosphorus or boron at a high concentration by an impurity diffusion method. Generally, it has a small specific resistance value and is used as a horizontal resistor parallel to the surface of a thin film substrate. Furthermore, a protective film is formed separately from the above process in order to improve the reliability of the high voltage element.

1 and 2 have the disadvantage that the chip area increases because the resistor region 9 is formed redundantly within the substrate surface, and when the ballast resistor is provided outside the substrate as shown in FIG. 3, polycrystalline silicon is used. When adding impurities to 10, as the amount added increases, the resistivity changes rapidly from high resistance to low resistance, so it is necessary to control the amount added to obtain a resistivity between high resistance and low resistance. is difficult. Furthermore, since it is used as a horizontal resistor, the chip area increases.

On the other hand, it is very important to inactivate the semiconductor substrate surface by coating it with the insulator 7 in order to increase the reliability of the semiconductor device.
Conventionally, it has been known to coat the surface of a semiconductor substrate with an insulating film such as silicon dioxide, silicon nitride, or a hybrid film of polycrystalline silicon and silicon oxide by thermal decomposition or chemical vapor deposition, which is a separate process from improving the safe operating area. It is carried out in

The present invention improves the problems of the devices shown in FIGS. 1 to 3 above, and uses a vertical resistor to prevent an increase in chip area, thereby expanding the safe operating range and improving reliability. It is.

The present invention provides a device having a structure in which a semi-insulating film of a hybrid of polycrystalline silicon and silicon oxide coated physically or chemically deposited on the surface of a semiconductor substrate is used as a stabilizing film and a resistive layer. The resistance layer is formed by selectively doping impurities, and its resistance value is set to a predetermined value in an impurity addition step that also serves as base contact diffusion.

Embodiments of the present invention will be described below with reference to the drawings.
FIGS. 4a, b, c, and d illustrate the embodiment in the order of steps. In FIG. 4A, an N-type base region 2 is formed by phosphorus diffusion in a P-type silicon crystal substrate 1, and a P-type emitter region 3 is formed within this base region 2 by boron diffusion. Reference numeral 7 denotes an oxide film used as a mask for selective diffusion of the base region 2 and emitter region 3. In FIG. 4B, the oxide film 7 is completely removed, and a hybrid film 11 in which silicon oxide is mixed in polycrystalline silicon is formed on the substrate surface.

Compared to the electrical resistance of silicon oxide formed by ordinary thermal oxidation, a hybrid film of polycrystalline silicon and silicon oxide has a small electrical resistance and is less likely to be charged. Taking advantage of this property, it has often been used as a protective film for power transistors. In this example, SiH ₄ -N ₂ O-based gas is reacted in a reduced pressure CVD apparatus at a temperature of about 650°C. The reason why a low pressure CVD device was used is that the uniformity and reproducibility of the film is better than when using a normal pressure CVD device. In FIG. 4c, phosphorus is added onto the base electrode region of the composite film 11 to simultaneously form a high impurity concentration region 6 for ohmicly adhering the resistive layer 12 and the electrode. Also, although not shown, the second
It is also possible to form a resistive layer on the upper part of the emitter region 3 in the same manner as in FIG. Figure 4d
In this example, a base electrode 4 and an emitter electrode 5 are formed. In the case of the hybrid film 11 of polycrystalline silicon and silicon oxide, as the amount of addition increases, the resistivity changes gradually from a high resistance value to a low resistance value, so controllability is better, compared to when impurities are added to the polycrystalline silicon film. It has the advantage of providing high electrical resistance.

As described above, the device of the present invention has the advantage that the base ballast resistor is formed vertically in a small area with good controllability in order to expand the safe operation area, and the protective film is also formed at the same time, resulting in high reliability. It has the feature of obtaining the characteristics.

In this embodiment, the present invention is applied to a PNP transistor, but it is obvious that the same effect can be obtained by applying the present invention to an NPN transistor.

[Brief explanation of drawings]

1, 2, and 3 are structural cross-sectional views of a conventional device, and FIG. 4 a, b, c, and d are cross-sectional views illustrating an apparatus according to an embodiment of the present invention in the order of steps. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate of conductivity type, 2...Base region of opposite conductivity type, 3...Emitter region of one conductivity type, 4...
Base electrode, 5...Emitter electrode, 11...Mixed film of polycrystalline silicon and silicon oxide, 12...Mixed film resistance layer.

Claims (1)

[Claims] 1. A transistor having a composite film of a polycrystalline semiconductor and an oxide on the surface of a transistor configured by providing a base region of an opposite conductivity type in a semiconductor substrate of one conductivity type and an emitter region of the same conductivity type as the substrate in the base region. A semiconductor device further comprising a resistive layer formed in a predetermined portion of the composite film by controlling the resistivity of the composite film by adding an impurity of the same conductivity type as that of the base region or the emitter region.