JPH0132667B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to transistors, particularly transistors with emitter resistance. As shown in FIG. 1, a conventional transistor with emitter resistance is composed of an N-type silicon semiconductor substrate 1 serving as a collector region, a P-type base region 2, and an N-type emitter region 3. Many were used as emitter resistors. However, in such a structure, the emitter region 3 is formed with a high impurity concentration and cannot be made very large in area, so the upper limit of the emitter resistance value is about 1Ω at most, and there is also a drawback that the emitter resistance value varies due to variations in emitter diffusion. had. The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a transistor that completely eliminates the conventional drawbacks. Embodiments of the present invention will be described in detail below with reference to FIGS. 2 to 6. The transistor according to the invention is shown in FIGS.
As shown in the figure, a P-type silicon semiconductor substrate 10
, an N-type epitaxial layer 11 stacked on the surface of the substrate 10 , a P+-type isolation region 12 that penetrates the epitaxial layer 11 and reaches the substrate 10 , and an epitaxial layer surrounded by the isolation region 12 . 11, a P-type base region 14 formed by selective diffusion on the surface of the island region 13, and an N+ type base region 14 formed by selective diffusion on the surface of each base region 14. an emitter region 15 of the mold;
An N+ type buried layer 16 buried in the bottom of the epitaxial layer 11 under at least the base region 14 of each island region 13, and an N+ type collector contact region 17 that is diffused from the surface of the island region 13 and reaches the buried layer 16. a conductive metal collector electrode 18 extending in ohmic contact with and connected to the collector contact region 17 of each island region 13; and a conductive metal collector electrode 18 extending in ohmic contact with and connected to the base region 14 of each island region 13. Metal base electrode 19
, a connecting electrode 20 that is in ohmic contact with the emitter region 15 of each island region 13 and an adjacent separation region 12 , and an emitter electrode 21 that is in ohmic contact with the back main surface of the substrate 10 . The semiconductor substrate 10 is P with a low resistance of 0.015Ωcm or less.
It consists of a + type substrate substrate 101 and a P- type epitaxial layer 102 with a high resistance of about 10 Ωcm grown on it.
2 mainly acts as an emitter resistance. Therefore, the value of the emitter resistance can be freely designed depending on the specific resistance and thickness of the epitaxial layer 102, and specifically, the value of 200Ω or less can be arbitrarily selected depending on the application. On the surface of the semiconductor substrate 10 thus formed, epitaxial layer 11 is formed after selectively performing embedding diffusion in a portion where a predetermined embedding layer 16 is to be formed. This epitaxial layer 11 is laminated over the entire surface of the substrate 10 to a thickness of 15 μm with a resistance of 2 Ωcm, for example. During the formation of this epitaxial layer 11, the impurities in the buried diffusion are also re-diffused to form a buried layer 16 at the bottom of the epitaxial layer 11. The isolation region 12 is formed as a P+ type diffusion region that is selectively diffused from the surface of the epitaxial layer 11, penetrates the epitaxial layer 11, and reaches the semiconductor substrate 10. The shape of the separation region 12 is formed in a lattice shape, as is clear from FIGS. 3 and 4, or in rows, excluding the horizontal divisions of the lattice, as shown in FIG. Further, the outermost portion of the separation region 12 forms a frame so as to completely surround the inner portion. Such isolation region 12 is connected to substrate 10 and isolation region 1
A plurality of island regions 13 are formed separated by PN junctions formed by the epitaxial layer 2 and the epitaxial layer 11. This island region 13 has one or more transistor cells 22 as shown in FIGS. 4 and 5.
is formed. This transistor cell 22 has P on the surface of the epitaxial layer 11 which becomes the collector region of each island region 13.
It is formed by double-diffusing the type base region 14 and the N-type emitter region 15, and further includes each of the aforementioned island regions 1.
An N + type collector contact region 17 is formed by penetrating the epitaxial layer 11 of each island region 13 in order to take out from the buried layer 16 formed under the epitaxial layer 11 of No. ³ in a manner substantially corresponding to the base region 14. is diffused and connects the buried layer 16. The transistor cell 22 will be further described in detail with reference to FIG. In FIG. 3, the oxide film 23 covering the surface of the epitaxial layer 11 is shown as transparent. Island region 1 divided by grid-like separation regions 12
3, one transistor cell 22 is formed. A frame indicated by a dotted line inside the isolation region 12 is a buried layer 16 provided under the epitaxial layer 11, and as is clear from the drawing, its size is similar to that of the base region 14 and the collector contact region 17.
It is designed to include. Also, the oxide film 2 on the surface
3, the base region 14 of the collector contact region 17 and the emitter region 1 are etched using a known photoetching technique.
5 and the isolation region 1 adjacent to the emitter region 15
Contact holes shown by hatched areas on 2 are formed, respectively. Thereafter, a conductive metal such as aluminum is vapor deposited on the oxide film 23 and etched into a desired shape, thereby forming the collector electrode 18 and the base electrode 19 shown by dotted lines extending vertically in FIG. 3 and extending laterally. A connecting electrode 20 connecting the existing emitter region 15 and the isolation region 12 is formed. Further, the back main surface of the substrate 10 is lined with a conductive metal such as gold-chromium to form an emitter electrode 21, which is used for taking out the emitter and fixing the transistor to the header. Therefore, since the emitter region 15 of each transistor cell 22 is taken out from the emitter electrode 21 via the connection electrode 20 separation region 12 and the semiconductor substrate 10, each emitter region 15 has a torque resistance formed by the semiconductor substrate 10 as described above. It will be connected as an emitter resistor. Further, FIG. 4 shows the electrode pattern of the entire transistor. Collector electrode 18 and base electrode 1 in ohmic contact with collector contact region 17 and base region 14 of each transistor cell 22
The numerals 9 extend in a comb-teeth shape on opposite sides in the vertical direction and converge on the bonding pad. Further, the connection electrode 20 is provided in each cell 22 and is led to the emitter electrode 21 using the separation region 12 adjacent to the emitter. The transistor shown in FIG. 5 is another embodiment of the present invention in which a large number of transistor cells 22 are formed in one island region 13, and has the above-described lattice-shaped isolation region 12 except for the shape of the isolation region 12. It is formed similarly to the transistor embodiment. The inventor formed the following three samples by setting the area of the emitter region 15 of the transistor cell 22 to 5×10 ^-3 mm ² and varying the thickness of the epitaxial layer 11.

[Table] In this table, V _CEO is the collector-emitter voltage, I _C is the collector current, and R _E is the emitter resistance. Further, the reason why the emitter resistance of each sample is constant at 25Ω is because the emitter resistance depends only on the semiconductor substrate 10 as described above. Therefore, by changing the thickness or conductivity of the epitaxial layer 102 of the semiconductor substrate 10 and changing the emitter resistance, it is possible to rapidly reduce the current amplification factor _hFE at a desired collector current value as shown in FIG. This makes it possible to provide a collector current limiting function. Furthermore, since the present invention has this good self-collector current limiting function, the safe operating area of the transistor is reduced.
This has the advantage that the portion of the ASO that is limited by the maximum collector current Ic _MAX can be greatly expanded. This result has a particularly large effect on high f _T transistors where the maximum collector current Ic _MAX is subject to large limitations.

[Brief explanation of drawings]

FIG. 1 is a sectional view illustrating a conventional transistor, and FIG. 2 is a sectional view illustrating a transistor of the present invention, which approximately corresponds to the cross-sectional view taken along the line - in FIG.
FIG. 3 is a plan view explaining the transistor of the present invention, FIGS. 4 and 5 are plan views explaining the electrode pattern of the transistor of the present invention, and FIG. 6 is a characteristic diagram explaining the operation of the transistor of the present invention. It is. Explanation of main figure numbers: 10 is a semiconductor substrate, 11 is an epitaxial layer, 12 is an isolation region, 13 is an island region, 14 is a base region, 15 is an emitter region, 1
6 is a buried layer, 17 is a collector contact region, 18 is a collector electrode, 19 is a base electrode, 2
0 is a connection electrode, 21 is an emitter electrode, and 22 is a transistor cell.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type and a first emitter resistor of the same conductivity type formed on the semiconductor substrate.
a second epitaxial layer of opposite conductivity type provided on the surface of the first epitaxial layer; and a conductive layer that penetrates the second epitaxial layer and reaches the first epitaxial layer. a plurality of island regions formed of a mold isolation region and a second epitaxial layer surrounded by the isolation region; a base region of one conductivity type diffused on the surface of the island region; and a base region of one conductivity type diffused on the surface of the base region. An emitter region of opposite conductivity type, a buried layer of opposite conductivity type provided at the bottom of the island region, a collector contact region of reverse conductivity type reaching from the surface of the island region to the buried layer, and the collector contact region of each island region are in ohmic contact. a connecting electrode that is in ohmic contact with the connected collector electrode and the base region of each island region, and in ohmic contact with the connected base electrode and the emitter region of each island region, and in ohmic contact with the adjacent separation region; A transistor comprising an emitter electrode in ohmic contact with the principal surface of the substrate. 2. The transistor according to claim 1, wherein the isolation region has a lattice shape.