JPH0156530B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to transistors, particularly transistors with emitter resistance. As shown in FIG. 1, a conventional transistor with low emitter resistance is composed of an N-type silicon semiconductor substrate 1 serving as a collector region, a P-type base region 2, and an N-type emitter region 3. In many cases, the resistor was used as an emitter resistor. However, in such a structure, the emitter region 3 is formed with a high impurity concentration and cannot be made very large in area, so the upper limit of the emitter resistance value is about 1Ω at most, and there is also a drawback that the emitter resistance value varies due to variations in emitter diffusion. had. The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a transistor that completely eliminates the conventional drawbacks. Embodiments of the present invention will be described in detail below with reference to FIGS. 2 to 6. The transistor according to the invention is shown in FIGS.
As shown in the figure, a P-type silicon semiconductor substrate 10
, an N type epitaxial layer 11 grown on the surface of the substrate 10 , an N ⁺ type buried layer 12 selectively provided at the bottom of the epitaxial layer 11 , and a layer extending from the surface of the epitaxial layer 11 to the buried layer 12 . In addition, the epitaxial layer 11 is formed into a plurality of island regions 1.
A connection between an N ⁺ type collector contact region 14 divided into 3, 13...13 and at least one P ⁺ type provided in each island region 13 and extending through the epitaxial layer 11 to the substrate 10. Area 15
and a P-type base region 1 surrounding the connection region 15 and formed on the surface of the island region 13 on the buried layer 12.
6, an N-type emitter region 17 formed on the surface of the base region 16 and surrounding the connection region 15, a conductive metal collector electrode 18 in ohmic contact with the collector contact region 14, and an ohmic contact with the base region 16 of each island region 13. a conductive metal base electrode 19 connected and extended; and each island region 1;
A connecting electrode 20 made of a conductive metal is in ohmic contact with the emitter region 17 of the substrate 1 and in ohmic contact with the connecting region 15 surrounded by the emitter region 17;
The emitter electrode 21 is made of a conductive metal and is in ohmic contact with the back main surface of the 0. The semiconductor substrate 10 has a low resistance of 0.015Ωcm or less ^.
A type substrate substrate 101 and a high resistance P ^- type epitaxial layer 1 of about 10 Ωcm grown on it.
02, this epitaxial layer 102
acts mainly as emitter resistance. Therefore, the value of the emitter resistance can be freely designed depending on the specific resistance and thickness of the epitaxial layer 102, and specifically, the value of 200Ω or less can be arbitrarily selected depending on the application. On the surface of the semiconductor substrate 10, after selectively performing embedding diffusion in a portion where a predetermined embedding layer 12 is to be formed, an epitaxial layer 11 is formed. This epitaxial layer 11 is spread over the entire surface of the substrate 10, for example.
Laminated with 2Ωcm and 15μm thick. During the formation of this epitaxial layer 11, the impurities in the buried diffusion are also re-diffused to form a buried layer 12 at the bottom of the epitaxial layer 11. The collector contact region 14 is selectively diffused from the surface of the epitaxial layer 11 and is formed to reach the buried layer 12 under the epitaxial layer 11. The collector contact region 14 is formed in a lattice shape as shown in FIGS. 3 and 4, or in rows excluding the horizontal divisions of the lattice as shown in FIG. Further, an isolation region 22 is formed outside the collector contact region 14 at the same time as the connection region 15 so as to surround the collector contact region 14, thereby insulating the collector from the side surface of the substrate 10. The collector contact region 14 divides the epitaxial layer 11 into a plurality of island regions 13 . Further, the above-mentioned buried layer 12 is arranged below the collector contact region 14 and extends to below the base region 16. This island area 13 has a fourth
As shown in the figure and FIG. 5, one or more transistor cells 23 are formed. This transistor cell 23 has a connection region 15 in the center which is a P ⁺ type diffusion region that penetrates the epitaxial layer 11 and reaches the substrate 10, and a double-diffused annular P type region surrounding this connection region 15. It is composed of a base region 16, an N-type emitter region 17, and a buried layer 12 extending from the collector contact region 14 described above to at least a portion corresponding to the bottom of the base region 16 below the epitaxial layer 11. The transistor cell 23 will be further described in detail with reference to FIG. In FIG. 3, the oxide film covering the surface of the epitaxial layer 11 is shown as transparent. One transistor cell 23 is formed in an island region 13 divided by a collector contact region 14 in a lattice shape. A frame indicated by a dotted line just outside the connection region 15 indicates that the buried layer 12 provided below the epitaxial layer 11 has been extended from below the collector contact region 14 to this point, and the buried layer 12 is connected to the connection region 15. This shows that the area has been expanded to almost the entire area except for the area around the area. Further, in the surface oxide film 24, contact holes shown by hatched areas are formed on the collector contact region 14, base region 16, emitter region 17, and connection region 15, respectively, by a known photoetching technique.
After that, a conductive metal such as aluminum is coated with an oxide film 24.
The collector electrode 18 and the base electrode 19 shown by dotted lines extending in the vertical direction in FIG. A connection electrode 20 is formed to connect the two.
Further, the collector electrode 18 is in continuous ohmic contact with the collector contact region 14 in the vertical direction, and two base electrodes 19 are provided in the connection region 15 of the annular base region 16 at axisymmetric positions and parallel to the collector electrode 18. It has been extended. Furthermore, the substrate 10
The back main surface of the transistor is lined with a conductive metal such as gold-chromium to form an emitter electrode 21, which is used for taking out the emitter and fixing the transistor to the header. Further, FIG. 4 shows the electrode pattern of the entire transistor. The collector electrode 18 extends in a comb-teeth shape in continuous ohmic contact along each column direction of the grid-shaped collector contact region 14, and converges at one end on a bonding pad. Further, two base electrodes 19 which are in ohmic contact with the base region 16 of each transistor cell 23 and which sandwich the connection electrode 20 are also extended in a comb-teeth shape and converged into a bonding pad on the opposite side of the collector electrode 18. Further, the connection electrode 20 is provided for each transistor cell 23 and guides the emitter to the emitter electrode 21 using the connection region 15. The transistor shown in FIG. 5 is another embodiment of the present invention in which a large number of transistor cells 23 are formed in one long island region 13 in the form of a row, and the point that the shape of the collector contact region 14 is made into a row is that Except for this, it is formed in the same manner as the embodiment of the transistor having the lattice-shaped collector contact region 14 described above. The present inventor formed two samples shown in the following table by setting the area of the emitter region 17 of the transistor cell 23 to 1×10 ^-2 mm ² and varying the bulk resistance of the semiconductor substrate 10.

[Table] In this table, V _CEO is the collector-emitter voltage, I _C is the collector current, and R _E is the emitter resistance. In both samples shown in the above table, only the emitter resistance R _E is controlled by the substrate 10, and the transistor cells 23 formed in the epitaxial layer 11 are the same. Therefore, by changing the thickness or conductivity of the epitaxial layer 102 of the semiconductor substrate 10 to change the emitter resistance, a good collector can be created in which the current amplification factor _hFE can be rapidly reduced at a desired collector current value, as shown in FIG. It becomes possible to provide a current limiting function. Furthermore, in the transistor according to the present invention, since the buried layer 12 of the collector is provided in a lattice or row pattern over almost the entire surface except for the connecting region 15, the collector resistance can be kept extremely low, and in the region where the collector current is large, the self-resistance due to the emitter resistance is reduced. It is suitable for large current transistors because it can fully utilize the collector current limiting function.

[Brief explanation of drawings]

FIG. 1 is a sectional view illustrating a conventional transistor, and FIG. 2 is a sectional view illustrating a transistor of the present invention, which approximately corresponds to the cross-sectional view taken along the line - in FIG.
FIG. 3 is a plan view explaining the transistor of the present invention, FIGS. 4 and 5 are plan views explaining the electrode pattern of the transistor of the present invention, and FIG. 6 is a characteristic diagram explaining the operation of the transistor of the present invention. It is. Explanation of main figure numbers: 10 is a semiconductor substrate, 11 is an epitaxial layer, 12 is a buried layer, 13 is an island region, 14 is a collector contact region, 15 is a connection region, 16 is a base region, 17 is an emitter region,
18 is a collector electrode, 19 is a base electrode, 20 is a connection electrode, 21 is an emitter electrode, and 23 is a transistor cell.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type and a first emitter resistor of the same conductivity type formed on the semiconductor substrate.
an epitaxial layer, a second epitaxial layer of opposite conductivity type provided on the surface of the first epitaxial layer, and a buried layer of opposite conductivity type selectively provided at the bottom of the second epitaxial layer. The second epitaxial layer is divided into a plurality of island regions, and includes a collector contact region of an opposite conductivity type that reaches the buried layer, and a collector contact region of the opposite conductivity type that is provided in the island region and penetrates the second epitaxial layer. at least one connection region of one conductivity type reaching the epitaxial layer of the second epitaxial layer; and a base of one conductivity type provided to surround the connection region and diffused into the second epitaxial layer on the buried layer. an emitter region of opposite conductivity type diffused on the surface of the base region so as to surround the region and the connection region; a collector electrode in ohmic contact with the collector contact region; and a collector electrode in ohmic contact with the base region of the island region and connected thereto. A transistor comprising: a connection electrode that is in ohmic contact with a base electrode and the emitter region; and a connection electrode that is in ohmic contact with the connection region surrounded by the emitter region; and an emitter electrode that is in ohmic contact with the main surface of the substrate. 2. The transistor according to claim 1, wherein the collector contact region has a lattice shape.