JPH0135543B2 - - Google Patents

Description

[Detailed description of the invention]

[Field to which the invention pertains] The present invention. The present invention relates to an improvement of an image processing device that encodes a binary image. [Prior Art] Conventionally, when encoding a binary image using software, encoding takes time, so it has been difficult to encode it in real time. [Object of the Invention] The present invention was made to solve the above-mentioned problems, and its purpose is to realize an image processing device that encodes a binary image in real time. [Summary of the Invention] In order to achieve the above object, the gist of the present invention is that the combination of signal values of two pixels adjacent in the scanning direction in a binary image signal is "01",
Y where the signal value is 1 at “10” and “11” respectively
a decoder that generates 1, Y2, and Y3 outputs, a length counter that is preset to 1 by the Y1 output and counts up by the Y3 output, a code address counter that counts up by the Y1 output, and a pixel being scanned. x of
and an X and Y address counter that generates a y-coordinate, and is addressed by the output of said code address counter, written with the output of said address counter by said Y1 output, and said Y2
and a code memory into which the output of the length counter is written according to the output. [Embodiments of the Invention] The present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. 1 is a 2-bit shift register into which a binary image signal and an image scanning clock are input, and whose contents are the signal values of two pixels adjacent in the scanning direction; 2 is output from the Q1 and Q2 terminals of this shift register 1. Input binary signals to the A and B input terminals respectively, and the combination of A and B inputs is "01", "10", "11"
Y1, Y2, Y whose signal value is 1 when
A decoder that generates 3 outputs, 3 is this decoder 2
4 is a length counter that is preset to 1 by the Y1 output and counted up by the Y3 output; 4 is a code address counter that is counted up by the Y1 output; 5;
6 are X and Y address counters that generate the x and y coordinates of the pixel being scanned, respectively.
7 is a code memory, of which 71 is a Y start address section into which the contents of the Y address counter 5 are written by the Y1 output, and 72 is the Y start address section where the contents of the Y address counter 5 are written by the Y1 output.
73 is a length section in which the contents of the length counter 3 are written in response to the Y2 output from the decoder 2. 8
is a code address latch that latches the contents of the code address counter 4 by the Y2 output;
9 stores the contents of the code memory 7 and the code address latch 8 in a processor (not shown in the figure).
It is a data bus that transmits data to other devices. The operation of the image processing apparatus having such a configuration will be described next. FIG. 2 is an explanatory diagram showing an example of a binary image processed by the above image processing apparatus. The x-coordinate of each pixel is shown on the upper right of the binary image, and the y-coordinate of the pixel is shown on the left side. Table 1 shows the operation when the binary image signal for the pixel on the first line (ie, the y coordinate is 0 in FIG. 2) is applied to the D input of the shift register 1. i.e. the scan clock

【table】

[Table] Therefore, "00", "00", "01", "11", etc. appear in the Q1 and Q2 outputs of the shift register 1.
These outputs become the A and B inputs of decoder 2,
Generate corresponding outputs Y1, Y2, Y3.
When the A and B inputs (combination) are "00", the decoder 2 generates no output. Object as “1”,
If the background is "0", when the A and B inputs are "01", it indicates the starting point of the object, so the Y1 output will be 1,
The code address counter 4 is incremented by one, and the contents of the X and Y address counters 5 and 6 are addressed by the output of the code address counter 4 and stored in the Y start address section 71 and the X start address section 72 of the code memory 7, respectively. At the same time as writing, length counter 3 is preset to 1. When the A and B inputs are "11", it indicates that it is inside the object, so
The Y3 output becomes 1, and the contents of the length counter 3 are incremented by one. When the A and B inputs are "10", it indicates the end point of the object, so the Y2 output becomes 1 and the output of the length counter 3 is determined by the output of the code address counter 4 of the length section 73 in the code memory 7. written to the specified address. By repeating this process, 2
The value image is encoded by the start address of a run of "1"s and its length. Table 2 shows the contents of the code memory 7 when the binary image example shown in FIG. 2 is processed. When processing for one screen is completed,

【table】

Claims (1)

[Claims] 1 2 adjacent in the scanning direction in the binary image signal
The combination of pixel signal values is “01”, “10”, “11”
When Y, the corresponding signal value is 1
a decoder that generates 1, Y2, and Y3 outputs, a length counter that is preset to 1 by the Y1 output and counts up by the Y3 output, a code address counter that counts up by the Y1 output, and a pixel being scanned. x of
and an X and Y address counter that generates and y coordinates, addressed by the output of the code address counter, written by the Y1 output to the output of the X and Y address counter, and by the Y2 output to the output of the length counter. An image processing device comprising: a code memory in which is written.