JPH0137772B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of an incircuit emulator, the purpose is to check the internal bus of the target system prior to system debugging work on the target system, and provide addresses and data to the target system. The data bus and address bus that connect the proxy CPU and the CPU socket connected to the address bus and data bus inside the target system and the proxy CPU, and the first
Controllable bus buffer and address bus of CPU
Bus section near the socket, buffer and substitute CPU
a first return path connecting a data bus section between the address bus and the CPU socket and having a second controllable buffer, a bus section of the address bus close to the CPU socket, and a data bus section between the buffer and the CPU socket; and a second return path having a second controllable buffer, and selectively making the first, second, and third controllable buffers high impedance. A control means for selectively selecting the second return path is provided.

[Industrial application field]

The present invention relates to improvements in in-circuit emulators.

In-circuit emulators are used to efficiently design and develop high-speed, multifunctional microprocessor application systems. This takes over the CPU functions of the prototype machine and efficiently debugs the system according to the debugging program.

[Conventional technology]

Conventional in-circuit emulators use an emulation control unit 1, trace memory 2, proxy memory 3, etc. to connect the terminals of a proxy CPU 4 that operates with a required program to a CPU socket 5 of a target system, as shown in FIG. Generally, after removing the microprocessor from the prototype, the plug from the emulator is inserted into its socket and connected to the development tools including the various types of memory mentioned above. As shown in FIG. 4, the basic usage method is to address the target system 9 from the proxy CPU 4 via the buffer 7,
System debugging is performed by comparing or analyzing the data obtained via the bidirectional buffer 8 and the written data. Note that emulation control is performed by loading a required program into the program memory 6.

[Problem to be solved by the invention]

The number of signal lines on the CPU bus in a target system increases as the performance of the CPU increases, and complex wiring is formed to connect to many LSIs, resulting in etching residue and other various causes. As a result, shorts may occur between the bus signal lines, or between the bus signal lines and the power supply. These shortcuts have the disadvantage that normal debugging cannot be performed because the CPU bus is physically fixed.

The present invention was created in view of the above problems, and an object of the present invention is to provide an in-circuit emulator that checks the internal bus of a target system prior to system debugging work on the target system.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in this figure, the present invention is composed of the following components.

A proxy CPU 4 that provides addresses and data to the target system 9; and a data bus 12 that connects the proxy CPU 4 to the CPU socket 5 that is connected to the address bus and data bus inside the target system 9.
an address bus 13; a first controllable buffer 20 interposed in the data bus 12; and the CPU socket 5 of the address bus 12.
bus section near to, the bus station 20 and the agency
Connect the data bus section between the CPU 4 and the second
a first loopback path 23 having a controllable buffer 21 of the CPU socket 5 of the address bus 12;
a bus section close to , the bus section 20 and the CPU
Connect the data bus section between the socket 5 and
a second folding path 27 having a third controllable buffer 25; and selectively placing the first, second and third controllable buffers 20, 21, 27 at high impedance; a control means 29 for selectively selecting the first or second return path; and a control means 29 for diagnosing the address bus inside the target system 9 by selecting the first return path 23; The present invention is configured to diagnose the data bus inside the target system by selecting the path.

[Effect]

When detecting a fault in the address bus in the target system 9, the proxy CPU 4 sends a required signal via the address bus 12 and the signal is
Target system 9 via CPU socket 5
address bus within. The applied signal also causes the first and third controllable buffers 20, 25 to be set in a high impedance state by the control means 29 and the second controllable buffer 21
is pulled into the proxy CPU 4 via the first return path 23 selected by setting on,
It is used for failure analysis.

Further, when detecting a fault in the data bus within the target system 9, the selection of the second return path 27, that is, the setting of the second controllable buffer 21 to a high impedance state by the control means 29 and the first and third By setting the controllable buffers 20 and 25 to ON, the signal applied from the proxy CPU 4 to the data bus in the target system 9 via the address bus 12 is pulled in by the proxy CPU 4 via the data bus 13, and the signal applied to the data bus in the target system 9 is Used to analyze data bus failures within the system.

Since the normality of each bus is checked prior to debugging the target system, debugging will not be inconvenienced by bus failures.

〔Example〕

FIG. 2 is a block diagram of one embodiment of the present invention, in which two tri-state buffers 14 and 15 are provided in addition to the buffers 7 and 8 shown in FIG. These buffers 14 and 15 are the address bus 12.
It controls signals going from the test mode register 1 to the data bus 13, as described later.
On-off control is performed by the control outputs C ₁ and C ₃ of No. 1.
In addition, during the pass through buffers 14 and 15,
By providing a ROM, it is also possible to convert the address data into a required state and put it on the data bus 13. Further, a program memory 10 for bus testing is added to the program memory 6 for emulation control, and a bus test is performed under program control. Here, to test the address bus 12, the control output of the test mode register 11 is
_C1 to _C3 turn on the buffer 14 and control the buffers 8 and 15 to a high impedance state, and apply the signal on the address bus 12, that is, to the internal address bus of the target system 9 via the CPU socket 5. data bus 1
3 to the proxy CPU 4 side. When testing the data bus 13, the tri-state buffer 14 is controlled to high impedance, and the tri-state buffers 8 and 15 are turned on to send address data to the data bus 13, that is, for the CPU of the target 9. It supplies its internal data bus via socket 5 and also serves as a proxy CPU.
4 side and analyze it to check for short circuits, etc.

〔Effect of the invention〕

As described above, according to the present invention, the occurrence of a physical failure in the bus such as a short circuit in the target system can be clearly identified, so that debugging work can be performed accurately.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of an in-circuit emulator, and Fig. 4 is a block diagram of a conventional in-circuit emulator. It is an explanatory diagram of existing problems. In Figure 2, 4 is the substitute CPU, 5 is the CPU socket, 7, 8, 14, 15, 20, 21, 2
5 is buffer, 9 is target system, 23,
27 is a return path, 29 is a control means (program memories 6, 10, test mode register 11)
It is.

Claims (1)

[Scope of Claims] 1. A proxy CPU 4 that provides addresses and data to the target system 9; and a data bus 12 that connects the CPU socket 5 connected to the address bus and data bus inside the target system 9 and the proxy CPU 4.
and an address bus 13; a first controllable buffer 20 provided on the data bus 12; and the CPU socket 5 of the address bus 12.
bus section near to, the bus station 20 and the agency
Connect the data bus section between the CPU 4 and the second
a first loopback path 23 having a controllable buffer 21 of the CPU socket 5 of the address bus 12;
a bus section close to , the bus section 20 and the CPU
a second return path 27 connecting the data bus section with the socket 5 and having a second controllable buffer 25; the first, second and third controllable buffers 20; 21 and 27 selectively set to high impedance, the control means 29 selectively selects the first or second return path, and the target is selected by selecting the first return path 23. An in-circuit emulator characterized in that the address bus inside the system 9 is diagnosed and the data bus inside the target system 9 is diagnosed by selecting the second return path 27.