JPH0137793B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical character reading system that can accurately read characters, numbers, symbols, etc. that are larger than the field of view of a two-dimensional sensor.

In the general optical character reading method, as shown in FIG. The image is formed on the arranged two-dimensional sensor 2, and the analog signal from the two-dimensional sensor 2 is converted into a binary signal corresponding to the character area and the background area by the binarization circuit 3, and this binary signal ( The identification circuit 4 identifies characters based on the white/black pattern (hereinafter referred to as a white/black pattern). On this occasion. In the vertical direction 7,
The two-dimensional sensor 2 is electrically scanned, and the horizontal direction 8
In this case, the two-dimensional sensor 2 is electrically scanned, and the optical system and paper are mechanically and relatively moved to read characters. still,
The paper 5 is illuminated by a light source (not shown).

As shown in FIG. 2A, if the entire character to be read is within the field of view 9 of the two-dimensional sensor 2, the above-mentioned However, when reading a character larger than the width of the field of view 9 of the two-dimensional sensor 2, as shown in FIG.
are moved at a predetermined speed relative to each other, and the white/black pattern when the left end of the character enters the visual field 9 to the white/black pattern when the right end of the character enters the visual field 9 is used. It is necessary to synthesize the white/black pattern of the entire character, and to identify the character based on this synthesized white/black pattern. When the two-dimensional sensor 2 and the paper 5 move relatively at a predetermined constant speed, characters larger than the field of view 9 can be read as described above. If the relative speed between the two-dimensional sensor 2 and the paper 5 is not constant, such as when moving the character, the white/black pattern of the entire character obtained as described above will be a deformation of the original pattern. , it had the disadvantage that it was difficult to read the text. That is, if the relative speed between the two-dimensional sensor 2 and the paper 5 is too slow, a white/black pattern that extends horizontally will result, and if it is too fast, a white/black pattern will contract horizontally, resulting in a character The problem was that it was difficult to read. In order to improve this drawback, it is possible to change the electrical scanning speed according to the relative speed between the two-dimensional sensor 2 and the paper 5, but this requires a speed detection function and requires control. It has the disadvantage of being complicated.

Regarding the idea of using a two-dimensional sensor with a large bit configuration for characters with a large width, (i) a two-dimensional sensor with a large bit configuration is expensive.

(ii) The time required for identification processing increases.

There are drawbacks such as.

For this reason, conventionally, it has been difficult and uneconomical to read characters larger than the field of view of a two-dimensional sensor.

The present invention has improved the above-mentioned drawbacks, and its purpose is to print characters larger than the field of view of a two-dimensional sensor even when the relative moving speed between the two-dimensional sensor and paper is not constant. , accurate reading in an economical configuration. Examples will be described in detail below.

First, the method of the present invention will be briefly explained with reference to FIGS. 3A and 3B. In the method of the present invention, as shown in FIG. Character identification based on the white/black pattern obtained by the time the predetermined position is reached (in this case, it is assumed that the white/black pattern for 6 screens b ₁ to b ₆ shown in Figure B is obtained). However, as in the conventional method, the obtained white/black patterns are directly synthesized to obtain a composite white/black pattern for the entire character, and characters are identified based on this composite white/black pattern. Instead, each time a new white/black pattern of the screen is obtained as the two-dimensional sensor scans in the horizontal direction, the white/black pattern of that part is calculated in units of multiple lines based on the white/black pattern. Find the row feature code that indicates the feature of the shape,
This line feature code and the corresponding composite feature codes up to the previous screen are combined to create a new composite feature code, thereby obtaining the composite feature code for the entire character, and based on this composite feature code. It is used to identify characters. That is, when the left end of the character reaches a predetermined position in the field of view of the two-dimensional sensor and the white/black pattern of screen _b1 shown in Figure B is obtained, the line feature code for multiple lines is determined as described above. is obtained for one screen, and when the white/black pattern of screen b ₂ is obtained as the two-dimensional sensor scans in the horizontal direction, a row feature code for screen b ₂ is created, and this row feature code is Create a composite feature code by combining the corresponding row feature codes of screen b ₁ , and if the white/black pattern of screen b ₃ is obtained as the two-dimensional sensor scans in the horizontal direction. For example, create a row feature code for screen b ₃ , and then create a new composite feature code by combining the corresponding row feature codes and the composite feature codes obtained up to screen b ₂ . This process is performed up to screen _b6 , and the resulting composite feature code for the entire character is used to perform identification processing. As described above, the method of the present invention synthesizes the row feature code indicating the characteristics of a white/black pattern in units of multiple rows newly obtained as the horizontal movement moves, and the previously synthesized feature code to generate a new one. A composite feature code is created for the entire character, and characters are identified based on this composite feature code. Even if the relative moving speed is not constant, the composite feature code of the entire character that is finally obtained will correspond to the character, so even if the relative moving speed is not constant, the two-dimensional sensor Characters larger than the visual field can also be accurately identified.

FIG. 4 is a block diagram of an embodiment of the present invention, in which 12 is a two-dimensional sensor in which photoelectric conversion elements are arranged two-dimensionally, 13 is a binarization circuit, 14 is a row feature extraction circuit, and 15 is a two-dimensional sensor in which photoelectric conversion elements are arranged two-dimensionally. 1 is a character movement detection circuit; 16 is a composite feature extraction circuit; 17 is a composite feature storage circuit;
8 is an identification circuit, and 19 is an interface circuit that performs format checking of identification results or data conversion for matching the interface with a host computer system. In addition, two-dimensional sensor 1
2, as shown in Fig. 5, photoelectric conversion elements are arranged in m rows x
It is arranged in 5 rows, from the 1st row to the 5th row.
Analog signals V ₁ to V ₅ corresponding to the photoelectric conversion elements arranged in columns are sequentially outputted from the first row to the m rows.

The binarization circuit 13 converts the analog signals V ₁ to _{V 5} from the two-dimensional sensor 13 into binary signals A ₁ to A ₅ corresponding to the character area and the background area,
The binary signals A ₁ to _{A 5} are applied to the line feature extraction circuit 14 , and the binary signals A ₂ to A ₄ corresponding to the analog signals V ₂ to _{V 4} are applied to the character movement detection circuit 15 .

The row feature extraction circuit 14 creates a row feature code for each three rows based on the binary signal from the binarization circuit 13, and has the configuration shown in FIG. 6, for example. In the figure, 20 is a parallel-to-serial converter, 21 and 22 are 6-stage shift registers, and 2
3 is a read-only memory (hereinafter abbreviated as memory), 24
is a latch circuit. 7 is an explanatory diagram of the operation of FIG. 6, FIG. 8 is a diagram showing an example of the correspondence between row feature codes and black and white patterns, and FIG. 9 is a diagram illustrating the row feature extraction circuit 1.
4 shows a part of the state transition diagram of No. 4.

The parallel-to-serial conversion circuit 20 converts 5-bit binary signals A ₁ to A ₅ output in parallel from the binarization circuit 13.
_are written in accordance with the timing of the clock signal CK _{1 shown} in FIG _. The clock signal shown in Figure 7
It is read out one bit at a time according to the timing of _CK2 . The binary signal output one bit at a time from the parallel-to-serial converter 20 is applied to a shift register 21 and a memory 23 which are operated by the clock signal CK ₂ , and the output of the shift register 21 is input by the clock signal CK ₂ . shift register 2
2 and memory 23, and the output of shift register 22 is also applied to memory 23. Therefore, the binary signals of three rows in the same column are applied to the memory 23 at the same time.

Furthermore, the latch circuit 24 is cleared by the clock signal CK ₁ and starts a state transition from an initial state (for example, all zeros), and its output (for example, 8 bits) is added to the memory 23 for parallel-to-serial conversion. The address of the memory 23 is determined together with the outputs of the shift register 20 and shift registers 21 and 22. The memory 23 includes a parallel-to-serial converter 20 and a shift register 2.
1, 22, and the data (for example, 8 bits) written in the address determined by the output of the latch circuit 24, and adds it to the latch circuit 24.
The latch circuit 24 transfers this data to the clock signal _CK2.
Latch according to. Therefore, at timing _T5 of clock _CK2 , data based on the binary signals of the first to fifth columns for three rows is set in the latch circuit 24. 2
By writing data corresponding to a state transition in which the row characteristic code is set in the lower five bits of the clock signal CK2 to the memory 23, the row characteristic code is set in the latch circuit at timing _T2 of the clock signal _CK2 . It can be set to the lower 5 bits of 24.

The above operation will be explained as follows with reference to the state transition diagram of FIG. When the initial state K ₀ ,
That is, the latch circuit 24 is activated by the clock signal _CK1 .
If, for example, a binary signal indicating black, white, and white is added to the memory 23 from the top as a binary signal for three rows in the first column when is cleared, the state of the row feature extraction circuit 14 transitions to intermediate state _K1 . At this time, the latch circuit 24 has an intermediate state K ₁
The data corresponding to is latched.

Next, when the binary signals for three rows of the second column are applied to the memory 23, the memory 23 is loaded with the binary signals and the data corresponding to the intermediate state K1 latched in the latch circuit ₂₄ . The data written in the determined address is read and the latch circuit 24
latches the output data from memory 23 according to the timing of clock signal _CK2 . When the binary signals for three rows in the second column indicate, for example, black, white, and white from the top, data corresponding to the intermediate state _K2 is latched in the latch circuit 24, and the row feature extraction circuit 14 latches the data corresponding to the intermediate state K2. The state transitions to intermediate state _K2 , and when the binary signal indicates black, black, and white from the top, data corresponding to intermediate state _K3 is latched in the latch circuit 24, and the row feature extraction circuit State 14 transitions to intermediate state _K3 .

Thereafter, the state of the row feature extraction circuit 14 is updated in the same manner, and when the binary signal for three rows in the fifth column is added, the memory 23 stores this binary signal and the output of the latch circuit 24. The latch circuit 24 reads out the data written in the address determined by the latch circuit 24, and latches this data at timing _T2 of the clock signal _CK2 . When the state of the row feature extraction circuit 24 is in the intermediate state _K5 at the time when the binary signals for three rows in the fourth column are added, the binary signals for three rows in the fifth column are output as black and white from the top. , is added indicating white, the latch circuit 24 latches the data corresponding to the state _K7 at timing _T5 of the clock signal _CK2 , and the state of the row feature extraction circuit 14 transitions to state _K7 , Also, when the binary signals for three rows in the fifth column are black, black, black from the top, the latch circuit 24 latches the data corresponding to state _K8 at timing _T5 of clock signal _CK2 , and The state of the feature extraction circuit 14 becomes state _K8 . In addition, the row feature extraction circuit 24
When is in the intermediate state _K6 , when a binary signal indicating black, black, and white is added from the top for three rows of the fifth column, the latch circuit 24 receives data corresponding to the state _K7 . It is latched and the state of the row feature extraction circuit 24 transitions to state _K7 . When the row feature extraction circuit 14 reaches state _K7 , a signal corresponding to the row feature code "5" shown in _FIG . A signal corresponding to the feature code “23” is output and applied to the composite feature extraction circuit 16.

Further, the character movement detection circuit 15 to which binary signals A ₂ , A ₃ , A ₄ corresponding to the second to fourth rows of the two-dimensional sensor 12 are applied from the binarization circuit 13 performs horizontal scanning. As a result, character images formed on the light receiving surface of the two-dimensional sensor 12, for example, as shown in FIGS. 10A to 10C.
In the case of the change as shown in Figure B, when a character element appears on the third row of the two-dimensional sensor, the start signal ST is applied to the synthetic feature extraction circuit 16, and as shown in Figure C, , when a character element disappears from the third line, an end signal ED is applied to the composite feature extraction circuit 16 and the interface circuit 19, and has the configuration shown in FIG. 11, for example. In the figure, FF1 to FF7 are flip-flops, AND1 to AND4 are AND gates,
OR1 is an OR gate, and IN1 and IN2 are inverters. In addition, flip-flops FF1 to FF3 are
The output of the Q terminal is added to the SET terminal,
When the output of the terminal becomes "0", the output of the Q terminal is kept at "1" and the output of the terminal is kept at "0" until the signal applied to the CLR terminal via inverter IN1 becomes "0". It is something. Also, the first
2A to 2S are explanatory diagrams of the operation of FIG. 11 when the character image formed on the light receiving surface of the two-dimensional sensor 12 changes as shown in FIGS. 10A to C, and the screen n, (n+1) and (n+m) correspond to FIG. 10A, B, and C, respectively.

The clock signal CK1 shown in FIG. 12A, which is synchronized with the output processing of the binarization circuit 12, is applied as a clock signal to the CK terminals of flip-flops _FF1 to FF3, and the data is applied to the D terminals.
Binary signals A ₃ , A 2 , and A ₂ shown in E, D, and F of the figure, respectively
A ₄ (“1” corresponds to the character area and “0” to the background area) is added to the CLR terminal, and the clock signal CK ₃ shown in Fig. B synchronized with the top of the screen is added to the CLR terminal. has been added. Therefore, the outputs of the Q terminals of flip-flops FF1 to FF3 are as shown in G to I in the figure, respectively. That is, flip-flops FF1 to FF3 each have a two-dimensional sensor 12.
If a character element appears on the 3rd, 2nd, or 4th line of the screen, the output of the Q terminal is kept at "1" and the output of the terminal is kept at "0" until the screen ends. be.

Furthermore, the outputs of the Q terminals of flip-flops FF1 to FF3 shown in Figures G to I are applied as data to the D terminals of flip-flops FF4 to FF6, and the outputs of the Q terminals of flip-flops FF1 to FF3 shown in Figures G to I are applied to the CK terminals as clock signals, respectively. The clock signal _CK3 shown is applied. Therefore, the Q of flip-flops FF4 and FF5
Signal output from terminal, flip-flop FF
The signals outputted from the terminals 6 are as shown in J to L in the figure, respectively. That is, flip-flops FF4 and FF5 each have two-dimensional sensor 1.
From the third line of 2, the screen following the screen where the character element appeared on the second line, to the third line, the screen where the character element disappeared from the second line, set the output of the Q terminal to "1", and the output of the terminal. The flip-flop FF6 holds the terminal output from the screen following the screen where the character element appears on the 4th line of the two-dimensional sensor 12 to the screen where the character element disappears from the 4th line. is held at "0".

Furthermore, the output signal of the Q terminal of flip-flop FF1, the output signal of the terminal of flip-flop FF4, and the clock signal _CK4 shown in C of the same figure are added to the AND gate AND1, and the output is as shown in M of the same figure. , becomes "1" on the screen (n+1) corresponding to FIG. That is, the output of the AND gate AND1 becomes "1" when a character element appears on the third row of the two-dimensional sensor 12, and is added to the composite feature extraction circuit 16 as a start signal ST.

Also, the output of the AND gate AND1 is applied to the CK terminal of flip-flop FF7, and the output of the Q terminal of flip-flop FF5 is applied to the D terminal, so the output signal from the Q terminal of flip-flop FF7 is as follows. Figure O, respectively.
The result is shown in P, and the AND gate AND3,
Added to AND4. The output signal of the AND gate AND2 shown in FIG. N and the output of the terminal of the flip-flop FF5 are also added to the AND gate AND3.
Since the output signal of the AND gate AND2 shown in N in the same figure and the output of the terminal of the flip-flop FF6 shown in L in the same figure are also added, the AND gate
The outputs of AND3 and AND4 are shown in Q and R in the figure, respectively. Therefore, the output of the OR gate OR becomes "1" on the screen (m+n) corresponding to FIG. 10C, as shown in FIG. Added to 19. The above explanation is for the case where the two-dimensional sensor 12 is moved from left to right, as shown in FIGS. 10A to C. In this case, on the screen where the character element disappears from the third row of the two-dimensional sensor 12, the AND gate is
The output of AND3 becomes "1", and the end signal ED is output from the OR gate OR.

Also, a start signal from the character movement detection circuit 15
A composite feature extraction circuit 16 to which ST, an end circuit ED, a row feature code from the row feature extraction circuit 14, and a composite feature code from the composite feature storage circuit 17 are added includes a row feature code from the row feature extraction circuit 14. A new composite feature code is created by combining the composite feature code from the composite feature storage circuit 17 for the previous screen, which is the screen scanned immediately before.
For example, it has the configuration shown in FIG. In the figure, ROM1 is a read-only memory (hereinafter referred to as memory), GAT is a gate circuit, and FF8
is a flip-flop, and the same reference numerals as in other FIG. 4 represent the same parts. Further, FIG. 14 is an explanatory diagram of the operation of the composite feature extraction circuit 16 and the composite feature storage circuit 17. Furthermore, FIGS. 15A and 15B are diagrams for explaining the processing contents of the composite feature extraction circuit 16, and diagrammatically illustrate changes in the row feature code and composite feature code of a certain plurality of specific lines (3 lines), respectively. This is what is shown.

A start signal ST and an end signal ED are applied to the S terminal and R terminal of the flip-flop FF8, respectively, from the character movement detection circuit 15, and when the start signal becomes "1", the end signal ED becomes "1". That is, from the time when the character element appears on the third row of the two-dimensional sensor 12 until it disappears, the flip-flop FF8 sets its output to "1", turns on the gate circuit GAT, and stores the synthetic feature storage circuit 1.
Memory the previous screen's composite feature code from 7.
This is added to ROM1. The synthetic feature storage circuit 17 is an m-stage (equal to the number of columns of the two-dimensional sensor 12) shift register that operates in accordance with the clock signal _CK5 shown in FIG. are connected in parallel in a number corresponding to the number of bits of the composite feature code. The memory ROM 1 is used to read data written at an address determined by the row feature code from the row feature extraction circuit 14 and the composite feature code from the composite feature storage circuit 17.

Therefore, when the row feature codes L ₀ to L ₁₀ of a specific plurality of rows from the row feature extraction circuit 14 change as shown in FIG. 15A, and the row feature code L ₁ is added, the end signal ED is generated. becomes “1” and the start signal is activated when the row feature code L ₃ is added.
Assuming that ST becomes "1", composite feature codes G ₀ to G ₁₀ shown in FIG. 2B are sequentially obtained. That is, when the end signal ED becomes "1" while the row feature code L ₁ is being added, the gate circuit GAT is turned off, so the memory ROM1 stores the composite feature code of zero and the row feature codes L ₂ and L ₃ . The composite _feature codes G ₂ and G ₃ written in the address determined by Since it is turned on, the memory ROM stores the composite feature code written in the address determined by the row feature code _L4 of the current screen and the corresponding composite feature code _G3 of the previous screen.
G ₄ is read, and in the same manner, a new composite feature code is written to the address defined by the row feature code L _i of the current screen and the composite feature code G _i-1 of the previous screen. The composite feature code is extracted by reading G _i (i is an integer). In addition, in FIG. B, the composite feature code G ₅ and the composite feature code G ₆ , the composite feature code G ₇ and the composite feature code G ₈ , and the composite feature code G ₉ and the composite feature code G ₁₀ are the same, Even if the row feature code changes, if the basic features do not change, this indicates that the same combined feature code is continuously output.

Then, the composite feature code from the composite feature extracting circuit 16 is applied to the composite feature storage circuit 17, shifted by the clock signal _CK5 , and then transferred to the identifying circuit 18.
added to.

The identification circuit 18 identifies characters based on the composite feature code from the composite feature storage circuit 17, and has the configuration shown in FIG. 16, for example, and the ROM 2 is a read-only memory (hereinafter abbreviated as memory). , LAT is a latch circuit. Also, the 17th
The figure is an explanatory diagram of the operation of the identification circuit 18. Also, the first
8A and 8B are diagrams for explaining the processing contents of the identification circuit 18. FIG. This is a diagrammatic representation of the composite feature code obtained based on the code. In addition, in FIGS. A and B, S ₁ to _{S 9} are three of the two-dimensional sensors 12, respectively.
For example, _S1 indicates the part corresponding to the first to third rows of the two-dimensional sensor 12, and _S2 indicates the part corresponding to the second to fourth rows shifted by one row. The corresponding parts are shown. Further, FIG. 19 is a diagram showing the correspondence between an example of a composite feature code and a diagrammatic representation thereof.

The composite feature code from the composite feature storage circuit 17 is applied to the memory ROM2 and together with the output of the latch circuit LAT (e.g. 8 bits) determines the address of the memory ROM2, and the memory ROM2 is written to this determined address. The data (e.g. 8 bits) is read out and applied to the latch circuit LAT.
The latch circuit LAT is cleared by the clear signal CLE shown in FIG. 17 immediately before the synthetic feature codes of the first to third rows are added from the synthetic feature storage circuit 17, and thereafter, the latch circuit LAT is cleared by the clear signal CLE shown in FIG. 2nd line to 4th line
The output data of the memory ROM 2 is latched in accordance with the timing of the clock signal CK ₆ , which becomes "1" every time the composite characteristic code of rows, ..., nth to (n+2)th rows, ... is added. . In addition, the same figure B
As can be seen from FIG. 19, the composite feature codes of parts S ₁ to _{S 9} of are D ₂ , D ₄ , D ₁ , D ₆ , respectively.
_D3 , _D1 , _D1 , _D5 , _D0 .

Therefore, the composite feature code corresponding to the bottom three rows of the two-dimensional sensor (the composite feature code of the S ₉ part)
At the time when is added, data based on the composite feature code from the top to the bottom, that is, the composite feature code from the _S1 part to the _S9 part, is set in the latch circuit LAT. At this time,
By writing data corresponding to the state transition contents such that the identification result is latched in the lower 5 bits of the latch circuit LAT into the memory ROM 2, the data at the time when the bottom three rows of synthetic feature codes are added. Then, the identification result can be set in the lower 5 bits of the latch circuit LAT.

FIG. 20 shows a part of the state transition diagram of the identification circuit 18, and shows the state transition until the numbers "3" and "5" are identified. In the figure, A ₀ is the initial state, A ₁ to _{A 9} are intermediate states, A ₁₀ and A ₁₁ are the final states, and D ₀
~ _D6 indicates the composite feature code of FIG.

Due to the state transition shown in the figure, the number "3",
"5" is identified, but in order to realize such a state transition, the synthetic feature storage circuit 1
It is sufficient to write data corresponding to the state transition contents to the address of the memory ROM 2 determined by the composite characteristic code from 7 and the output data of the latch circuit LAT. For example, in the initial state A ₀ , when the composite feature code D ₀ is added to the memory ROM2, there is no transition from the initial state A ₀ , and when the composite feature code D ₂ is added, there is no transition from the initial state A 0 to the intermediate state Condition A ₁
Therefore, the composite feature code D ₀
and the data corresponding to the initial state A ₀ latched in the latch circuit LAT when _{the initial state A 0 is set} . Initial state A ₀
The data corresponding to the intermediate state A1 may be written to the address determined by the data corresponding to the intermediate state _A1 . Also, in intermediate state _A1 , if composite feature code _D4 is added, the state transitions to intermediate state _A2 , and if composite feature code _D3 is added, it transitions to intermediate state _A6 . Therefore, the data corresponding to the intermediate state A2 is transferred to the address determined by the composite feature code _D4 and the data corresponding to the intermediate state _A1 latched in the latch circuit _LAT at this time. Data corresponding to the _intermediate state _A6 may be written to the address determined by the intermediate state _A6 and the intermediate state A1.

The data set in the lower five bits of the latch circuit LAT of the identification circuit 18, which operates as described above, is applied to the interface circuit 19, and the interface circuit 19 receives the end signal ED from the character movement detection circuit 15 as "1". ”, the output data of the latch circuit LAT is taken in as the identification result.

As described above, in this embodiment, a composite feature code is obtained based on the line feature code, and characters are identified based on the composite feature code. Even when the relative speed changes, characters larger than the field of view of the two-dimensional sensor can be read accurately.

FIG. 21 is a block diagram of another embodiment of the present invention, and the difference from the embodiment shown in FIG. A circuit 25 is provided, and based on the detection result, characters are identified using only the composite feature code of the area where the character element exists, even when there is noise such as dirt.
This makes it possible to accurately identify characters.
In the figure, 26 is a gate circuit, and the same reference numerals as in other parts of FIG. 4 represent the same parts.

First, the operation of the character area detection circuit 25 will be briefly explained with reference to FIGS. 22A and 22B. In addition, in the same figure A, (a) represents noise such as dirt.

For example, if the field of view of the two-dimensional sensor moves from a ₁ to a 2 as shown in Figure A, then the field of view changes from a ₂ to a ₂ .
The composite feature code obtained when moving to is shown in Figure B.
It will be as shown below. Therefore, by detecting composite feature codes that indicate the presence of a character element and counting the number of consecutive composite feature codes that indicate the presence of a character element, it is possible to distinguish between noise and character areas. be able to. In other words, in the case of a character area, the length is greater than a certain value, as shown in b ₁ , and in the case of noise, the length is extremely short, as shown in b ₂ . It is possible to output a detection signal only in this area.

FIG. 23 is a block diagram showing an example of the configuration of the character area detection circuit 25, in which DET detects whether or not it is a composite feature code in which a character element exists;
A character element detector that outputs "1" when a character element is detected, FF9 to FF11 are flip-flops, IN3 and IN4 are inverters, AND5 to
AND7 is an AND gate, CNT1 to CNT4 are counters, and REG1 to REG3 are registers. or,
24 A to 0 and FIGS. 25 A to H are explanatory diagrams of the operation of FIG. 23, and are for the case where a two-dimensional sensor with 64 rows is used.

The counter CNT1 receives a clock signal _CK5 shown in FIG. 24A (same as the clock signal _CK5 shown in FIGS. 14 and 17, and is synchronized with the output processing of the row feature extraction circuit 14). CK ₇ , shown in Figure B, advances in accordance with
The contents are as shown in C of the same figure. That is, counter CNT1
The count value indicates the row number of the top row among the plurality of rows being processed by the composite feature extraction circuit 16.

For example, if the output of the character element detector DET, which detects the presence or absence of a character element based on the composite feature code from the composite feature extraction circuit 16, is as shown in FIG. The output of the device DET is a flip-flop FF9 in which the clock signal _CK5 is added to the clock signal CK.
The signal output from the Q terminal of the register is as shown in E in the same figure, and the outputs of the AND gates AND5 and AND6 are as shown in F and G in the same figure, and the output of the AND gate AND5 is the one shown in the clock terminal CK of the register REG1. , the load terminal LOAD of the counter CNT2, and the reset terminal R of the flip-flop FF10, and the output of the AND gate AND6 is applied to the clock terminal CK of the register REG2 and the AND gate AND7.

Registers REG1 and REG2 each register when the signal applied to the clock terminal CK becomes “1”.
This is to set the count value added from counter CNT1. Therefore, in this case, the contents of registers REG1 and REG2 are respectively H and I in the figure.
It will be as shown below. That is, in register REG1,
The line number where the character element appears is in register REG2
will store the line number where the character element disappeared. In addition, in H and I of the figure, a and b indicate the line numbers set on the previous screen.
Also, the output of the AND gate AND5 is the load terminal.
The counter CNT2 added to LOAD is a 64-decimal down counter that counts down according to the clock signal _CK5 shown in Figure A. When the count value reaches "63", its output is set to "1". In addition to the set terminal S of flip-flop FF10,
Further, when the signal applied from the AND gate AND5 to the load terminal LOAD becomes "1", the data INIT applied to the data terminal D is loaded. Furthermore, the data added to data terminal D
INIT is the minimum height of the character area, i.e. the minimum number of lines in the character area (in this case, for example, 11 lines)
It should correspond to Therefore, the counter
The contents of CNT2 are shown in Figure J, and
The output is shown in K in the figure.

Furthermore, the flip-flop FF10 has the output signal of the counter CNT2 applied to the set terminal S, and the output of the AND gate AND5 applied to the reset terminal R.
The output of the Q terminal of is shown in figure L, and
The output of the AND gate AND7 to which the outputs of the flip-flop FF10, the inverter IN4, and the AND gate AND6 are added becomes the one shown in FIG. M, and is applied to the set terminals S of the registers REG3 and REG4. Furthermore, when the signal applied to the set terminal S becomes "1", the registers REG3 and REG4 set the data from the registers REG1 and REG2 and add it to the data terminal of the counter CNT3, the contents of which are shown in the figure. It will be as shown in N and O. In addition, in N and O in the figure, c and d represent the line numbers set on the previous screen. That is, only when a character element exists consecutively for a certain number of lines (11 lines in this case), the output of the AND gate AND7 becomes "1" in the line where the character element is cut off (in this case, There are character elements in the 2nd to 5th lines and 16th to 28th lines, but the character elements existing in the 2nd to 5th lines are limited to the predetermined number of lines (11
line), it is considered as noise, and the output of the AND gate AND7 does not become "1"), and registers REGG3 and REG4 contain the line number at the top of the character area and the next line at the bottom of the character area, respectively. The line number will be stored.

Further, counters CNT3 and CNT4, whose row numbers set in registers REG3 and REG4 are added to data terminal D, are shown in FIG. 25B, respectively.
It is a 64-decimal down counter that counts down in accordance with the clock signal CK ₅ shown in FIG. 24 (same as the clock signal CK ₅ shown in FIG. 24A),
When the count value reaches ``63'', the output is set to ``1'' and is applied to the set terminal S and reset terminal R of the flip-flop FF11, as well as the clock signal _CK8 synchronized with the screen unit processing shown in C of the same figure. is applied to the load terminal LOAD, the register
This loads the line numbers set in REG3 and REG4. Therefore, counter CNT3,
The contents of CNT4 are as shown in D and E in the figure, respectively, and the outputs of counters CNT3 and CNT4 are as shown in F and G in the figure, respectively. still,
Figure A shows the contents of the counter CNT1.

Therefore, the output of flip-flop FF11 is
As shown in FIG. 21H, the count value of the counter CNT1 becomes "1" only when it is between "16" and "28", that is, only in the character area, and is applied to the gate circuit 26 shown in FIG. Since the gate circuit 26 applies the composite feature code from the composite feature storage circuit 17 to the identification circuit 18 only when the output of the flip-flop FF 11 becomes "1", the identification circuit 18 can read characters without being affected by noise. Also, by using the character area data, the character movement detection circuit 15 can generate and output the start signal ST and end signal ED without the influence of noise. According to this embodiment, characters can be accurately identified even when there is noise such as dirt.

In addition, in this embodiment, down counters CNT3,
I am operating flip-flop FF11 using the data of CNT4, but the counter
A method may also be considered in which the contents of CNT3 and CNT4 are decoded and input to the flip-flop FF11.
For example, a decoder that becomes "1" when the content of counter CNT3 becomes "63" and a counter
Flip-flop each input of the decoder which becomes “1” when the content of CNT4 becomes “1”.
By inputting to FF11, the character area signal becomes "1" in the line numbers "15" to "29", which are wider than the line numbers "16" to "28" where the character element existed on the previous screen, and the character pattern becomes "1" on the next screen. Even if it shifts up and down,
This means that it can be processed as data within the character area.

Further, in this embodiment, the character movement detection circuit 15 and the character area detection circuit 25 are implemented by flip-flop circuits,
Although it is constructed using an AND circuit or the like, a construction method using a sequential circuit including a read-only memory and a latch circuit is also conceivable.

As explained above, the present invention extracts a row feature code based on a binary signal, extracts a composite feature code based on the row feature code, and further identifies characters based on the composite feature code. Therefore, even when the relative speed between the two-dimensional sensor and the paper on which the characters are written is not constant, there is an advantage that characters larger than the field of view of the two-dimensional sensor can be accurately read. Further, since the present invention is provided with a character area detection circuit and identifies characters using only the composite feature code of the character area,
This has the advantage that characters can be read accurately even if there is noise such as dirt.

[Brief explanation of drawings]

Figures 1 and 2 A and B are explanatory diagrams of the conventional example, and Figure 3
Figures A and B are diagrams for explaining the principle of the present invention, Figure 4 is a block diagram of an embodiment of the present invention, Figure 5 is a diagram for explaining a two-dimensional sensor, and Figure 6 is a block diagram of the row feature extraction circuit 14. 7 is an explanatory diagram of the operation of FIG. 6, FIG. 8 is a diagram showing an example of correspondence between a row feature code and a black and white pattern, FIG. 9 is a state transition diagram of the row feature extraction circuit 14, and FIG. A to C are diagrams for explaining the operation of the character movement detection circuit 15, FIG. 11 is a block diagram of the character movement detection circuit 15, and FIGS.
Figure 13 is an explanatory diagram of the operation of the composite feature extraction circuit 1.
6, FIG. 14 is an explanatory diagram of the operation of FIG. 13, FIGS. 15A and B are diagrams for explaining the processing contents of the composite feature extraction circuit 16, and FIG. 16 is a block diagram of the identification circuit 18. Figure 17 is an explanatory diagram of the operation in Figure 16, Figures 18A and B are diagrams for explaining the processing contents of the identification circuit 18, Figure 19 is the correspondence between the composite feature code and its diagrammatic representation. Figure 2 showing
0 is a state transition diagram of the identification circuit 18, FIG. 21 is a block diagram of another embodiment of the present invention, and FIG. 22A,
B is a diagram for explaining the operation of the character area detection circuit 25, FIG. 23 is a block diagram of the character area detection circuit 25, FIGS.
It is an explanatory diagram of the operation of the figure. 1 is an optical system, 2 and 12 are two-dimensional sensors, 3, 1
3 is a binarization circuit, 4 and 18 are identification circuits, 5 is paper, 6 is a character, 14 is a line feature extraction circuit, 15 is a character movement detection circuit, 16 is a composite feature extraction circuit, 17
19 is an interface circuit, 20 is a parallel-to-serial converter, 21 and 22 are shift registers, 23, ROM1 and ROM2 are memories,
24, LAT is a latch circuit, 25 is a character area detection circuit, 26, GAT is a gate circuit, FF1 to FF1
1 is a flip-flop, AND1 to AND7 are AND gates, OR1 is an OR gate, IN1 to IN4 are inverters, DET is a character element detector, CNT1 to
CNT4 is a counter, and REG1 to REG4 are registers.

Claims (1)

[Claims] 1. A two-dimensional sensor in which photoelectric conversion elements are two-dimensionally arranged, a binarization circuit that converts an output signal of the two-dimensional sensor into a binary signal, and a binary signal from the binarization circuit. a line feature extraction circuit that sequentially extracts line feature codes representing features of the shape of a plurality of lines of a character image formed on the light receiving surface of the two-dimensional sensor over the entire screen based on the value signal; Synthesize the row feature code from the feature extraction circuit and the composite feature code from the composite feature storage circuit in which the composite feature code for the immediately previous scanned screen is stored to obtain the composite feature code for the current screen. When a character image appears at a predetermined position on the light-receiving surface of the two-dimensional sensor, a start signal is generated based on the binary signal from the composite feature extraction circuit and the binarization circuit, which is extracted and added to the composite feature storage circuit. a character movement detection circuit that outputs an end signal when the character image disappears from the predetermined position; and an identification circuit that identifies the character based on the composite feature code from the composite feature storage circuit; After the signal is output until the end signal is output, the composite feature circuit performs extraction processing of the composite feature code, and also extracts the composite feature code from the output of the identification circuit on the screen where the end signal is output. An optical character reading method characterized in that the identification results are: 2. A two-dimensional sensor in which photoelectric conversion elements are arranged two-dimensionally, a binarization circuit that converts the output signal of the two-dimensional sensor into a binary signal, based on the binary signal from the binarization circuit, a line feature extraction circuit that sequentially extracts line feature codes representing features of the shape of each of a plurality of lines of a character image formed on the light receiving surface of the two-dimensional sensor over the entire screen; a line from the line feature extraction circuit; A composite feature code of the current screen is extracted by combining the corresponding feature code with a composite feature code from a composite feature storage circuit in which the composite feature code of the immediately previous scanned screen is stored, and the composite feature code of the current screen is extracted. A synthetic feature extraction circuit added to the circuit outputs a start signal when a character image appears at a predetermined position on the light-receiving surface of the two-dimensional sensor based on the binary signal from the binarization circuit, and starts processing from the predetermined position. When the character image disappears,
a character movement detection circuit that outputs an end signal; an identification circuit that identifies characters based on the composite feature code from the composite feature storage circuit; and a character movement detection circuit that identifies characters based on the composite feature code from the composite feature extraction circuit. A character area detection circuit detecting a character area is provided, the character movement detection circuit performs an end signal detection process only when the character area detection circuit detects a character area, and the synthetic feature extraction circuit detects the start signal. The process of extracting a composite feature code is performed from when the character area detection circuit detects a character area until the end signal is output, and the identification circuit performs the identification process only when the character area detection circuit detects a character area. An optical character reading system characterized in that the output of the identification circuit on the screen on which the end signal is output from the detection circuit is used as the identification result.